[{"id":1765498,"web_url":"http://patchwork.ozlabs.org/comment/1765498/","msgid":"<20170908182442.34054758@bahia>","list_archive_url":null,"date":"2017-09-08T16:24:42","subject":"Re: [Qemu-devel] [Qemu-ppc] [PATCH 1/3] ppc/xive: fix\n\tOV5_XIVE_EXPLOIT bits","submitter":{"id":69178,"url":"http://patchwork.ozlabs.org/api/people/69178/","name":"Greg Kurz","email":"groug@kaod.org"},"content":"Shouldn't the patch title mention spapr instead of ppc/xive ?\n\nOn Fri, 8 Sep 2017 16:33:42 +0200\nCédric Le Goater wrote:\n\n> On POWER9, the Client Architecture Support (CAS) negotiation process\n> determines whether the guest operates in XIVE Legacy compatibility or\n> in XIVE exploitation mode. Now that we have initial guest support for\n> the XIVE interrupt controller, let's fix the bits definition which have\n> evolved in the latest specs.\n> \n> The platform advertises the XIVE Exploitation Mode support using the\n> property \"ibm,arch-vec-5-platform-support-vec-5\", byte 23 bits 0-1 :\n> \n> - 0b00 XIVE legacy mode Only\n> - 0b01 XIVE exploitation mode Only\n> - 0b10 XIVE legacy or exploitation mode\n> \n> The OS asks for XIVE Exploitation Mode support using the property\n> \"ibm,architecture-vec-5\", byte 23 bits 0-1:\n> \n> - 0b00 XIVE legacy mode Only\n> - 0b01 XIVE exploitation mode Only\n> \n> Signed-off-by: Cédric Le Goater \n> ---\n> hw/ppc/spapr.c | 2 +-\n> include/hw/ppc/spapr_ovec.h | 3 ++-\n> 2 files changed, 3 insertions(+), 2 deletions(-)\n> \n> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c\n> index cec441cbf48d..3e3ff1fbc988 100644\n> --- a/hw/ppc/spapr.c\n> +++ b/hw/ppc/spapr.c\n> @@ -914,7 +914,7 @@ static void spapr_dt_ov5_platform_support(void *fdt, int chosen)\n> PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu);\n> \n> char val[2 * 4] = {\n> - 23, 0x00, /* Xive mode: 0 = legacy (as in ISA 2.7), 1 = Exploitation */\n> + 23, 0x00, /* Xive mode, filled in below. */\n> 24, 0x00, /* Hash/Radix, filled in below. */\n> 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */\n> 26, 0x40, /* Radix options: GTSE == yes. */\n> diff --git a/include/hw/ppc/spapr_ovec.h b/include/hw/ppc/spapr_ovec.h\n> index 9edfa5ff7530..bf25e5d954a1 100644\n> --- a/include/hw/ppc/spapr_ovec.h\n> +++ b/include/hw/ppc/spapr_ovec.h\n> @@ -51,7 +51,8 @@ typedef struct sPAPROptionVector sPAPROptionVector;\n> #define OV5_FORM1_AFFINITY OV_BIT(5, 0)\n> #define OV5_HP_EVT OV_BIT(6, 5)\n> #define OV5_HPT_RESIZE OV_BIT(6, 7)\n> -#define OV5_XIVE_EXPLOIT OV_BIT(23, 7)\n> +#define OV5_XIVE_BOTH OV_BIT(23, 0)\n> +#define OV5_XIVE_EXPLOIT OV_BIT(23, 1) /* 1=exploitation 0=legacy */\n> \n> /* ISA 3.00 MMU features: */\n> #define OV5_MMU_BOTH OV_BIT(24, 0) /* Radix and hash */","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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Fri, 08 Sep 2017 12:24:59 -0400","from player714.ha.ovh.net (b6.ovh.net [213.186.33.56])\n\tby mo177.mail-out.ovh.net (Postfix) with ESMTP id 052147A3DC\n\tfor ; Fri, 8 Sep 2017 18:24:51 +0200 (CEST)","from bahia (gar31-1-82-66-74-139.fbx.proxad.net [82.66.74.139])\n\t(Authenticated sender: groug@kaod.org)\n\tby player714.ha.ovh.net (Postfix) with ESMTPSA id E3BBA3C006B;\n\tFri, 8 Sep 2017 18:24:43 +0200 (CEST)"],"Date":"Fri, 8 Sep 2017 18:24:42 +0200","From":"Greg Kurz ","To":"=?utf-8?q?C=C3=A9dric?= Le Goater ","Message-ID":"<20170908182442.34054758@bahia>","In-Reply-To":"<20170908143344.12960-2-clg@kaod.org>","References":"<20170908143344.12960-1-clg@kaod.org>\n\t<20170908143344.12960-2-clg@kaod.org>","X-Mailer":"Claws Mail 3.14.1 (GTK+ 2.24.31; x86_64-redhat-linux-gnu)","MIME-Version":"1.0","Content-Type":"multipart/signed; micalg=pgp-sha1;\n\tboundary=\"Sig_/b=i3mL.1RU8aTkGuI0PwyWH\";\n\tprotocol=\"application/pgp-signature\"","X-Ovh-Tracer-Id":"14146650857743423883","X-VR-SPAMSTATE":"OK","X-VR-SPAMSCORE":"-100","X-VR-SPAMCAUSE":"gggruggvucftvghtrhhoucdtuddrfeelledrfeeggddutddvucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]","X-Received-From":"46.105.72.238","Subject":"Re: [Qemu-devel] [Qemu-ppc] [PATCH 1/3] ppc/xive: fix\n\tOV5_XIVE_EXPLOIT bits","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"David Gibson , qemu-ppc@nongnu.org,\n\tqemu-devel@nongnu.org, Michael Roth ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1765895,"web_url":"http://patchwork.ozlabs.org/comment/1765895/","msgid":"<20170910031655.GX2735@umbus.fritz.box>","list_archive_url":null,"date":"2017-09-10T03:16:55","subject":"Re: [Qemu-devel] [PATCH 1/3] ppc/xive: fix OV5_XIVE_EXPLOIT bits","submitter":{"id":47,"url":"http://patchwork.ozlabs.org/api/people/47/","name":"David Gibson","email":"david@gibson.dropbear.id.au"},"content":"On Fri, Sep 08, 2017 at 04:33:42PM +0200, Cédric Le Goater wrote:\n> On POWER9, the Client Architecture Support (CAS) negotiation process\n> determines whether the guest operates in XIVE Legacy compatibility or\n> in XIVE exploitation mode. Now that we have initial guest support for\n> the XIVE interrupt controller, let's fix the bits definition which have\n> evolved in the latest specs.\n> \n> The platform advertises the XIVE Exploitation Mode support using the\n> property \"ibm,arch-vec-5-platform-support-vec-5\", byte 23 bits 0-1 :\n> \n> - 0b00 XIVE legacy mode Only\n> - 0b01 XIVE exploitation mode Only\n> - 0b10 XIVE legacy or exploitation mode\n> \n> The OS asks for XIVE Exploitation Mode support using the property\n> \"ibm,architecture-vec-5\", byte 23 bits 0-1:\n> \n> - 0b00 XIVE legacy mode Only\n> - 0b01 XIVE exploitation mode Only\n> \n> Signed-off-by: Cédric Le Goater \n\nApplied to ppc-for-2.11, thanks.\n\n> ---\n> hw/ppc/spapr.c | 2 +-\n> include/hw/ppc/spapr_ovec.h | 3 ++-\n> 2 files changed, 3 insertions(+), 2 deletions(-)\n> \n> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c\n> index cec441cbf48d..3e3ff1fbc988 100644\n> --- a/hw/ppc/spapr.c\n> +++ b/hw/ppc/spapr.c\n> @@ -914,7 +914,7 @@ static void spapr_dt_ov5_platform_support(void *fdt, int chosen)\n> PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu);\n> \n> char val[2 * 4] = {\n> - 23, 0x00, /* Xive mode: 0 = legacy (as in ISA 2.7), 1 = Exploitation */\n> + 23, 0x00, /* Xive mode, filled in below. */\n> 24, 0x00, /* Hash/Radix, filled in below. */\n> 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */\n> 26, 0x40, /* Radix options: GTSE == yes. */\n> diff --git a/include/hw/ppc/spapr_ovec.h b/include/hw/ppc/spapr_ovec.h\n> index 9edfa5ff7530..bf25e5d954a1 100644\n> --- a/include/hw/ppc/spapr_ovec.h\n> +++ b/include/hw/ppc/spapr_ovec.h\n> @@ -51,7 +51,8 @@ typedef struct sPAPROptionVector sPAPROptionVector;\n> #define OV5_FORM1_AFFINITY OV_BIT(5, 0)\n> #define OV5_HP_EVT OV_BIT(6, 5)\n> #define OV5_HPT_RESIZE OV_BIT(6, 7)\n> -#define OV5_XIVE_EXPLOIT OV_BIT(23, 7)\n> +#define OV5_XIVE_BOTH OV_BIT(23, 0)\n> +#define OV5_XIVE_EXPLOIT OV_BIT(23, 1) /* 1=exploitation 0=legacy */\n> \n> /* ISA 3.00 MMU features: */\n> #define OV5_MMU_BOTH OV_BIT(24, 0) /* Radix and hash */","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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