[{"id":1765382,"web_url":"http://patchwork.ozlabs.org/comment/1765382/","msgid":"<20170908135716.GB25219@lunn.ch>","list_archive_url":null,"date":"2017-09-08T13:57:16","subject":"Re: [PATCH net-next 3/3] net: phy: realtek: add RTL8201F phy-id and\n\tfunctions","submitter":{"id":13608,"url":"http://patchwork.ozlabs.org/api/people/13608/","name":"Andrew Lunn","email":"andrew@lunn.ch"},"content":"On Fri, Sep 08, 2017 at 10:02:11PM +0900, Kunihiko Hayashi wrote:\n> From: Jassi Brar <jaswinder.singh@linaro.org>\n> \n> Add RTL8201F phy-id and the related functions to the driver.\n> \n> The original patch is as follows:\n> https://patchwork.kernel.org/patch/2538341/\n> \n> Signed-off-by: Jongsung Kim <neidhard.kim@lge.com>\n> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>\n> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>\n\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\n\n    Andrew","headers":{"Return-Path":"<netdev-owner@vger.kernel.org>","X-Original-To":"patchwork-incoming@ozlabs.org","Delivered-To":"patchwork-incoming@ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=netdev-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xpf5s0NPVz9sCZ\n\tfor <patchwork-incoming@ozlabs.org>;\n\tFri,  8 Sep 2017 23:57:37 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752482AbdIHN5Y (ORCPT <rfc822;patchwork-incoming@ozlabs.org>);\n\tFri, 8 Sep 2017 09:57:24 -0400","from vps0.lunn.ch ([178.209.37.122]:32994 \"EHLO vps0.lunn.ch\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1750966AbdIHN5X (ORCPT <rfc822;netdev@vger.kernel.org>);\n\tFri, 8 Sep 2017 09:57:23 -0400","from andrew by vps0.lunn.ch with local (Exim 4.84_2)\n\t(envelope-from <andrew@lunn.ch>)\n\tid 1dqJmW-00075F-RN; Fri, 08 Sep 2017 15:57:16 +0200"],"Date":"Fri, 8 Sep 2017 15:57:16 +0200","From":"Andrew Lunn <andrew@lunn.ch>","To":"Kunihiko Hayashi <hayashi.kunihiko@socionext.com>","Cc":"netdev@vger.kernel.org, \"David S. Miller\" <davem@davemloft.net>,\n\tFlorian Fainelli <f.fainelli@gmail.com>,\n\tRob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>,\n\tlinux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,\n\tdevicetree@vger.kernel.org,\n\tMasahiro Yamada <yamada.masahiro@socionext.com>,\n\tMasami Hiramatsu <masami.hiramatsu@linaro.org>,\n\tJassi Brar <jaswinder.singh@linaro.org>,\n\tJongsung Kim <neidhard.kim@lge.com>","Subject":"Re: [PATCH net-next 3/3] net: phy: realtek: add RTL8201F phy-id and\n\tfunctions","Message-ID":"<20170908135716.GB25219@lunn.ch>","References":"<1504875731-3680-1-git-send-email-hayashi.kunihiko@socionext.com>\n\t<1504875731-3680-4-git-send-email-hayashi.kunihiko@socionext.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<1504875731-3680-4-git-send-email-hayashi.kunihiko@socionext.com>","User-Agent":"Mutt/1.5.23 (2014-03-12)","Sender":"netdev-owner@vger.kernel.org","Precedence":"bulk","List-ID":"<netdev.vger.kernel.org>","X-Mailing-List":"netdev@vger.kernel.org"}},{"id":1765580,"web_url":"http://patchwork.ozlabs.org/comment/1765580/","msgid":"<4173a876-3cff-205a-ce87-ce049f419aa0@gmail.com>","list_archive_url":null,"date":"2017-09-08T18:51:34","subject":"Re: [PATCH net-next 3/3] net: phy: realtek: add RTL8201F phy-id and\n\tfunctions","submitter":{"id":2800,"url":"http://patchwork.ozlabs.org/api/people/2800/","name":"Florian Fainelli","email":"f.fainelli@gmail.com"},"content":"On 09/08/2017 06:02 AM, Kunihiko Hayashi wrote:\n> From: Jassi Brar <jaswinder.singh@linaro.org>\n> \n> Add RTL8201F phy-id and the related functions to the driver.\n> \n> The original patch is as follows:\n> https://patchwork.kernel.org/patch/2538341/\n> \n> Signed-off-by: Jongsung Kim <neidhard.kim@lge.com>\n> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>\n> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>\n> ---\n>  drivers/net/phy/realtek.c | 45 +++++++++++++++++++++++++++++++++++++++++++++\n>  1 file changed, 45 insertions(+)\n> \n> diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c\n> index 9cbe645..d9974ce 100644\n> --- a/drivers/net/phy/realtek.c\n> +++ b/drivers/net/phy/realtek.c\n> @@ -29,10 +29,23 @@\n>  #define RTL8211F_PAGE_SELECT\t0x1f\n>  #define RTL8211F_TX_DELAY\t0x100\n>  \n> +#define RTL8201F_ISR\t\t0x1e\n> +#define RTL8201F_PAGE_SELECT\t0x1f\n\nWe have a page select register define for the RTL8211F right above, so\nsurely we can make that a common definition?\n\n> +#define RTL8201F_IER\t\t0x13\n> +\n>  MODULE_DESCRIPTION(\"Realtek PHY driver\");\n>  MODULE_AUTHOR(\"Johnson Leung\");\n>  MODULE_LICENSE(\"GPL\");\n>  \n> +static int rtl8201_ack_interrupt(struct phy_device *phydev)\n> +{\n> +\tint err;\n> +\n> +\terr = phy_read(phydev, RTL8201F_ISR);\n> +\n> +\treturn (err < 0) ? err : 0;\n> +}\n> +\n>  static int rtl821x_ack_interrupt(struct phy_device *phydev)\n>  {\n>  \tint err;\n> @@ -54,6 +67,25 @@ static int rtl8211f_ack_interrupt(struct phy_device *phydev)\n>  \treturn (err < 0) ? err : 0;\n>  }\n>  \n> +static int rtl8201_config_intr(struct phy_device *phydev)\n> +{\n> +\tint err;\n> +\n> +\t/* switch to page 7 */\n> +\tphy_write(phydev, RTL8201F_PAGE_SELECT, 0x7);\n> +\n> +\tif (phydev->interrupts == PHY_INTERRUPT_ENABLED)\n> +\t\terr = phy_write(phydev, RTL8201F_IER,\n> +\t\t\t\tBIT(13) | BIT(12) | BIT(11));\n\nCan you detail what bits 11, 12 and 13 do? Do they correspond to link,\nduplex and pause changes by any chance?\n\n> +\telse\n> +\t\terr = phy_write(phydev, RTL8201F_IER, 0);\n> +\n> +\t/* restore to default page 0 */\n> +\tphy_write(phydev, RTL8201F_PAGE_SELECT, 0x0);\n> +\n> +\treturn err;\n> +}\n> +\n\nOther than that, LGTM:\n\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\n\n>  static int rtl8211b_config_intr(struct phy_device *phydev)\n>  {\n>  \tint err;\n> @@ -129,6 +161,18 @@ static struct phy_driver realtek_drvs[] = {\n>  \t\t.config_aneg    = &genphy_config_aneg,\n>  \t\t.read_status    = &genphy_read_status,\n>  \t}, {\n> +\t\t.phy_id\t\t= 0x001cc816,\n> +\t\t.name\t\t= \"RTL8201F 10/100Mbps Ethernet\",\n> +\t\t.phy_id_mask\t= 0x001fffff,\n> +\t\t.features\t= PHY_BASIC_FEATURES,\n> +\t\t.flags\t\t= PHY_HAS_INTERRUPT,\n> +\t\t.config_aneg\t= &genphy_config_aneg,\n> +\t\t.read_status\t= &genphy_read_status,\n> +\t\t.ack_interrupt\t= &rtl8201_ack_interrupt,\n> +\t\t.config_intr\t= &rtl8201_config_intr,\n> +\t\t.suspend\t= genphy_suspend,\n> +\t\t.resume\t\t= genphy_resume,\n> +\t}, {\n>  \t\t.phy_id\t\t= 0x001cc912,\n>  \t\t.name\t\t= \"RTL8211B Gigabit Ethernet\",\n>  \t\t.phy_id_mask\t= 0x001fffff,\n> @@ -181,6 +225,7 @@ static struct phy_driver realtek_drvs[] = {\n>  module_phy_driver(realtek_drvs);\n>  \n>  static struct mdio_device_id __maybe_unused realtek_tbl[] = {\n> +\t{ 0x001cc816, 0x001fffff },\n>  \t{ 0x001cc912, 0x001fffff },\n>  \t{ 0x001cc914, 0x001fffff },\n>  \t{ 0x001cc915, 0x001fffff },\n>","headers":{"Return-Path":"<netdev-owner@vger.kernel.org>","X-Original-To":"patchwork-incoming@ozlabs.org","Delivered-To":"patchwork-incoming@ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=netdev-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"rkpThpcT\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xpmdQ0ZjKz9t2c\n\tfor <patchwork-incoming@ozlabs.org>;\n\tSat,  9 Sep 2017 04:51:54 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1756832AbdIHSvl (ORCPT <rfc822;patchwork-incoming@ozlabs.org>);\n\tFri, 8 Sep 2017 14:51:41 -0400","from mail-qt0-f194.google.com ([209.85.216.194]:34681 \"EHLO\n\tmail-qt0-f194.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1756615AbdIHSvj (ORCPT\n\t<rfc822;netdev@vger.kernel.org>); Fri, 8 Sep 2017 14:51:39 -0400","by mail-qt0-f194.google.com with SMTP id q8so2058200qtb.1;\n\tFri, 08 Sep 2017 11:51:39 -0700 (PDT)","from [10.112.156.244] ([192.19.255.250])\n\tby smtp.googlemail.com with ESMTPSA id\n\t48sm1719446qty.29.2017.09.08.11.51.35\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tFri, 08 Sep 2017 11:51:37 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=gmail.com; s=20161025;\n\th=subject:to:cc:references:from:message-id:date:user-agent\n\t:mime-version:in-reply-to:content-language:content-transfer-encoding; \n\tbh=xepZjv61IGLdNaJ4J7OwBulLfoZuDkxQ+i9irm7V9Lk=;\n\tb=rkpThpcTmVldruCuYi+dcATcYt+uTH9s0I81weJeGi29nXFekT8kFILnpryEWUYCoF\n\tYBwYSkryZuc7B5SGfD0PH3ILNCAB6JeQz6izgWys+RFpUJBH5co3Y0UEF58I+zkULV4E\n\tBb5l5Lxm1baAE1sVS7LtX/dKDsqJB4Hjv1yXXMo4QYRuiRf9l0VeCK1AxcZOKSOMbf6N\n\td6dftmbulJzu+1KW/WUWHJtU/pInCX+lhL/c9hakDzRTYmhAsFYPZfxP7c2h9zO0fK6V\n\tcwcRsNopavdMlJZPUma9DLTCzMO04VU2S10+lZd3Mp/2ZxlfaJys2ealqdsI9g/23CN/\n\tCAqQ==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:subject:to:cc:references:from:message-id:date\n\t:user-agent:mime-version:in-reply-to:content-language\n\t:content-transfer-encoding;\n\tbh=xepZjv61IGLdNaJ4J7OwBulLfoZuDkxQ+i9irm7V9Lk=;\n\tb=gU84tJG+BG9MM73d2mFs6JrAr3OofRPDTkQrC029upySLKt+eOTO8L2Zf/JHQdI+hK\n\tpF7o+dC5sU70gf6xz7xmZqlHjbIu/4vfYETPhvqUFNjOFfFeho4VFnCBnsy6TthmtZMV\n\tVAY03u6piGI0blT+nLoJJVjET8ySKFmjgCTO7fshp3HfDR7ZJsQJpEScd39qhF/a3wG6\n\tA+eKq790hrKUiS9WVDnSgjMDDyo1HVw1O6vPGbWqkdvLVjP80ZIem75XG4p34U7ymX7G\n\tbJTsnt1uZF1P4gc6lEyhYHxrm1+IF938XDxoWRuQSrTkrr6TTtFNE29EdyvBm8o9HIai\n\tVrmA==","X-Gm-Message-State":"AHPjjUjLvWiqiR1ddGIR3sPuSNCWrUCdZWpPpkDYvLVHKb9QAMwCgsSc\n\teBctsUmT9GGsow==","X-Google-Smtp-Source":"AOwi7QAuPVLqmetSPm+aqIMWa021iGvrSOjD+xW2KB/UUMiU036hnukiP+JQoMasTM52anMY3OrAaA==","X-Received":"by 10.237.43.39 with SMTP id p36mr5899744qtd.154.1504896698543; \n\tFri, 08 Sep 2017 11:51:38 -0700 (PDT)","Subject":"Re: [PATCH net-next 3/3] net: phy: realtek: add RTL8201F phy-id and\n\tfunctions","To":"Kunihiko Hayashi <hayashi.kunihiko@socionext.com>,\n\tnetdev@vger.kernel.org, \"David S. Miller\" <davem@davemloft.net>,\n\tAndrew Lunn <andrew@lunn.ch>","Cc":"Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>,\n\tlinux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,\n\tdevicetree@vger.kernel.org,\n\tMasahiro Yamada <yamada.masahiro@socionext.com>,\n\tMasami Hiramatsu <masami.hiramatsu@linaro.org>,\n\tJassi Brar <jaswinder.singh@linaro.org>,\n\tJongsung Kim <neidhard.kim@lge.com>","References":"<1504875731-3680-1-git-send-email-hayashi.kunihiko@socionext.com>\n\t<1504875731-3680-4-git-send-email-hayashi.kunihiko@socionext.com>","From":"Florian Fainelli <f.fainelli@gmail.com>","Message-ID":"<4173a876-3cff-205a-ce87-ce049f419aa0@gmail.com>","Date":"Fri, 8 Sep 2017 11:51:34 -0700","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"<1504875731-3680-4-git-send-email-hayashi.kunihiko@socionext.com>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","Sender":"netdev-owner@vger.kernel.org","Precedence":"bulk","List-ID":"<netdev.vger.kernel.org>","X-Mailing-List":"netdev@vger.kernel.org"}},{"id":1765685,"web_url":"http://patchwork.ozlabs.org/comment/1765685/","msgid":"<CAJe_ZhciWBhw5npxEjTUGw2duS7DSfhzP5nzAOy_ig4-1XcPWw@mail.gmail.com>","list_archive_url":null,"date":"2017-09-09T03:33:05","subject":"Re: [PATCH net-next 3/3] net: phy: realtek: add RTL8201F phy-id and\n\tfunctions","submitter":{"id":10481,"url":"http://patchwork.ozlabs.org/api/people/10481/","name":"Jassi Brar","email":"jaswinder.singh@linaro.org"},"content":"On 9 September 2017 at 00:21, Florian Fainelli <f.fainelli@gmail.com> wrote:\n> On 09/08/2017 06:02 AM, Kunihiko Hayashi wrote:\n>> From: Jassi Brar <jaswinder.singh@linaro.org>\n>>\n>> Add RTL8201F phy-id and the related functions to the driver.\n>>\n>> The original patch is as follows:\n>> https://patchwork.kernel.org/patch/2538341/\n>>\n>> Signed-off-by: Jongsung Kim <neidhard.kim@lge.com>\n>> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>\n>> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>\n>> ---\n>>  drivers/net/phy/realtek.c | 45 +++++++++++++++++++++++++++++++++++++++++++++\n>>  1 file changed, 45 insertions(+)\n>>\n>> diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c\n>> index 9cbe645..d9974ce 100644\n>> --- a/drivers/net/phy/realtek.c\n>> +++ b/drivers/net/phy/realtek.c\n>> @@ -29,10 +29,23 @@\n>>  #define RTL8211F_PAGE_SELECT 0x1f\n>>  #define RTL8211F_TX_DELAY    0x100\n>>\n>> +#define RTL8201F_ISR         0x1e\n>> +#define RTL8201F_PAGE_SELECT 0x1f\n>\n> We have a page select register define for the RTL8211F right above, so\n> surely we can make that a common definition?\n>\nThat is just for the sake of consistency.\nI mean RTL8211 wouldn't look neat among everything else RTL8201.\n\nAlso the page-select offsets just _happen_ to be same value...\nRTL8211E_INER_LINK_STATUS and RTL8211F_INER_LINK_STATUS are very\ndifferent.\n\n>> +#define RTL8201F_IER         0x13\n>> +\n>>  MODULE_DESCRIPTION(\"Realtek PHY driver\");\n>>  MODULE_AUTHOR(\"Johnson Leung\");\n>>  MODULE_LICENSE(\"GPL\");\n>>\n>> +static int rtl8201_ack_interrupt(struct phy_device *phydev)\n>> +{\n>> +     int err;\n>> +\n>> +     err = phy_read(phydev, RTL8201F_ISR);\n>> +\n>> +     return (err < 0) ? err : 0;\n>> +}\n>> +\n>>  static int rtl821x_ack_interrupt(struct phy_device *phydev)\n>>  {\n>>       int err;\n>> @@ -54,6 +67,25 @@ static int rtl8211f_ack_interrupt(struct phy_device *phydev)\n>>       return (err < 0) ? err : 0;\n>>  }\n>>\n>> +static int rtl8201_config_intr(struct phy_device *phydev)\n>> +{\n>> +     int err;\n>> +\n>> +     /* switch to page 7 */\n>> +     phy_write(phydev, RTL8201F_PAGE_SELECT, 0x7);\n>> +\n>> +     if (phydev->interrupts == PHY_INTERRUPT_ENABLED)\n>> +             err = phy_write(phydev, RTL8201F_IER,\n>> +                             BIT(13) | BIT(12) | BIT(11));\n>\n> Can you detail what bits 11, 12 and 13 do? Do they correspond to link,\n> duplex and pause changes by any chance?\n>\nSorry no idea. The datasheet would say, and other functions too use\nsuch magic values.\n\n>> +     else\n>> +             err = phy_write(phydev, RTL8201F_IER, 0);\n>> +\n>> +     /* restore to default page 0 */\n>> +     phy_write(phydev, RTL8201F_PAGE_SELECT, 0x0);\n>> +\n>> +     return err;\n>> +}\n>> +\n>\n> Other than that, LGTM:\n>\n> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>\n>\nThank you.","headers":{"Return-Path":"<netdev-owner@vger.kernel.org>","X-Original-To":"patchwork-incoming@ozlabs.org","Delivered-To":"patchwork-incoming@ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=netdev-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)","ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"BW4zjBVV\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xq0C91H3vz9s8J\n\tfor <patchwork-incoming@ozlabs.org>;\n\tSat,  9 Sep 2017 13:33:25 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1757378AbdIIDdK (ORCPT <rfc822;patchwork-incoming@ozlabs.org>);\n\tFri, 8 Sep 2017 23:33:10 -0400","from mail-oi0-f48.google.com ([209.85.218.48]:34145 \"EHLO\n\tmail-oi0-f48.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1753201AbdIIDdG (ORCPT\n\t<rfc822;netdev@vger.kernel.org>); Fri, 8 Sep 2017 23:33:06 -0400","by mail-oi0-f48.google.com with SMTP id l74so19748610oih.1\n\tfor <netdev@vger.kernel.org>; Fri, 08 Sep 2017 20:33:06 -0700 (PDT)","by 10.157.47.238 with HTTP; Fri, 8 Sep 2017 20:33:05 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=mime-version:in-reply-to:references:from:date:message-id:subject:to\n\t:cc; bh=6aioD9XmeXlf/9WNC59rOoWvrVSqmaepWBP6i2fCxQM=;\n\tb=BW4zjBVVrWuvP8OEjSkKBOqbkm5PLa6yHNhnKj3tISlKjL88EjcVBRlpTXDx9DjmaM\n\tMN8OeIHBplh62QB61U918isSvHbeuI0LQa4/Lg2lf2A1TLlUJ0dX6lwe4T08uL9BKHQl\n\tXUMl6pUELVLAKP0kt7yo4gy5waIs+fFxFObOs=","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:mime-version:in-reply-to:references:from:date\n\t:message-id:subject:to:cc;\n\tbh=6aioD9XmeXlf/9WNC59rOoWvrVSqmaepWBP6i2fCxQM=;\n\tb=gVy0cdq5Vjrre8nfyTOxG8vH51uoRb+WfCY4h0w8UPlM0Y+2uoQs3AjVDtqOYVyZFW\n\t/yfksPEZpkm/HgpUiQ3mA6JR4H/swXcFhVDrJBFEnCEUMYi0pt0ZqAPB0wnCLc9/JMhD\n\tBKBlRxWRZbS96uRi8UfGbkdGikUZJI6M/kwdRsmvVIkJM2wKVhkU7iuHD9tK0GyPNauY\n\tLt2vSe7CNRuKQay/kQjINGeLwqUQL9aoTkVfwX8hdogFzJrJI6e1b8cs3R78PgJEj9/k\n\tgOuR64JQ3slmqYFdfkBQxwbHYJ9r37K9gBTD5SVMp7nSEH0J40Qczw5yVDFF4MPs1sqa\n\tU3CQ==","X-Gm-Message-State":"AHPjjUj8w9yNFxxrV6YYywBryBqYm38TGue1qgZsmmZcZBBzRqbZtN4g\n\t3WzoX8REXURHjFOuG1R8Xe221nLq2ATT","X-Google-Smtp-Source":"AOwi7QCHxINyjbjiN9P1hANJb5Z7VOVD5YqihlSuCGWFJa5geSXgselAkThi2Mtz8c1T/sAELOrrPEo0oTLZ/crlIZU=","X-Received":"by 10.202.206.1 with SMTP id e1mr4652021oig.150.1504927985694;\n\tFri, 08 Sep 2017 20:33:05 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"<4173a876-3cff-205a-ce87-ce049f419aa0@gmail.com>","References":"<1504875731-3680-1-git-send-email-hayashi.kunihiko@socionext.com>\n\t<1504875731-3680-4-git-send-email-hayashi.kunihiko@socionext.com>\n\t<4173a876-3cff-205a-ce87-ce049f419aa0@gmail.com>","From":"Jassi Brar <jaswinder.singh@linaro.org>","Date":"Sat, 9 Sep 2017 09:03:05 +0530","Message-ID":"<CAJe_ZhciWBhw5npxEjTUGw2duS7DSfhzP5nzAOy_ig4-1XcPWw@mail.gmail.com>","Subject":"Re: [PATCH net-next 3/3] net: phy: realtek: add RTL8201F phy-id and\n\tfunctions","To":"Florian Fainelli <f.fainelli@gmail.com>","Cc":"Kunihiko Hayashi <hayashi.kunihiko@socionext.com>,\n\tnetdev@vger.kernel.org, \"David S. Miller\" <davem@davemloft.net>,\n\tAndrew Lunn <andrew@lunn.ch>, Rob Herring <robh+dt@kernel.org>,\n\tMark Rutland <mark.rutland@arm.com>,\n\t\"linux-arm-kernel@lists.infradead.org\" \n\t<linux-arm-kernel@lists.infradead.org>,\n\tlkml <linux-kernel@vger.kernel.org>,\n\tDevicetree List <devicetree@vger.kernel.org>,\n\tMasahiro Yamada <yamada.masahiro@socionext.com>,\n\tMasami Hiramatsu <masami.hiramatsu@linaro.org>,\n\tJongsung Kim <neidhard.kim@lge.com>","Content-Type":"text/plain; charset=\"UTF-8\"","Sender":"netdev-owner@vger.kernel.org","Precedence":"bulk","List-ID":"<netdev.vger.kernel.org>","X-Mailing-List":"netdev@vger.kernel.org"}},{"id":1765817,"web_url":"http://patchwork.ozlabs.org/comment/1765817/","msgid":"<20170909155517.GB19117@lunn.ch>","list_archive_url":null,"date":"2017-09-09T15:55:17","subject":"Re: [PATCH net-next 3/3] net: phy: realtek: add RTL8201F phy-id and\n\tfunctions","submitter":{"id":13608,"url":"http://patchwork.ozlabs.org/api/people/13608/","name":"Andrew Lunn","email":"andrew@lunn.ch"},"content":"On Sat, Sep 09, 2017 at 09:03:05AM +0530, Jassi Brar wrote:\n> On 9 September 2017 at 00:21, Florian Fainelli <f.fainelli@gmail.com> wrote:\n> > On 09/08/2017 06:02 AM, Kunihiko Hayashi wrote:\n> >> From: Jassi Brar <jaswinder.singh@linaro.org>\n> >>\n> >> Add RTL8201F phy-id and the related functions to the driver.\n> >>\n> >> The original patch is as follows:\n> >> https://patchwork.kernel.org/patch/2538341/\n> >>\n> >> Signed-off-by: Jongsung Kim <neidhard.kim@lge.com>\n> >> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>\n> >> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>\n> >> ---\n> >>  drivers/net/phy/realtek.c | 45 +++++++++++++++++++++++++++++++++++++++++++++\n> >>  1 file changed, 45 insertions(+)\n> >>\n> >> diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c\n> >> index 9cbe645..d9974ce 100644\n> >> --- a/drivers/net/phy/realtek.c\n> >> +++ b/drivers/net/phy/realtek.c\n> >> @@ -29,10 +29,23 @@\n> >>  #define RTL8211F_PAGE_SELECT 0x1f\n> >>  #define RTL8211F_TX_DELAY    0x100\n> >>\n> >> +#define RTL8201F_ISR         0x1e\n> >> +#define RTL8201F_PAGE_SELECT 0x1f\n> >\n> > We have a page select register define for the RTL8211F right above, so\n> > surely we can make that a common definition?\n> >\n> That is just for the sake of consistency.\n> I mean RTL8211 wouldn't look neat among everything else RTL8201.\n> \n> Also the page-select offsets just _happen_ to be same value...\n\nIf you look at all the other supported PHYs, they all consistently use\nthe same page register across models. Marvell is always 22, mscc is\nalways 31, vitesse is always 31.\n\nI would say it is a safe bet that all realtek PHYs will use 0x1f for\npage select. So please add a patch which renames RTL8211F_PAGE_SELECT\nto RTL821x_PAGE_SELECT.\n\nIt is best to do this now. I spent a while cleaning up the mess the\nMarvell driver had got into with its page select code. Lots of\nduplicate code and defines doing the same thing.\n\n\t  Andrew","headers":{"Return-Path":"<netdev-owner@vger.kernel.org>","X-Original-To":"patchwork-incoming@ozlabs.org","Delivered-To":"patchwork-incoming@ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=netdev-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xqJgf4vXPz9t16\n\tfor <patchwork-incoming@ozlabs.org>;\n\tSun, 10 Sep 2017 01:55:42 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1757584AbdIIPza (ORCPT <rfc822;patchwork-incoming@ozlabs.org>);\n\tSat, 9 Sep 2017 11:55:30 -0400","from vps0.lunn.ch ([178.209.37.122]:34401 \"EHLO vps0.lunn.ch\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1753519AbdIIPz2 (ORCPT <rfc822;netdev@vger.kernel.org>);\n\tSat, 9 Sep 2017 11:55:28 -0400","from andrew by vps0.lunn.ch with local (Exim 4.84_2)\n\t(envelope-from <andrew@lunn.ch>)\n\tid 1dqi6H-0005BJ-O9; Sat, 09 Sep 2017 17:55:17 +0200"],"Date":"Sat, 9 Sep 2017 17:55:17 +0200","From":"Andrew Lunn <andrew@lunn.ch>","To":"Jassi Brar <jaswinder.singh@linaro.org>","Cc":"Florian Fainelli <f.fainelli@gmail.com>,\n\tKunihiko Hayashi <hayashi.kunihiko@socionext.com>,\n\tnetdev@vger.kernel.org, \"David S. Miller\" <davem@davemloft.net>,\n\tRob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>,\n\t\"linux-arm-kernel@lists.infradead.org\" \n\t<linux-arm-kernel@lists.infradead.org>,\n\tlkml <linux-kernel@vger.kernel.org>,\n\tDevicetree List <devicetree@vger.kernel.org>,\n\tMasahiro Yamada <yamada.masahiro@socionext.com>,\n\tMasami Hiramatsu <masami.hiramatsu@linaro.org>,\n\tJongsung Kim <neidhard.kim@lge.com>","Subject":"Re: [PATCH net-next 3/3] net: phy: realtek: add RTL8201F phy-id and\n\tfunctions","Message-ID":"<20170909155517.GB19117@lunn.ch>","References":"<1504875731-3680-1-git-send-email-hayashi.kunihiko@socionext.com>\n\t<1504875731-3680-4-git-send-email-hayashi.kunihiko@socionext.com>\n\t<4173a876-3cff-205a-ce87-ce049f419aa0@gmail.com>\n\t<CAJe_ZhciWBhw5npxEjTUGw2duS7DSfhzP5nzAOy_ig4-1XcPWw@mail.gmail.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<CAJe_ZhciWBhw5npxEjTUGw2duS7DSfhzP5nzAOy_ig4-1XcPWw@mail.gmail.com>","User-Agent":"Mutt/1.5.23 (2014-03-12)","Sender":"netdev-owner@vger.kernel.org","Precedence":"bulk","List-ID":"<netdev.vger.kernel.org>","X-Mailing-List":"netdev@vger.kernel.org"}},{"id":1766108,"web_url":"http://patchwork.ozlabs.org/comment/1766108/","msgid":"<20170911164803.6720.4A936039@socionext.com>","list_archive_url":null,"date":"2017-09-11T07:48:03","subject":"Re: [PATCH net-next 3/3] net: phy: realtek: add RTL8201F phy-id and\n\tfunctions","submitter":{"id":71700,"url":"http://patchwork.ozlabs.org/api/people/71700/","name":"Kunihiko Hayashi","email":"hayashi.kunihiko@socionext.com"},"content":"Hi Andrew,\nThank your for reviewing.\n\nOn Sat, 9 Sep 2017 17:55:17 +0200 <andrew@lunn.ch> wrote:\n\n> On Sat, Sep 09, 2017 at 09:03:05AM +0530, Jassi Brar wrote:\n> > On 9 September 2017 at 00:21, Florian Fainelli <f.fainelli@gmail.com> wrote:\n> > > On 09/08/2017 06:02 AM, Kunihiko Hayashi wrote:\n> > >> From: Jassi Brar <jaswinder.singh@linaro.org>\n> > >>\n> > >> Add RTL8201F phy-id and the related functions to the driver.\n> > >>\n> > >> The original patch is as follows:\n> > >> https://patchwork.kernel.org/patch/2538341/\n> > >>\n> > >> Signed-off-by: Jongsung Kim <neidhard.kim@lge.com>\n> > >> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>\n> > >> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>\n> > >> ---\n> > >>  drivers/net/phy/realtek.c | 45 +++++++++++++++++++++++++++++++++++++++++++++\n> > >>  1 file changed, 45 insertions(+)\n> > >>\n> > >> diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c\n> > >> index 9cbe645..d9974ce 100644\n> > >> --- a/drivers/net/phy/realtek.c\n> > >> +++ b/drivers/net/phy/realtek.c\n> > >> @@ -29,10 +29,23 @@\n> > >>  #define RTL8211F_PAGE_SELECT 0x1f\n> > >>  #define RTL8211F_TX_DELAY    0x100\n> > >>\n> > >> +#define RTL8201F_ISR         0x1e\n> > >> +#define RTL8201F_PAGE_SELECT 0x1f\n> > >\n> > > We have a page select register define for the RTL8211F right above, so\n> > > surely we can make that a common definition?\n> > >\n> > That is just for the sake of consistency.\n> > I mean RTL8211 wouldn't look neat among everything else RTL8201.\n> > \n> > Also the page-select offsets just _happen_ to be same value...\n> \n> If you look at all the other supported PHYs, they all consistently use\n> the same page register across models. Marvell is always 22, mscc is\n> always 31, vitesse is always 31.\n> \n> I would say it is a safe bet that all realtek PHYs will use 0x1f for\n> page select. So please add a patch which renames RTL8211F_PAGE_SELECT\n> to RTL821x_PAGE_SELECT.\n> \n> It is best to do this now. I spent a while cleaning up the mess the\n> Marvell driver had got into with its page select code. Lots of\n> duplicate code and defines doing the same thing.\n> \n> \t  Andrew\n\nI see. In case of renaming to RTL821x_PAGE_SELECT, \nI think that I'll make a patch series as realtek PHY series including this\npatch independent from the series of MAC driver.\n\n---\nBest Regards,\nKunihiko Hayashi","headers":{"Return-Path":"<netdev-owner@vger.kernel.org>","X-Original-To":"patchwork-incoming@ozlabs.org","Delivered-To":"patchwork-incoming@ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=netdev-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xrKmP64Rvz9s83\n\tfor <patchwork-incoming@ozlabs.org>;\n\tMon, 11 Sep 2017 17:48:21 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751151AbdIKHsH (ORCPT <rfc822;patchwork-incoming@ozlabs.org>);\n\tMon, 11 Sep 2017 03:48:07 -0400","from mx.socionext.com ([202.248.49.38]:14044 \"EHLO\n\tmx.socionext.com\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1750968AbdIKHsG (ORCPT <rfc822;netdev@vger.kernel.org>);\n\tMon, 11 Sep 2017 03:48:06 -0400","from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52])\n\tby mx.socionext.com with ESMTP; 11 Sep 2017 16:48:05 +0900","from mail.mfilter.local (unknown [10.213.24.61])\n\tby kinkan-ex.css.socionext.com (Postfix) with ESMTP id E46DF180070;\n\tMon, 11 Sep 2017 16:48:04 +0900 (JST)","from 172.31.9.53 (172.31.9.53) by m-FILTER with ESMTP;\n\tMon, 11 Sep 2017 16:48:04 +0900","from yuzu.css.socionext.com (yuzu [172.31.8.45])\n\tby iyokan.css.socionext.com (Postfix) with ESMTP id 5278D4052E;\n\tMon, 11 Sep 2017 16:48:04 +0900 (JST)","from [127.0.0.1] (unknown [10.213.134.37])\n\tby yuzu.css.socionext.com (Postfix) with ESMTP id 08ABC120480;\n\tMon, 11 Sep 2017 16:48:04 +0900 (JST)"],"Date":"Mon, 11 Sep 2017 16:48:03 +0900","From":"Kunihiko Hayashi <hayashi.kunihiko@socionext.com>","To":"Andrew Lunn <andrew@lunn.ch>","Subject":"Re: [PATCH net-next 3/3] net: phy: realtek: add RTL8201F phy-id and\n\tfunctions","Cc":"Jassi Brar <jaswinder.singh@linaro.org>,\n\tFlorian Fainelli <f.fainelli@gmail.com>,\n\t<netdev@vger.kernel.org>, \"David S. Miller\" <davem@davemloft.net>,\n\tRob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>,\n\t\"linux-arm-kernel@lists.infradead.org\" \n\t<linux-arm-kernel@lists.infradead.org>,\n\tlkml <linux-kernel@vger.kernel.org>,\n\tDevicetree List <devicetree@vger.kernel.org>,\n\tMasahiro Yamada <yamada.masahiro@socionext.com>,\n\tMasami Hiramatsu <masami.hiramatsu@linaro.org>,\n\tJongsung Kim <neidhard.kim@lge.com>","In-Reply-To":"<20170909155517.GB19117@lunn.ch>","References":"<CAJe_ZhciWBhw5npxEjTUGw2duS7DSfhzP5nzAOy_ig4-1XcPWw@mail.gmail.com>\n\t<20170909155517.GB19117@lunn.ch>","Message-Id":"<20170911164803.6720.4A936039@socionext.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"US-ASCII\"","Content-Transfer-Encoding":"7bit","X-Mailer":"Becky! ver. 2.70 [ja]","Sender":"netdev-owner@vger.kernel.org","Precedence":"bulk","List-ID":"<netdev.vger.kernel.org>","X-Mailing-List":"netdev@vger.kernel.org"}}]