[{"id":1765326,"web_url":"http://patchwork.ozlabs.org/comment/1765326/","msgid":"<20170908130520.GA11248@lunn.ch>","list_archive_url":null,"date":"2017-09-08T13:05:20","subject":"Re: [PATCH v5 10/10] net: stmmac: dwmac-sun8i: Handle\n\tintegrated/external MDIOs","submitter":{"id":13608,"url":"http://patchwork.ozlabs.org/api/people/13608/","name":"Andrew Lunn","email":"andrew@lunn.ch"},"content":"> +#define DWMAC_sUN8I_MDIO_MUX_INTERNAL_ID\t0\n> +#define DWMAC_sUN8I_MDIO_MUX_EXTERNAL_ID\t1\n> \n> /* H3/A64 specific bits */\n> #define SYSCON_RMII_EN\t\tBIT(13) /* 1: enable RMII (overrides EPIT) */\n> @@ -634,6 +639,76 @@ static int sun8i_dwmac_reset(struct stmmac_priv *priv)\n> \treturn 0;\n> }\n> \n> +/* MDIO multiplexing switch function\n> + * This function is called by the mdio-mux layer when it thinks the mdio bus\n> + * multiplexer needs to switch.\n> + * 'current_child' is the current value of the mux register\n> + * 'desired_child' is the value of the 'reg' property of the target child MDIO\n> + * node.\n> + * The first time this function is called, current_child == -1.\n> + * If current_child == desired_child, then the mux is already set to the\n> + * correct bus.\n> + *\n> + * Note that we do not use reg/mask like mdio-mux-mmioreg because we need to\n> + * know easily which bus is used (reset must be done only for desired bus).\n> + */\n> +static int mdio_mux_syscon_switch_fn(int current_child, int desired_child,\n> +\t\t\t\t void *data)\n> +{\n> +\tstruct stmmac_priv *priv = data;\n> +\tstruct sunxi_priv_data *gmac = priv->plat->bsp_priv;\n> +\tu32 reg, val;\n> +\tint ret = 0;\n> +\tbool need_reset = false;\n> +\n> +\tif (current_child ^ desired_child) {\n> +\t\tregmap_read(gmac->regmap, SYSCON_EMAC_REG, ®);\n> +\t\tswitch (desired_child) {\n> +\t\tcase DWMAC_sUN8I_MDIO_MUX_INTERNAL_ID:\n> +\t\t\tdev_info(priv->device, \"Switch mux to internal PHY\");\n> +\t\t\tval = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SELECT;\n> +\t\t\tif (gmac->use_internal_phy)\n> +\t\t\t\tneed_reset = true;\n> +\t\t\tbreak;\n\nThis i don't get. Why do you need use_internal_phy? Isn't that\nimplicit from DWMAC_sUN8I_MDIO_MUX_INTERNAL_ID? Is it even possible to\nuse an external PHY on the internal MDIO bus?\n\n> +\t\tcase DWMAC_sUN8I_MDIO_MUX_EXTERNAL_ID:\n> +\t\t\tdev_info(priv->device, \"Switch mux to external PHY\");\n> +\t\t\tval = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SHUTDOWN;\n> +\t\t\tif (!gmac->use_internal_phy)\n> +\t\t\t\tneed_reset = true;\n> +\t\t\tbreak;\n\nAnd is it possible to use the internal PHY on the external bus?\n\n Andrew","headers":{"Return-Path":"","X-Original-To":"patchwork-incoming@ozlabs.org","Delivered-To":"patchwork-incoming@ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=netdev-owner@vger.kernel.org;\n\treceiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xpcy13rqsz9ryk\n\tfor ;\n\tFri, 8 Sep 2017 23:05:45 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1755745AbdIHNFe (ORCPT );\n\tFri, 8 Sep 2017 09:05:34 -0400","from vps0.lunn.ch ([178.209.37.122]:32888 \"EHLO vps0.lunn.ch\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1755119AbdIHNFc (ORCPT );\n\tFri, 8 Sep 2017 09:05:32 -0400","from andrew by vps0.lunn.ch with local (Exim 4.84_2)\n\t(envelope-from )\n\tid 1dqIyG-0006QP-KT; Fri, 08 Sep 2017 15:05:20 +0200"],"Date":"Fri, 8 Sep 2017 15:05:20 +0200","From":"Andrew Lunn ","To":"Corentin Labbe ","Cc":"robh+dt@kernel.org, mark.rutland@arm.com,\n\tmaxime.ripard@free-electrons.com, wens@csie.org,\n\tlinux@armlinux.org.uk, catalin.marinas@arm.com,\n\twill.deacon@arm.com, peppe.cavallaro@st.com,\n\talexandre.torgue@st.com, f.fainelli@gmail.com,\n\tnetdev@vger.kernel.org, devicetree@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org","Subject":"Re: [PATCH v5 10/10] net: stmmac: dwmac-sun8i: Handle\n\tintegrated/external MDIOs","Message-ID":"<20170908130520.GA11248@lunn.ch>","References":"<20170908071156.5115-1-clabbe.montjoie@gmail.com>\n\t<20170908071156.5115-11-clabbe.montjoie@gmail.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170908071156.5115-11-clabbe.montjoie@gmail.com>","User-Agent":"Mutt/1.5.23 (2014-03-12)","Sender":"netdev-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"netdev@vger.kernel.org"}},{"id":1765350,"web_url":"http://patchwork.ozlabs.org/comment/1765350/","msgid":"<20170908132632.GA3037@Red>","list_archive_url":null,"date":"2017-09-08T13:26:32","subject":"Re: [PATCH v5 10/10] net: stmmac: dwmac-sun8i: Handle\n\tintegrated/external MDIOs","submitter":{"id":64152,"url":"http://patchwork.ozlabs.org/api/people/64152/","name":"Corentin Labbe","email":"clabbe.montjoie@gmail.com"},"content":"On Fri, Sep 08, 2017 at 03:05:20PM +0200, Andrew Lunn wrote:\n> > +#define DWMAC_sUN8I_MDIO_MUX_INTERNAL_ID\t0\n> > +#define DWMAC_sUN8I_MDIO_MUX_EXTERNAL_ID\t1\n> > \n> > /* H3/A64 specific bits */\n> > #define SYSCON_RMII_EN\t\tBIT(13) /* 1: enable RMII (overrides EPIT) */\n> > @@ -634,6 +639,76 @@ static int sun8i_dwmac_reset(struct stmmac_priv *priv)\n> > \treturn 0;\n> > }\n> > \n> > +/* MDIO multiplexing switch function\n> > + * This function is called by the mdio-mux layer when it thinks the mdio bus\n> > + * multiplexer needs to switch.\n> > + * 'current_child' is the current value of the mux register\n> > + * 'desired_child' is the value of the 'reg' property of the target child MDIO\n> > + * node.\n> > + * The first time this function is called, current_child == -1.\n> > + * If current_child == desired_child, then the mux is already set to the\n> > + * correct bus.\n> > + *\n> > + * Note that we do not use reg/mask like mdio-mux-mmioreg because we need to\n> > + * know easily which bus is used (reset must be done only for desired bus).\n> > + */\n> > +static int mdio_mux_syscon_switch_fn(int current_child, int desired_child,\n> > +\t\t\t\t void *data)\n> > +{\n> > +\tstruct stmmac_priv *priv = data;\n> > +\tstruct sunxi_priv_data *gmac = priv->plat->bsp_priv;\n> > +\tu32 reg, val;\n> > +\tint ret = 0;\n> > +\tbool need_reset = false;\n> > +\n> > +\tif (current_child ^ desired_child) {\n> > +\t\tregmap_read(gmac->regmap, SYSCON_EMAC_REG, ®);\n> > +\t\tswitch (desired_child) {\n> > +\t\tcase DWMAC_sUN8I_MDIO_MUX_INTERNAL_ID:\n> > +\t\t\tdev_info(priv->device, \"Switch mux to internal PHY\");\n> > +\t\t\tval = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SELECT;\n> > +\t\t\tif (gmac->use_internal_phy)\n> > +\t\t\t\tneed_reset = true;\n> > +\t\t\tbreak;\n> \n> This i don't get. Why do you need use_internal_phy? Isn't that\n> implicit from DWMAC_sUN8I_MDIO_MUX_INTERNAL_ID? Is it even possible to\n> use an external PHY on the internal MDIO bus?\n> \n\nOn my H3 box with external PHY, the MDIO mux library first select (for scan ?) the internal MDIO.\nWithout use_internal_phy usage, this board will launch a reset to use the internal MDIO... and this reset timeout/fail.\nAfter the MDIO mux select the external MDIO.\n\n> > +\t\tcase DWMAC_sUN8I_MDIO_MUX_EXTERNAL_ID:\n> > +\t\t\tdev_info(priv->device, \"Switch mux to external PHY\");\n> > +\t\t\tval = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SHUTDOWN;\n> > +\t\t\tif (!gmac->use_internal_phy)\n> > +\t\t\t\tneed_reset = true;\n> > +\t\t\tbreak;\n> \n> And is it possible to use the internal PHY on the external bus?\n> \n\nI need to check that.\n\nRegards","headers":{"Return-Path":"","X-Original-To":"patchwork-incoming@ozlabs.org","Delivered-To":"patchwork-incoming@ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=netdev-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"sQ8+GfEN\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xpdQZ6jcKz9s4s\n\tfor ;\n\tFri, 8 Sep 2017 23:27:02 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S933308AbdIHN0r (ORCPT );\n\tFri, 8 Sep 2017 09:26:47 -0400","from mail-wr0-f174.google.com ([209.85.128.174]:34284 \"EHLO\n\tmail-wr0-f174.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1756468AbdIHN0m (ORCPT\n\t); Fri, 8 Sep 2017 09:26:42 -0400","by mail-wr0-f174.google.com with SMTP id v109so4722114wrc.1;\n\tFri, 08 Sep 2017 06:26:41 -0700 (PDT)","from Red ([2a01:cb1d:16e:1300:2e56:dcff:fed2:c6d6])\n\tby smtp.googlemail.com with ESMTPSA id\n\t25sm1664932wrv.8.2017.09.08.06.26.39\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tFri, 08 Sep 2017 06:26:39 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=gmail.com; s=20161025;\n\th=date:from:to:cc:subject:message-id:references:mime-version\n\t:content-disposition:in-reply-to:user-agent;\n\tbh=ABC0sceKuoEyuo2GW9tOg1Ab1KNol2XYuiqDWZ/cVrw=;\n\tb=sQ8+GfENa2Ir5gKCOjXqNuMp44q624Qp3dFAMoeRRcZNuFNOYIiCVEAShkH0Jo28XD\n\tlBeHfd1Zm8C6sGOtRO6fYSM5GQcAsyu8s7pyloPljBobeX0ZOsFbkXfEIPQbxIg4NPK2\n\tmFV7XCHUx0CMAtOndXXFDn6pxwk0+6k+0ULOwd8R+tCCo8E3iE4EMJPN9ic0gJp/N/0s\n\tKKYKQJy31HE+lr5jOcB+2zc/ZQ3LY7tyPtTf9iVQOCKN4OS+B50eeQJ22a0Nsw6FLddn\n\tdgxhJ5OXAHeU1TBKSRHTUCUdNzNt/h1cPHjcpe2VAmqSvQ7FYZjqjYX2IXRszdlYa+GG\n\tybug==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:date:from:to:cc:subject:message-id:references\n\t:mime-version:content-disposition:in-reply-to:user-agent;\n\tbh=ABC0sceKuoEyuo2GW9tOg1Ab1KNol2XYuiqDWZ/cVrw=;\n\tb=MhNvwJSp3moa4ZPFxj6ExG0b0kvagLOJ2cxfRc8/I/3xd+syNLJ05DVHb33lxY/gyZ\n\toCtK7Aocn/QUDBk+2hbgh9kKQPXT1dp8mDAXp3jILpvY2vzC7xSiCIo+hKbZnYvxqErN\n\tUNhVQaM5NYcynZKlSdyJTWP7aJsoGo5dlPbjQNGS401sp4b6cxlGpgYhK7kfYzmK0qmu\n\tWzhAWwgjO0WeunHGgwB1aBdvwYwlqBSv2qtN/iqTLF0NsS7+2B/llMbuB2bZXitcbTL8\n\t3dYWkuJIRtofa5qKy4DmFszq5+Cg7zeOb+UZE8rwXlCbKM2h/xzPYXcE1WSJepMXMXcI\n\tNq/g==","X-Gm-Message-State":"AHPjjUgVpmZXzzufwrtt7HitPu28Mb0uAz/wIcU57IWWsdQ3IbeIdg+D\n\tOql5cGWNO/gttQ==","X-Google-Smtp-Source":"ADKCNb7Url3OLBd39P8Yp6SrbEs1W9FY15H3CXQka4m1iHXyTVHoxnwQyl0kYFNxFNCAFi29V0+5wA==","X-Received":"by 10.223.154.120 with SMTP id\n\tz111mr2173238wrb.260.1504877200476; \n\tFri, 08 Sep 2017 06:26:40 -0700 (PDT)","Date":"Fri, 8 Sep 2017 15:26:32 +0200","From":"Corentin Labbe ","To":"Andrew Lunn ","Cc":"robh+dt@kernel.org, mark.rutland@arm.com,\n\tmaxime.ripard@free-electrons.com, wens@csie.org,\n\tlinux@armlinux.org.uk, catalin.marinas@arm.com,\n\twill.deacon@arm.com, peppe.cavallaro@st.com,\n\talexandre.torgue@st.com, f.fainelli@gmail.com,\n\tnetdev@vger.kernel.org, devicetree@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org","Subject":"Re: [PATCH v5 10/10] net: stmmac: dwmac-sun8i: Handle\n\tintegrated/external MDIOs","Message-ID":"<20170908132632.GA3037@Red>","References":"<20170908071156.5115-1-clabbe.montjoie@gmail.com>\n\t<20170908071156.5115-11-clabbe.montjoie@gmail.com>\n\t<20170908130520.GA11248@lunn.ch>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170908130520.GA11248@lunn.ch>","User-Agent":"Mutt/1.7.2 (2016-11-26)","Sender":"netdev-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"netdev@vger.kernel.org"}},{"id":1765388,"web_url":"http://patchwork.ozlabs.org/comment/1765388/","msgid":"<20170908140020.GC25219@lunn.ch>","list_archive_url":null,"date":"2017-09-08T14:00:20","subject":"Re: [PATCH v5 10/10] net: stmmac: dwmac-sun8i: Handle\n\tintegrated/external MDIOs","submitter":{"id":13608,"url":"http://patchwork.ozlabs.org/api/people/13608/","name":"Andrew Lunn","email":"andrew@lunn.ch"},"content":"> > > +static int mdio_mux_syscon_switch_fn(int current_child, int desired_child,\n> > > +\t\t\t\t void *data)\n> > > +{\n> > > +\tstruct stmmac_priv *priv = data;\n> > > +\tstruct sunxi_priv_data *gmac = priv->plat->bsp_priv;\n> > > +\tu32 reg, val;\n> > > +\tint ret = 0;\n> > > +\tbool need_reset = false;\n> > > +\n> > > +\tif (current_child ^ desired_child) {\n> > > +\t\tregmap_read(gmac->regmap, SYSCON_EMAC_REG, ®);\n> > > +\t\tswitch (desired_child) {\n> > > +\t\tcase DWMAC_sUN8I_MDIO_MUX_INTERNAL_ID:\n> > > +\t\t\tdev_info(priv->device, \"Switch mux to internal PHY\");\n> > > +\t\t\tval = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SELECT;\n> > > +\t\t\tif (gmac->use_internal_phy)\n> > > +\t\t\t\tneed_reset = true;\n> > > +\t\t\tbreak;\n> > \n> > This i don't get. Why do you need use_internal_phy? Isn't that\n> > implicit from DWMAC_sUN8I_MDIO_MUX_INTERNAL_ID? Is it even possible to\n> > use an external PHY on the internal MDIO bus?\n> > \n> \n> On my H3 box with external PHY, the MDIO mux library first select (for scan ?) the internal MDIO.\n> Without use_internal_phy usage, this board will launch a reset to use the internal MDIO... and this reset timeout/fail.\n\nDo you know why the reset times out/fails?\n\n Andrew","headers":{"Return-Path":"","X-Original-To":"patchwork-incoming@ozlabs.org","Delivered-To":"patchwork-incoming@ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=netdev-owner@vger.kernel.org;\n\treceiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xpf9Q2WS8z9s7G\n\tfor ;\n\tSat, 9 Sep 2017 00:00:42 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752764AbdIHOAa (ORCPT );\n\tFri, 8 Sep 2017 10:00:30 -0400","from vps0.lunn.ch ([178.209.37.122]:33011 \"EHLO vps0.lunn.ch\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1750985AbdIHOA2 (ORCPT );\n\tFri, 8 Sep 2017 10:00:28 -0400","from andrew by vps0.lunn.ch with local (Exim 4.84_2)\n\t(envelope-from )\n\tid 1dqJpU-00078J-JB; Fri, 08 Sep 2017 16:00:20 +0200"],"Date":"Fri, 8 Sep 2017 16:00:20 +0200","From":"Andrew Lunn ","To":"Corentin Labbe ","Cc":"robh+dt@kernel.org, mark.rutland@arm.com,\n\tmaxime.ripard@free-electrons.com, wens@csie.org,\n\tlinux@armlinux.org.uk, catalin.marinas@arm.com,\n\twill.deacon@arm.com, peppe.cavallaro@st.com,\n\talexandre.torgue@st.com, f.fainelli@gmail.com,\n\tnetdev@vger.kernel.org, devicetree@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org","Subject":"Re: [PATCH v5 10/10] net: stmmac: dwmac-sun8i: Handle\n\tintegrated/external MDIOs","Message-ID":"<20170908140020.GC25219@lunn.ch>","References":"<20170908071156.5115-1-clabbe.montjoie@gmail.com>\n\t<20170908071156.5115-11-clabbe.montjoie@gmail.com>\n\t<20170908130520.GA11248@lunn.ch> <20170908132632.GA3037@Red>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170908132632.GA3037@Red>","User-Agent":"Mutt/1.5.23 (2014-03-12)","Sender":"netdev-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"netdev@vger.kernel.org"}},{"id":1765399,"web_url":"http://patchwork.ozlabs.org/comment/1765399/","msgid":"<20170908140832.GB3037@Red>","list_archive_url":null,"date":"2017-09-08T14:08:32","subject":"Re: [PATCH v5 10/10] net: stmmac: dwmac-sun8i: Handle\n\tintegrated/external MDIOs","submitter":{"id":64152,"url":"http://patchwork.ozlabs.org/api/people/64152/","name":"Corentin Labbe","email":"clabbe.montjoie@gmail.com"},"content":"On Fri, Sep 08, 2017 at 04:00:20PM +0200, Andrew Lunn wrote:\n> > > > +static int mdio_mux_syscon_switch_fn(int current_child, int desired_child,\n> > > > +\t\t\t\t void *data)\n> > > > +{\n> > > > +\tstruct stmmac_priv *priv = data;\n> > > > +\tstruct sunxi_priv_data *gmac = priv->plat->bsp_priv;\n> > > > +\tu32 reg, val;\n> > > > +\tint ret = 0;\n> > > > +\tbool need_reset = false;\n> > > > +\n> > > > +\tif (current_child ^ desired_child) {\n> > > > +\t\tregmap_read(gmac->regmap, SYSCON_EMAC_REG, ®);\n> > > > +\t\tswitch (desired_child) {\n> > > > +\t\tcase DWMAC_sUN8I_MDIO_MUX_INTERNAL_ID:\n> > > > +\t\t\tdev_info(priv->device, \"Switch mux to internal PHY\");\n> > > > +\t\t\tval = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SELECT;\n> > > > +\t\t\tif (gmac->use_internal_phy)\n> > > > +\t\t\t\tneed_reset = true;\n> > > > +\t\t\tbreak;\n> > > \n> > > This i don't get. Why do you need use_internal_phy? Isn't that\n> > > implicit from DWMAC_sUN8I_MDIO_MUX_INTERNAL_ID? Is it even possible to\n> > > use an external PHY on the internal MDIO bus?\n> > > \n> > \n> > On my H3 box with external PHY, the MDIO mux library first select (for scan ?) the internal MDIO.\n> > Without use_internal_phy usage, this board will launch a reset to use the internal MDIO... and this reset timeout/fail.\n> \n> Do you know why the reset times out/fails?\n> \n\nBecause there are nothing connected to it.\nI got also reset timeout on integrated MDIO when the integrated PHY is not powered.","headers":{"Return-Path":"","X-Original-To":"patchwork-incoming@ozlabs.org","Delivered-To":"patchwork-incoming@ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=netdev-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"nvjMQr9D\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xpfLj6CY7z9s7G\n\tfor ;\n\tSat, 9 Sep 2017 00:08:45 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1753132AbdIHOIn (ORCPT );\n\tFri, 8 Sep 2017 10:08:43 -0400","from mail-wm0-f66.google.com ([74.125.82.66]:36317 \"EHLO\n\tmail-wm0-f66.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751139AbdIHOIl (ORCPT\n\t); Fri, 8 Sep 2017 10:08:41 -0400","by mail-wm0-f66.google.com with SMTP id p17so1817662wmd.3;\n\tFri, 08 Sep 2017 07:08:41 -0700 (PDT)","from Red ([2a01:cb1d:16e:1300:2e56:dcff:fed2:c6d6])\n\tby smtp.googlemail.com with ESMTPSA id\n\tm19sm1477166wmd.16.2017.09.08.07.08.39\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tFri, 08 Sep 2017 07:08:39 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=gmail.com; s=20161025;\n\th=date:from:to:cc:subject:message-id:references:mime-version\n\t:content-disposition:in-reply-to:user-agent;\n\tbh=p3d0mpH+Jn1o0PcmosPIASkWVhlqhXQi3UxfJu5AajI=;\n\tb=nvjMQr9DKO3FuSLs2fTQTeEgZzZxM7+oFMSfzQKzZlXjb1wgupl/OiJ1gYVJBkIPv2\n\t5YcsbHafvLc/YnrVlnyaWRL7wFGttpod33YNQJDomgGw5RAOgL2m/uwZWpDiJwE/OZbh\n\t5o1NAAnVsmoJ/5yDHd1c1QV9scUwfYdQuw0cww99zj2ea1qG8MW1j5pT7cp7SO+T7Q/L\n\tzEOtJj0l5qBhTZRBnBXzVG7bwrFr/CMLgx3QYfs1ItI9eeVNh5KQwsEm2dw1Kx6ENemn\n\tun4rN8r1CMIpH2BbevaH+4XWc7PQ0HSlXF+CQOsQGf8hR359KqXHRECRgr1u0r+7OEJW\n\t2chA==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:date:from:to:cc:subject:message-id:references\n\t:mime-version:content-disposition:in-reply-to:user-agent;\n\tbh=p3d0mpH+Jn1o0PcmosPIASkWVhlqhXQi3UxfJu5AajI=;\n\tb=g8fI/evFfIsmMIDCn42w2e0CmdQqKIJN883hHrR4TFlPDR2Jp3ATgfNj8OuJjoHBEs\n\tCWv0X2VdqeNLmm1BL2hv1HfLRaxlEmpRQrv/m/OgT08irdL+E0wE5dccL+YMNvl16CLt\n\t3QaVW3I3PkuijGAt/I4EXZDAXMFKcTFwXjdVaab+smfvhzitxt7dKjD063l3AZ+j8RaD\n\tdrGeYHABoB+KdivY19XCBYOwVwm+GILqzInYDmLp0gBFUgJWT7fZRaI04x6lLx4xm7by\n\ti1r4NZ08z4fWJxpThc9utEWnWYeJdko1Q+foEzXgXMr8NRw0J9SdqDHRAGUSfWBjHzFC\n\tttpA==","X-Gm-Message-State":"AHPjjUjVbcWZWVB4gRYjsJ8YCBniBqqPEdCdgSuDotU70hzrquZNAa6g\n\tWys/kmckUPr6XBgi+T7Sn0Y=","X-Google-Smtp-Source":"ADKCNb55ddthQdRXcOrvHLlegohEkzxYg9IdwcOuKkS16HRQDW4LzLifqrhbBWvhCknOrBvirOeg5w==","X-Received":"by 10.28.26.15 with SMTP id a15mr968911wma.16.1504879720469;\n\tFri, 08 Sep 2017 07:08:40 -0700 (PDT)","Date":"Fri, 8 Sep 2017 16:08:32 +0200","From":"Corentin Labbe ","To":"Andrew Lunn ","Cc":"robh+dt@kernel.org, mark.rutland@arm.com,\n\tmaxime.ripard@free-electrons.com, wens@csie.org,\n\tlinux@armlinux.org.uk, catalin.marinas@arm.com,\n\twill.deacon@arm.com, peppe.cavallaro@st.com,\n\talexandre.torgue@st.com, f.fainelli@gmail.com,\n\tnetdev@vger.kernel.org, devicetree@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org","Subject":"Re: [PATCH v5 10/10] net: stmmac: dwmac-sun8i: Handle\n\tintegrated/external MDIOs","Message-ID":"<20170908140832.GB3037@Red>","References":"<20170908071156.5115-1-clabbe.montjoie@gmail.com>\n\t<20170908071156.5115-11-clabbe.montjoie@gmail.com>\n\t<20170908130520.GA11248@lunn.ch> <20170908132632.GA3037@Red>\n\t<20170908140020.GC25219@lunn.ch>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170908140020.GC25219@lunn.ch>","User-Agent":"Mutt/1.7.2 (2016-11-26)","Sender":"netdev-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"netdev@vger.kernel.org"}},{"id":1765409,"web_url":"http://patchwork.ozlabs.org/comment/1765409/","msgid":"<20170908141736.GF25219@lunn.ch>","list_archive_url":null,"date":"2017-09-08T14:17:36","subject":"Re: [PATCH v5 10/10] net: stmmac: dwmac-sun8i: Handle\n\tintegrated/external MDIOs","submitter":{"id":13608,"url":"http://patchwork.ozlabs.org/api/people/13608/","name":"Andrew Lunn","email":"andrew@lunn.ch"},"content":"> > Do you know why the reset times out/fails?\n> > \n> \n> Because there are nothing connected to it.\n\nThat should not be an issue. A read should just return 0xffff. And it\nshould return 0xffff fast. The timing of the MDIO protocol is fixed. A\nread or a write takes a fixed number of cycles, independent of if\nthere is a device there or not. The bus data line has a pullup, so if\nyou try to access a missing device, you automatically read 0xffff.\n\n Andrew","headers":{"Return-Path":"","X-Original-To":"patchwork-incoming@ozlabs.org","Delivered-To":"patchwork-incoming@ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=netdev-owner@vger.kernel.org;\n\treceiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xpfYM3zDjz9s7G\n\tfor ;\n\tSat, 9 Sep 2017 00:17:59 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1755392AbdIHORs (ORCPT );\n\tFri, 8 Sep 2017 10:17:48 -0400","from vps0.lunn.ch ([178.209.37.122]:33076 \"EHLO vps0.lunn.ch\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1753243AbdIHORq (ORCPT );\n\tFri, 8 Sep 2017 10:17:46 -0400","from andrew by vps0.lunn.ch with local (Exim 4.84_2)\n\t(envelope-from )\n\tid 1dqK6C-0007Re-MN; Fri, 08 Sep 2017 16:17:36 +0200"],"Date":"Fri, 8 Sep 2017 16:17:36 +0200","From":"Andrew Lunn ","To":"Corentin Labbe ","Cc":"robh+dt@kernel.org, mark.rutland@arm.com,\n\tmaxime.ripard@free-electrons.com, wens@csie.org,\n\tlinux@armlinux.org.uk, catalin.marinas@arm.com,\n\twill.deacon@arm.com, peppe.cavallaro@st.com,\n\talexandre.torgue@st.com, f.fainelli@gmail.com,\n\tnetdev@vger.kernel.org, devicetree@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org","Subject":"Re: [PATCH v5 10/10] net: stmmac: dwmac-sun8i: Handle\n\tintegrated/external MDIOs","Message-ID":"<20170908141736.GF25219@lunn.ch>","References":"<20170908071156.5115-1-clabbe.montjoie@gmail.com>\n\t<20170908071156.5115-11-clabbe.montjoie@gmail.com>\n\t<20170908130520.GA11248@lunn.ch> <20170908132632.GA3037@Red>\n\t<20170908140020.GC25219@lunn.ch> <20170908140832.GB3037@Red>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170908140832.GB3037@Red>","User-Agent":"Mutt/1.5.23 (2014-03-12)","Sender":"netdev-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"netdev@vger.kernel.org"}},{"id":1765416,"web_url":"http://patchwork.ozlabs.org/comment/1765416/","msgid":"<20170908142825.GC3037@Red>","list_archive_url":null,"date":"2017-09-08T14:28:25","subject":"Re: [PATCH v5 10/10] net: stmmac: dwmac-sun8i: Handle\n\tintegrated/external MDIOs","submitter":{"id":64152,"url":"http://patchwork.ozlabs.org/api/people/64152/","name":"Corentin Labbe","email":"clabbe.montjoie@gmail.com"},"content":"On Fri, Sep 08, 2017 at 04:17:36PM +0200, Andrew Lunn wrote:\n> > > Do you know why the reset times out/fails?\n> > > \n> > \n> > Because there are nothing connected to it.\n> \n> That should not be an issue. A read should just return 0xffff. And it\n> should return 0xffff fast. The timing of the MDIO protocol is fixed. A\n> read or a write takes a fixed number of cycles, independent of if\n> there is a device there or not. The bus data line has a pullup, so if\n> you try to access a missing device, you automatically read 0xffff.\n> \n\nPerhaps, but the reality is that with nothing connected to it, the reset of the MAC timeout.\nCertainly, the MAC does not support finding no PHY.\n\nSo, to prevent an error message, and a \"freeze\" of the net process, the need_reset trick is necessary.\n\nRegards\nCorentin Labbe","headers":{"Return-Path":"","X-Original-To":"patchwork-incoming@ozlabs.org","Delivered-To":"patchwork-incoming@ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=netdev-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"g45+HDhj\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xpfnq414Vz9s7G\n\tfor ;\n\tSat, 9 Sep 2017 00:28:47 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1756218AbdIHO2f (ORCPT );\n\tFri, 8 Sep 2017 10:28:35 -0400","from mail-wr0-f181.google.com ([209.85.128.181]:36562 \"EHLO\n\tmail-wr0-f181.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1753243AbdIHO2e (ORCPT\n\t); Fri, 8 Sep 2017 10:28:34 -0400","by mail-wr0-f181.google.com with SMTP id o42so5002689wrb.3;\n\tFri, 08 Sep 2017 07:28:33 -0700 (PDT)","from Red ([2a01:cb1d:16e:1300:2e56:dcff:fed2:c6d6])\n\tby smtp.googlemail.com with ESMTPSA id\n\tw82sm2368196wme.5.2017.09.08.07.28.31\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tFri, 08 Sep 2017 07:28:32 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=gmail.com; s=20161025;\n\th=date:from:to:cc:subject:message-id:references:mime-version\n\t:content-disposition:in-reply-to:user-agent;\n\tbh=CemjWqI9tG6GU2myYclJV4DrL4gc6E6tKAvzN03UPXw=;\n\tb=g45+HDhjm1KMyELELW4nHQiWSj85crx7vFAdiE8Eq8ycDrLWyAm665gvGUUUHNat5s\n\tQItHqEaTpSJO9nHeE3vaAw6UoOdAJnig+1qJ2ciImEAmLmu0F0sAyzausYfINJ8hAgJ7\n\t438eYpKCf1SljSfIgGfFFfcGhjOrqVunA9yqJlDAn1rjISacfB97HQHQgPHCBwxg32wk\n\t4eluApXoWI6Lwrvi7IAKBlqA6Rehtunv6x0MNhJEu6a4R7PCKEmYKCj89gcPqxe6Qp5E\n\tRanQR3mpK/rF+eoNhJuPEHJuUxq3jk5s2ea0E+mJhHfnaTSEufJQzkwG229UMCAagzCG\n\tjhVA==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:date:from:to:cc:subject:message-id:references\n\t:mime-version:content-disposition:in-reply-to:user-agent;\n\tbh=CemjWqI9tG6GU2myYclJV4DrL4gc6E6tKAvzN03UPXw=;\n\tb=IFzm7H4k5fGMJYfU9woVVahLGzG82nbowXuzSfNwaY9kuTbynhWiAfAABp9qIYrdY8\n\t0QGpdILptkbwtE9uygRnUy/jc65+JdfOOlaPFqrDj81FkTrWvvwdowBrn78L8BWi1ZQq\n\t+4cIDZj8DrDYULN6hRakW6p0iRj0763kM+P2JJ/tzc99AgU78xGdJi2YIvB05iKnIgZ2\n\tLBPjjVVZ8AVKpGF/UmN7qaPiexol05NUqowRcQLmTVKPG2w0UQD9dxrNnPARIRHLxLkJ\n\tlQ9ehkIAaiIomeyBlfvL0ygrjw5Zhj+APqO+4wu3EZvB9JblqP4Ixa66jEDYJ3AGRrlk\n\tH4lQ==","X-Gm-Message-State":"AHPjjUgtHlSadG6/EoaAswTWjItkTbZ3jWKgzo7Rr8WZOIYNrZ3qDc8v\n\tXMS1APk0ULGmYw==","X-Google-Smtp-Source":"ADKCNb42s9wZByp0FN2+bMjidsTQsry1myhh9ZMyVqbTNdCltWkhAnRCBwWP6POE6LJLOWu5NyHtLg==","X-Received":"by 10.223.147.195 with SMTP id 61mr2171296wrp.119.1504880912652; \n\tFri, 08 Sep 2017 07:28:32 -0700 (PDT)","Date":"Fri, 8 Sep 2017 16:28:25 +0200","From":"Corentin Labbe ","To":"Andrew Lunn ","Cc":"robh+dt@kernel.org, mark.rutland@arm.com,\n\tmaxime.ripard@free-electrons.com, wens@csie.org,\n\tlinux@armlinux.org.uk, catalin.marinas@arm.com,\n\twill.deacon@arm.com, peppe.cavallaro@st.com,\n\talexandre.torgue@st.com, f.fainelli@gmail.com,\n\tnetdev@vger.kernel.org, devicetree@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org","Subject":"Re: [PATCH v5 10/10] net: stmmac: dwmac-sun8i: Handle\n\tintegrated/external MDIOs","Message-ID":"<20170908142825.GC3037@Red>","References":"<20170908071156.5115-1-clabbe.montjoie@gmail.com>\n\t<20170908071156.5115-11-clabbe.montjoie@gmail.com>\n\t<20170908130520.GA11248@lunn.ch> <20170908132632.GA3037@Red>\n\t<20170908140020.GC25219@lunn.ch> <20170908140832.GB3037@Red>\n\t<20170908141736.GF25219@lunn.ch>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170908141736.GF25219@lunn.ch>","User-Agent":"Mutt/1.7.2 (2016-11-26)","Sender":"netdev-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"netdev@vger.kernel.org"}},{"id":1766378,"web_url":"http://patchwork.ozlabs.org/comment/1766378/","msgid":"<20170911161124.GD27599@lunn.ch>","list_archive_url":null,"date":"2017-09-11T16:11:24","subject":"Re: [PATCH v5 10/10] net: stmmac: dwmac-sun8i: Handle\n\tintegrated/external MDIOs","submitter":{"id":13608,"url":"http://patchwork.ozlabs.org/api/people/13608/","name":"Andrew Lunn","email":"andrew@lunn.ch"},"content":"On Fri, Sep 08, 2017 at 04:28:25PM +0200, Corentin Labbe wrote:\n> On Fri, Sep 08, 2017 at 04:17:36PM +0200, Andrew Lunn wrote:\n> > > > Do you know why the reset times out/fails?\n> > > > \n> > > \n> > > Because there are nothing connected to it.\n> > \n> > That should not be an issue. A read should just return 0xffff. And it\n> > should return 0xffff fast. The timing of the MDIO protocol is fixed. A\n> > read or a write takes a fixed number of cycles, independent of if\n> > there is a device there or not. The bus data line has a pullup, so if\n> > you try to access a missing device, you automatically read 0xffff.\n> > \n> \n> Perhaps, but the reality is that with nothing connected to it, the reset of the MAC timeout.\n> Certainly, the MAC does not support finding no PHY.\n\nAre you sure this is not because of the clock and reset?\n\n+ #address-cells = <1>;\n+ #size-cells = <0>;\n+ int_mii_phy: ethernet-phy@1 {\n+ compatible = \"ethernet-phy-ieee802.3-c22\";\n+ reg = <1>;\n+ clocks = <&ccu CLK_BUS_EPHY>;\n+ resets = <&ccu RST_BUS_EPHY>;\n\nThe way you describe it here, the clock and reset are for the PHY. But\nmaybe it is actually for the bus? I can understand a bus timing out if\nit has no clock, or it is held in reset. Try enabling the clock and\nreset when the internal bus is selected, not when the PHY on the bus\nis selected.\n\n\tAndrew","headers":{"Return-Path":"","X-Original-To":"patchwork-incoming@ozlabs.org","Delivered-To":"patchwork-incoming@ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=netdev-owner@vger.kernel.org;\n\treceiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xrXxN5ngxz9s7f\n\tfor ;\n\tTue, 12 Sep 2017 02:11:52 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751790AbdIKQLi (ORCPT );\n\tMon, 11 Sep 2017 12:11:38 -0400","from vps0.lunn.ch ([178.209.37.122]:37299 \"EHLO vps0.lunn.ch\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1750957AbdIKQLg (ORCPT );\n\tMon, 11 Sep 2017 12:11:36 -0400","from andrew by vps0.lunn.ch with local (Exim 4.84_2)\n\t(envelope-from )\n\tid 1drRIy-0008JZ-II; Mon, 11 Sep 2017 18:11:24 +0200"],"Date":"Mon, 11 Sep 2017 18:11:24 +0200","From":"Andrew Lunn ","To":"Corentin Labbe ","Cc":"robh+dt@kernel.org, mark.rutland@arm.com,\n\tmaxime.ripard@free-electrons.com, wens@csie.org,\n\tlinux@armlinux.org.uk, catalin.marinas@arm.com,\n\twill.deacon@arm.com, peppe.cavallaro@st.com,\n\talexandre.torgue@st.com, f.fainelli@gmail.com,\n\tnetdev@vger.kernel.org, devicetree@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org","Subject":"Re: [PATCH v5 10/10] net: stmmac: dwmac-sun8i: Handle\n\tintegrated/external MDIOs","Message-ID":"<20170911161124.GD27599@lunn.ch>","References":"<20170908071156.5115-1-clabbe.montjoie@gmail.com>\n\t<20170908071156.5115-11-clabbe.montjoie@gmail.com>\n\t<20170908130520.GA11248@lunn.ch> <20170908132632.GA3037@Red>\n\t<20170908140020.GC25219@lunn.ch> <20170908140832.GB3037@Red>\n\t<20170908141736.GF25219@lunn.ch> <20170908142825.GC3037@Red>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170908142825.GC3037@Red>","User-Agent":"Mutt/1.5.23 (2014-03-12)","Sender":"netdev-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"netdev@vger.kernel.org"}},{"id":1766463,"web_url":"http://patchwork.ozlabs.org/comment/1766463/","msgid":"<20170911190850.GA2291@Red>","list_archive_url":null,"date":"2017-09-11T19:08:50","subject":"Re: [PATCH v5 10/10] net: stmmac: dwmac-sun8i: Handle\n\tintegrated/external MDIOs","submitter":{"id":64152,"url":"http://patchwork.ozlabs.org/api/people/64152/","name":"Corentin Labbe","email":"clabbe.montjoie@gmail.com"},"content":"On Mon, Sep 11, 2017 at 06:11:24PM +0200, Andrew Lunn wrote:\n> On Fri, Sep 08, 2017 at 04:28:25PM +0200, Corentin Labbe wrote:\n> > On Fri, Sep 08, 2017 at 04:17:36PM +0200, Andrew Lunn wrote:\n> > > > > Do you know why the reset times out/fails?\n> > > > > \n> > > > \n> > > > Because there are nothing connected to it.\n> > > \n> > > That should not be an issue. A read should just return 0xffff. And it\n> > > should return 0xffff fast. The timing of the MDIO protocol is fixed. A\n> > > read or a write takes a fixed number of cycles, independent of if\n> > > there is a device there or not. The bus data line has a pullup, so if\n> > > you try to access a missing device, you automatically read 0xffff.\n> > > \n> > \n> > Perhaps, but the reality is that with nothing connected to it, the reset of the MAC timeout.\n> > Certainly, the MAC does not support finding no PHY.\n> \n> Are you sure this is not because of the clock and reset?\n> \n> + #address-cells = <1>;\n> + #size-cells = <0>;\n> + int_mii_phy: ethernet-phy@1 {\n> + compatible = \"ethernet-phy-ieee802.3-c22\";\n> + reg = <1>;\n> + clocks = <&ccu CLK_BUS_EPHY>;\n> + resets = <&ccu RST_BUS_EPHY>;\n> \n> The way you describe it here, the clock and reset are for the PHY. But\n> maybe it is actually for the bus? I can understand a bus timing out if\n> it has no clock, or it is held in reset. Try enabling the clock and\n> reset when the internal bus is selected, not when the PHY on the bus\n> is selected.\n> \n\nEven with CLK_BUS_EPHY/RST_BUS_EPHY enabled, the MAC reset timeout.\nSo no the CLK/RST are really for the PHY.\n\nRegards\n\nPS: patch and result with \"integrated CLK/RST always on\"\n--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c\n+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c\n@@ -659,7 +659,7 @@ static int mdio_mux_syscon_switch_fn(int current_child, int desired_child,\n struct sunxi_priv_data *gmac = priv->plat->bsp_priv;\n u32 reg, val;\n int ret = 0;\n- bool need_reset = false;\n+ bool need_reset = true;\n \n if (current_child ^ desired_child) {\n regmap_read(gmac->regmap, SYSCON_EMAC_REG, ®);\n@@ -824,7 +824,7 @@ static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv)\n int ret;\n \n if (!gmac->use_internal_phy)\n- return 0;\n+ dev_info(priv->device, \"IPHY BYPASS\\n\");\n \n ret = clk_prepare_enable(gmac->ephy_clk);\n if (ret) {\n\n[ 18.057162] dwmac-sun8i 1c30000.ethernet: Will use external PHY\n[ 18.183789] dwmac-sun8i 1c30000.ethernet: IPHY BYPASS\n[ 18.184136] dwmac-sun8i 1c30000.ethernet: Chain mode enabled\n[ 18.184158] dwmac-sun8i 1c30000.ethernet: No HW DMA feature register supported\n[ 18.184175] dwmac-sun8i 1c30000.ethernet: Normal descriptors\n[ 18.184192] dwmac-sun8i 1c30000.ethernet: RX Checksum Offload Engine supported\n[ 18.184214] dwmac-sun8i 1c30000.ethernet: COE Type 2\n[ 18.184231] dwmac-sun8i 1c30000.ethernet: TX Checksum insertion supported\n[ 18.185491] libphy: stmmac: probed\n[ 18.188481] libphy: mdio_mux: probed\n[ 18.188831] dwmac-sun8i 1c30000.ethernet: Switch mux to internal PHY\n[ 18.288981] dwmac-sun8i 1c30000.ethernet: EMAC reset timeout\n[ 18.289559] libphy: mdio_mux: probed\n[ 18.289629] dwmac-sun8i 1c30000.ethernet: Switch mux to external PHY\n[ 20.578316] EXT4-fs (mmcblk0p1): re-mounted. Opts: (null)\n[ 31.240650] RTL8211E Gigabit Ethernet 0.1:00: attached PHY driver [RTL8211E Gigabit Ethernet] (mii_bus:phy_addr=0.1:00, irq=POLL)","headers":{"Return-Path":"","X-Original-To":"patchwork-incoming@ozlabs.org","Delivered-To":"patchwork-incoming@ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=netdev-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"ioGLJS/h\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xrct56bQPz9s7g\n\tfor ;\n\tTue, 12 Sep 2017 05:09:17 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751038AbdIKTJI (ORCPT );\n\tMon, 11 Sep 2017 15:09:08 -0400","from mail-wr0-f181.google.com ([209.85.128.181]:33677 \"EHLO\n\tmail-wr0-f181.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1750911AbdIKTJG (ORCPT\n\t); Mon, 11 Sep 2017 15:09:06 -0400","by mail-wr0-f181.google.com with SMTP id a43so16584870wrc.0;\n\tMon, 11 Sep 2017 12:09:05 -0700 (PDT)","from Red ([2a01:cb1d:16e:1300:2e56:dcff:fed2:c6d6])\n\tby smtp.googlemail.com with ESMTPSA id\n\tr15sm5078050wrc.30.2017.09.11.12.09.03\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tMon, 11 Sep 2017 12:09:04 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=gmail.com; s=20161025;\n\th=date:from:to:cc:subject:message-id:references:mime-version\n\t:content-disposition:in-reply-to:user-agent;\n\tbh=ZHKSqmLeuhZKPfo7llEyACDZfohFxT37P6Tqpm8c3FI=;\n\tb=ioGLJS/hRqkYyajcy2f0TX4JK8oBSAvM2dQ5f6MtPUc1AAn1Rz+SG6h9l3En1zRjMS\n\t4/eicRcl2Tlgnlj57b5xQ/iFDHc75ZrJyDjj1ziapAZPkgFjR/7+DoKUpF2rkY3+DdHm\n\twuwlCFD/0wgw8+crKutpO8j3oNVINz/Leb8G/PZORH/fW63tA9khII3y2EjjKwh24DMx\n\tTTCKVlmMKgaN0O9ldvPq0QZsewV9uPzVn4jIV5qSxVge5rAePmv33VCw9p+gCsOMEeHb\n\t29f6UdMyb8+HBDTjUnv3jj/wWqRffSsFCJQv615Rvk9sXHRXnu7NG/yCt8bSYWGJt5st\n\t47iw==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:date:from:to:cc:subject:message-id:references\n\t:mime-version:content-disposition:in-reply-to:user-agent;\n\tbh=ZHKSqmLeuhZKPfo7llEyACDZfohFxT37P6Tqpm8c3FI=;\n\tb=BjLNr/1tzu9/ruIz8vVm43L4HwGq5tVKvBztgI88gUv4l8lFsTavSYnYJ8q16PZVrG\n\tWLtYCIDRKI/xIMkSUfI6BaveWrhGq1OCRKezg0b+e/lOvM+CV2geF1Ket4VtnG7+XtSh\n\tQ9R171gmD7XIHA1zw4OsG2bZnO2Ur0mhp/V5nXsssOfVTaBpotr/Ig9PxUrGRVRp6K2u\n\tVUzAjk/fMpmpvxAAdBqRxLxZ1JsDtg9yHWR+2G2TrknUYxaV+A/oswvTy7OQ+S99ctOZ\n\tQmMXJE11i7/sV8zhJ6j8C2dOLa0IMk0w/IBcxWD3TbaOQl6PcrgsfVcUDnqwezHikVsO\n\tfeIg==","X-Gm-Message-State":"AHPjjUiQm70tNqOhs3ZfO+FCk9hav2yHFS9gR9w0qe9BKoF12GlrPQOJ\n\tiCiiHVuZnk0GoQ==","X-Google-Smtp-Source":"ADKCNb7xTctWpNOwYcwHCUSSWx80C2SZegtuMokA3sP+GY2RuxrXZDsbQYVnNuicDxXMoz+8ZGsRzA==","X-Received":"by 10.223.182.137 with SMTP id j9mr9367503wre.150.1505156944889; \n\tMon, 11 Sep 2017 12:09:04 -0700 (PDT)","Date":"Mon, 11 Sep 2017 21:08:50 +0200","From":"Corentin Labbe ","To":"Andrew Lunn ","Cc":"robh+dt@kernel.org, mark.rutland@arm.com,\n\tmaxime.ripard@free-electrons.com, wens@csie.org,\n\tlinux@armlinux.org.uk, catalin.marinas@arm.com,\n\twill.deacon@arm.com, peppe.cavallaro@st.com,\n\talexandre.torgue@st.com, f.fainelli@gmail.com,\n\tnetdev@vger.kernel.org, devicetree@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org","Subject":"Re: [PATCH v5 10/10] net: stmmac: dwmac-sun8i: Handle\n\tintegrated/external MDIOs","Message-ID":"<20170911190850.GA2291@Red>","References":"<20170908071156.5115-1-clabbe.montjoie@gmail.com>\n\t<20170908071156.5115-11-clabbe.montjoie@gmail.com>\n\t<20170908130520.GA11248@lunn.ch> <20170908132632.GA3037@Red>\n\t<20170908140020.GC25219@lunn.ch> <20170908140832.GB3037@Red>\n\t<20170908141736.GF25219@lunn.ch> <20170908142825.GC3037@Red>\n\t<20170911161124.GD27599@lunn.ch>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170911161124.GD27599@lunn.ch>","User-Agent":"Mutt/1.7.2 (2016-11-26)","Sender":"netdev-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"netdev@vger.kernel.org"}},{"id":1766513,"web_url":"http://patchwork.ozlabs.org/comment/1766513/","msgid":"<20170911201920.GA5983@lunn.ch>","list_archive_url":null,"date":"2017-09-11T20:19:20","subject":"Re: [PATCH v5 10/10] net: stmmac: dwmac-sun8i: Handle\n\tintegrated/external MDIOs","submitter":{"id":13608,"url":"http://patchwork.ozlabs.org/api/people/13608/","name":"Andrew Lunn","email":"andrew@lunn.ch"},"content":"> Even with CLK_BUS_EPHY/RST_BUS_EPHY enabled, the MAC reset timeout.\n> So no the CLK/RST are really for the PHY.\n\nThanks for trying that.\n\nYou said it was probably during scanning of the bus it times out. What\naddress is causing the timeout? 0 or 1? If the internal bus can only\nhave one PHY on it, maybe we need to set bus->phy_mask to 0x1?\n\n Andrew","headers":{"Return-Path":"","X-Original-To":"patchwork-incoming@ozlabs.org","Delivered-To":"patchwork-incoming@ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=netdev-owner@vger.kernel.org;\n\treceiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xrfRP21tBz9s5L\n\tfor ;\n\tTue, 12 Sep 2017 06:19:45 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751052AbdIKUTf (ORCPT );\n\tMon, 11 Sep 2017 16:19:35 -0400","from vps0.lunn.ch ([178.209.37.122]:37507 \"EHLO vps0.lunn.ch\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1750853AbdIKUTd (ORCPT );\n\tMon, 11 Sep 2017 16:19:33 -0400","from andrew by vps0.lunn.ch with local (Exim 4.84_2)\n\t(envelope-from )\n\tid 1drVAu-0001bU-Ec; Mon, 11 Sep 2017 22:19:20 +0200"],"Date":"Mon, 11 Sep 2017 22:19:20 +0200","From":"Andrew Lunn ","To":"Corentin Labbe ","Cc":"robh+dt@kernel.org, mark.rutland@arm.com,\n\tmaxime.ripard@free-electrons.com, wens@csie.org,\n\tlinux@armlinux.org.uk, catalin.marinas@arm.com,\n\twill.deacon@arm.com, peppe.cavallaro@st.com,\n\talexandre.torgue@st.com, f.fainelli@gmail.com,\n\tnetdev@vger.kernel.org, devicetree@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org","Subject":"Re: [PATCH v5 10/10] net: stmmac: dwmac-sun8i: Handle\n\tintegrated/external MDIOs","Message-ID":"<20170911201920.GA5983@lunn.ch>","References":"<20170908071156.5115-1-clabbe.montjoie@gmail.com>\n\t<20170908071156.5115-11-clabbe.montjoie@gmail.com>\n\t<20170908130520.GA11248@lunn.ch> <20170908132632.GA3037@Red>\n\t<20170908140020.GC25219@lunn.ch> <20170908140832.GB3037@Red>\n\t<20170908141736.GF25219@lunn.ch> <20170908142825.GC3037@Red>\n\t<20170911161124.GD27599@lunn.ch> <20170911190850.GA2291@Red>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170911190850.GA2291@Red>","User-Agent":"Mutt/1.5.23 (2014-03-12)","Sender":"netdev-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"netdev@vger.kernel.org"}},{"id":1766736,"web_url":"http://patchwork.ozlabs.org/comment/1766736/","msgid":"<20170912075415.GA1358@Red>","list_archive_url":null,"date":"2017-09-12T07:54:15","subject":"Re: [PATCH v5 10/10] net: stmmac: dwmac-sun8i: Handle\n\tintegrated/external MDIOs","submitter":{"id":64152,"url":"http://patchwork.ozlabs.org/api/people/64152/","name":"Corentin Labbe","email":"clabbe.montjoie@gmail.com"},"content":"On Mon, Sep 11, 2017 at 10:19:20PM +0200, Andrew Lunn wrote:\n> > Even with CLK_BUS_EPHY/RST_BUS_EPHY enabled, the MAC reset timeout.\n> > So no the CLK/RST are really for the PHY.\n> \n> Thanks for trying that.\n> \n> You said it was probably during scanning of the bus it times out. What\n> address is causing the timeout? 0 or 1? If the internal bus can only\n> have one PHY on it, maybe we need to set bus->phy_mask to 0x1?\n> \n\nI have added a trace in begin and end of stmmac_mdio_read()\n\n[ 18.145451] libphy: stmmac: probed\n[ 18.148398] libphy: mdio_mux: probed\n[ 18.148650] dwmac-sun8i 1c30000.ethernet: Switch mux to internal PHY\n[ 18.248751] dwmac-sun8i 1c30000.ethernet: EMAC reset timeout\n[ 18.249297] libphy: mdio_mux: probed\n[ 18.249362] dwmac-sun8i 1c30000.ethernet: Switch mux to external PHY\n[ 18.249391] stmmac_mdio_read 0 2\n[ 18.249598] stmmac_mdio_read 0 2 1c\n[ 18.249623] stmmac_mdio_read 0 3\n[ 18.249811] stmmac_mdio_read 0 3 c915\n[ 20.737271] EXT4-fs (mmcblk0p1): re-mounted. Opts: (null)\n[ 31.294868] stmmac_mdio_read 0 0\n[ 31.295311] stmmac_mdio_read 0 0 1140\n\nIt seems that the timeout is unrelated to MDIO bus.\n\nRegards","headers":{"Return-Path":"","X-Original-To":"patchwork-incoming@ozlabs.org","Delivered-To":"patchwork-incoming@ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=netdev-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"Dp0EP04w\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xrxs83rjlz9s7B\n\tfor ;\n\tTue, 12 Sep 2017 17:54:36 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751366AbdILHy0 (ORCPT );\n\tTue, 12 Sep 2017 03:54:26 -0400","from mail-wr0-f176.google.com ([209.85.128.176]:33355 \"EHLO\n\tmail-wr0-f176.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751089AbdILHyY (ORCPT\n\t); Tue, 12 Sep 2017 03:54:24 -0400","by mail-wr0-f176.google.com with SMTP id a43so18847821wrc.0;\n\tTue, 12 Sep 2017 00:54:23 -0700 (PDT)","from Red ([2a01:cb1d:16e:1300:2e56:dcff:fed2:c6d6])\n\tby smtp.googlemail.com with ESMTPSA id\n\tn6sm7479539wmg.11.2017.09.12.00.54.21\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tTue, 12 Sep 2017 00:54:22 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=gmail.com; s=20161025;\n\th=date:from:to:cc:subject:message-id:references:mime-version\n\t:content-disposition:in-reply-to:user-agent;\n\tbh=YIBazUM2EgCh0VN8t9kDwV+QxrDefETvCWH0it0C/NU=;\n\tb=Dp0EP04wgeZL5EtBNuIouN/sbkbAVKWPB7Z1k8vr/ddTHilsJAwzJx7Ru8jCTxtEt8\n\tExzkLVOJbgaaDkLnBFOjhsUSNHhbo94G+tlnbzsLLPLtu2CegCypNvoxVHS5t6c0PexC\n\tJE1xBiEPk3WmvhaYEyzxjpQQBEwNkVjpxHiRD4kKNtUOy7Tu4NJoGrstaRjyxzGqmgRF\n\tO45IT181kbSCKP0FUXb3JPwlqyms8m2U+MZBJeJ58jSxzNd+TMw8axHiaJNZfMvQOkPF\n\tOVOw6O4Jg+3xGal2Ong2e995gA0w1Tc0pGaVjuDn98kLbaDAUP3x85OPJZ4uSNN3ZDiP\n\tLTew==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:date:from:to:cc:subject:message-id:references\n\t:mime-version:content-disposition:in-reply-to:user-agent;\n\tbh=YIBazUM2EgCh0VN8t9kDwV+QxrDefETvCWH0it0C/NU=;\n\tb=TIZDmxsEXoJiK7Ybcuua4zTIEMxopeIxaaIU/R9QojIzUkxBPd2/Vww0BXuZsaK7TS\n\tdf0vwfRApR173X6HimwHtP4Q6jV52UJcqZChABMIETXWyLIPlPUu1RxSX/prlFjd9I/T\n\tyTE+tlK0dEP6zWX5yqWKMux2vzZQXkVQHJy3mEuoFSiteB1zgo4H0wuowYcg4KQWBsa6\n\tGdi0FdBey2F2NBdZ9zVTy0s/iqGJ9jrm//Z+S1sKALrCxBuWcpDxq4JkGQhaIP5jIIL/\n\tvg3vNZ3xcbCMP6pIsMSwaPOFtXb588ACJL8czNrFGg9djm+1kf8pbYoGEWtEbZK72qEr\n\ty8mw==","X-Gm-Message-State":"AHPjjUjtzJ1x85TLW/TsAs/xEX0PJXtuW6qFaSs5LSntX8i1cHLXDeru\n\tqqgdkhe6xtwoeQ==","X-Google-Smtp-Source":"ADKCNb6rFYmG9ggRqEQqniuu0MYwRO1263fhZcUTBm2rC8ARePwUqgplXVukpMJb3e7Zwwmppc05+Q==","X-Received":"by 10.223.177.18 with SMTP id l18mr9086184wra.167.1505202862812; \n\tTue, 12 Sep 2017 00:54:22 -0700 (PDT)","Date":"Tue, 12 Sep 2017 09:54:15 +0200","From":"Corentin Labbe ","To":"Andrew Lunn ","Cc":"robh+dt@kernel.org, mark.rutland@arm.com,\n\tmaxime.ripard@free-electrons.com, wens@csie.org,\n\tlinux@armlinux.org.uk, catalin.marinas@arm.com,\n\twill.deacon@arm.com, peppe.cavallaro@st.com,\n\talexandre.torgue@st.com, f.fainelli@gmail.com,\n\tnetdev@vger.kernel.org, devicetree@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org","Subject":"Re: [PATCH v5 10/10] net: stmmac: dwmac-sun8i: Handle\n\tintegrated/external MDIOs","Message-ID":"<20170912075415.GA1358@Red>","References":"<20170908071156.5115-11-clabbe.montjoie@gmail.com>\n\t<20170908130520.GA11248@lunn.ch> <20170908132632.GA3037@Red>\n\t<20170908140020.GC25219@lunn.ch> <20170908140832.GB3037@Red>\n\t<20170908141736.GF25219@lunn.ch> <20170908142825.GC3037@Red>\n\t<20170911161124.GD27599@lunn.ch> <20170911190850.GA2291@Red>\n\t<20170911201920.GA5983@lunn.ch>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170911201920.GA5983@lunn.ch>","User-Agent":"Mutt/1.7.2 (2016-11-26)","Sender":"netdev-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"netdev@vger.kernel.org"}}]