[{"id":1764911,"web_url":"http://patchwork.ozlabs.org/comment/1764911/","msgid":"","list_archive_url":null,"date":"2017-09-07T19:41:40","subject":"Re: [PATCH v4 6/6] gpio: uniphier: add UniPhier GPIO controller\n\tdriver","submitter":{"id":67416,"url":"http://patchwork.ozlabs.org/api/people/67416/","name":"Rob Herring","email":"robh+dt@kernel.org"},"content":"On Thu, Sep 7, 2017 at 6:42 AM, Masahiro Yamada\n wrote:\n> This GPIO controller device is used on UniPhier SoCs.\n>\n> It also serves as an interrupt controller, but interrupt signals are\n> just delivered to the parent irqchip without any latching or OR'ing.\n> This is implemented by using hierarchy IRQ domain.\n>\n> Implementation note:\n> Unfortunately, the IRQ mapping from this controller to the parent is\n> random. (48, 49, ..., 63, 154, 155, ...)\n> If \"interrupts\" property is used, IRQ resources may be statically\n> allocated when platform devices are populated from DT. This can be\n> a problem for the hierarchy IRQ domain because IRQ allocation must\n> happen from the outer-most domain up to the root domain in order to\n> build up the stacked IRQ. (https://lkml.org/lkml/2017/7/6/758)\n> Solutions to work around it could be to hard-code parent hwirqs or\n> to invent a driver-specific DT property.\n>\n> Here, the new API irq_domain_push_irq() was merged by v4.14-rc1.\n> It allows to add irq_data to the existing hierarchy. It will help\n> to make this driver work whether the parent has already initialized\n> the hierarchy or not.\n>\n> Signed-off-by: Masahiro Yamada \n> ---\n>\n> Changes in v4:\n> - Add COMPILE_TEST and select IRQ_DOMAIN_HIERARCHY\n> - Reimplement irqchip part by using irq_domain_push_irq()\n>\n> Changes in v3:\n> - Add .irq_set_affinity() hook\n> - Use irq_domain_create_hierarchy() instead of legacy\n> irq_domain_add_hierarchy()\n>\n> Changes in v2:\n> - Remove +32 offset for parent interrupts to follow the GIC\n> binding convention\n> - Let uniphier_gpio_irq_alloc() fail if nr_irqs != 1\n> - Allocate gpio_chip statically because just one instance is\n> supported\n> - Fix suspend and resume hooks\n>\n> .../devicetree/bindings/gpio/gpio-uniphier.txt | 43 ++\n\nWhat happened to my ack? One line here more that before, but I'm not\ngoing to diff your patches for you.\n\nBTW, it is preferred to split bindings to a separate patch.\n\n> MAINTAINERS | 1 +\n> drivers/gpio/Kconfig | 8 +\n> drivers/gpio/Makefile | 1 +\n> drivers/gpio/gpio-uniphier.c | 486 +++++++++++++++++++++\n> include/dt-bindings/gpio/uniphier-gpio.h | 18 +\n> 6 files changed, 557 insertions(+)\n> create mode 100644 Documentation/devicetree/bindings/gpio/gpio-uniphier.txt\n> create mode 100644 drivers/gpio/gpio-uniphier.c\n> create mode 100644 include/dt-bindings/gpio/uniphier-gpio.h\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","mail.kernel.org;\n\tdmarc=none (p=none dis=none) header.from=kernel.org","mail.kernel.org;\n\tspf=none smtp.mailfrom=robh+dt@kernel.org"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xp9nn5Bp5z9t16\n\tfor ;\n\tFri, 8 Sep 2017 05:42:05 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1755584AbdIGTmD (ORCPT\n\t);\n\tThu, 7 Sep 2017 15:42:03 -0400","from mail.kernel.org ([198.145.29.99]:53790 \"EHLO mail.kernel.org\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1754859AbdIGTmC (ORCPT );\n\tThu, 7 Sep 2017 15:42:02 -0400","from mail-qk0-f173.google.com (mail-qk0-f173.google.com\n\t[209.85.220.173])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\tby mail.kernel.org (Postfix) with ESMTPSA id E82DD21B81;\n\tThu, 7 Sep 2017 19:42:01 +0000 (UTC)","by mail-qk0-f173.google.com with SMTP id o129so1765240qkd.0;\n\tThu, 07 Sep 2017 12:42:01 -0700 (PDT)","by 10.12.153.1 with HTTP; Thu, 7 Sep 2017 12:41:40 -0700 (PDT)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mail.kernel.org E82DD21B81","X-Gm-Message-State":"AHPjjUgh6R3byoBQhsxxABJZZZUzLUPBxTOaxou2UBq5eeNrN3qlVYd8\n\tzuUKu5bilZZws2rcIGpNWKXKz/Intw==","X-Google-Smtp-Source":"AOwi7QDtzaPSfQ/GjDy/HhKpsnghiyaE4TrO+oN33nQo3u2wYZYG9qS+SeBKGXugKY9K9Blf2pEEuqhFtALzF6CZ69A=","X-Received":"by 10.55.33.75 with SMTP id h72mr626150qkh.132.1504813321115;\n\tThu, 07 Sep 2017 12:42:01 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"<1504784522-26841-7-git-send-email-yamada.masahiro@socionext.com>","References":"<1504784522-26841-1-git-send-email-yamada.masahiro@socionext.com>\n\t<1504784522-26841-7-git-send-email-yamada.masahiro@socionext.com>","From":"Rob Herring ","Date":"Thu, 7 Sep 2017 14:41:40 -0500","X-Gmail-Original-Message-ID":"","Message-ID":"","Subject":"Re: [PATCH v4 6/6] gpio: uniphier: add UniPhier GPIO controller\n\tdriver","To":"Masahiro Yamada ","Cc":"Marc Zyngier , Thomas Gleixner ,\n\tLinus Walleij ,\n\t\"linux-gpio@vger.kernel.org\" ,\n\tJassi Brar ,\n\t\"devicetree@vger.kernel.org\" ,\n\tJason Cooper ,\n\tMasami Hiramatsu ,\n\tDavid Daney ,\n\t\"linux-kernel@vger.kernel.org\" ,\n\tMark Rutland ,\n\t\"linux-arm-kernel@lists.infradead.org\" \n\t","Content-Type":"text/plain; charset=\"UTF-8\"","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1765452,"web_url":"http://patchwork.ozlabs.org/comment/1765452/","msgid":"","list_archive_url":null,"date":"2017-09-08T15:14:45","subject":"Re: [PATCH v4 6/6] gpio: uniphier: add UniPhier GPIO controller\n\tdriver","submitter":{"id":65882,"url":"http://patchwork.ozlabs.org/api/people/65882/","name":"Masahiro Yamada","email":"yamada.masahiro@socionext.com"},"content":"Hi Rob,\n\n\n2017-09-08 4:41 GMT+09:00 Rob Herring :\n> On Thu, Sep 7, 2017 at 6:42 AM, Masahiro Yamada\n> wrote:\n>> This GPIO controller device is used on UniPhier SoCs.\n>>\n>> It also serves as an interrupt controller, but interrupt signals are\n>> just delivered to the parent irqchip without any latching or OR'ing.\n>> This is implemented by using hierarchy IRQ domain.\n>>\n>> Implementation note:\n>> Unfortunately, the IRQ mapping from this controller to the parent is\n>> random. (48, 49, ..., 63, 154, 155, ...)\n>> If \"interrupts\" property is used, IRQ resources may be statically\n>> allocated when platform devices are populated from DT. This can be\n>> a problem for the hierarchy IRQ domain because IRQ allocation must\n>> happen from the outer-most domain up to the root domain in order to\n>> build up the stacked IRQ. (https://lkml.org/lkml/2017/7/6/758)\n>> Solutions to work around it could be to hard-code parent hwirqs or\n>> to invent a driver-specific DT property.\n>>\n>> Here, the new API irq_domain_push_irq() was merged by v4.14-rc1.\n>> It allows to add irq_data to the existing hierarchy. It will help\n>> to make this driver work whether the parent has already initialized\n>> the hierarchy or not.\n>>\n>> Signed-off-by: Masahiro Yamada \n>> ---\n>>\n>> Changes in v4:\n>> - Add COMPILE_TEST and select IRQ_DOMAIN_HIERARCHY\n>> - Reimplement irqchip part by using irq_domain_push_irq()\n>>\n>> Changes in v3:\n>> - Add .irq_set_affinity() hook\n>> - Use irq_domain_create_hierarchy() instead of legacy\n>> irq_domain_add_hierarchy()\n>>\n>> Changes in v2:\n>> - Remove +32 offset for parent interrupts to follow the GIC\n>> binding convention\n>> - Let uniphier_gpio_irq_alloc() fail if nr_irqs != 1\n>> - Allocate gpio_chip statically because just one instance is\n>> supported\n>> - Fix suspend and resume hooks\n>>\n>> .../devicetree/bindings/gpio/gpio-uniphier.txt | 43 ++\n>\n> What happened to my ack? One line here more that before, but I'm not\n> going to diff your patches for you.\n\nI changed the binding for this version.\nIt includes a new one you have not acked yet.\n\nMaybe I was too worried about it.\n\n\n> BTW, it is preferred to split bindings to a separate patch.\n\nI will do so next time.","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=nifty.com header.i=@nifty.com\n\theader.b=\"gRmvelnp\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xpgqm5WKyz9sBZ\n\tfor ;\n\tSat, 9 Sep 2017 01:15:32 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1753243AbdIHPPb (ORCPT\n\t);\n\tFri, 8 Sep 2017 11:15:31 -0400","from conssluserg-06.nifty.com ([210.131.2.91]:17376 \"EHLO\n\tconssluserg-06.nifty.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1752538AbdIHPPa (ORCPT\n\t); Fri, 8 Sep 2017 11:15:30 -0400","from mail-yw0-f173.google.com (mail-yw0-f173.google.com\n\t[209.85.161.173]) (authenticated)\n\tby conssluserg-06.nifty.com with ESMTP id v88FFQQq019546;\n\tSat, 9 Sep 2017 00:15:27 +0900","by mail-yw0-f173.google.com with SMTP id q80so8331813ywg.2;\n\tFri, 08 Sep 2017 08:15:27 -0700 (PDT)","by 10.37.164.225 with HTTP; Fri, 8 Sep 2017 08:14:45 -0700 (PDT)"],"DKIM-Filter":"OpenDKIM Filter v2.10.3 conssluserg-06.nifty.com v88FFQQq019546","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com;\n\ts=dec2015msa; t=1504883727;\n\tbh=VkbtTeo8hP07JKFcZWZm5AdZ1TrUG9qXFxCyP1PwAj0=;\n\th=In-Reply-To:References:From:Date:Subject:To:Cc:From;\n\tb=gRmvelnplc/wtL8mvB9nNbnnofEtZjeLGGDbRmLhvQR+HrznzGymmqxEnrZtuRo/b\n\tgBQ8KCTIkNo8lVzZYYM/xgwElDp5Scow6QBWH3/VeVKmG5t2zJmVVrLVTH1D7JX08i\n\t+gS9CK8wfBE0EMIkfIxmqzKZYuM7RvBzMHVVOmWE/5Pft/v9NULfO7ncVvaghcr6nF\n\tbRsuS1RQ2LceAXQIcpSyrowLe+mcJBJ6vBoYSMDGX6EVAcjqxdBy4Wh3Dzvb8ldGIj\n\ts9ERnh878qXsizTfr+9UHj4Hd/STrs5xeKLTvP715a2bfv09m8LUlJ1E2aF7GpX8j8\n\tMuQAH5/rJhi7Q==","X-Nifty-SrcIP":"[209.85.161.173]","X-Gm-Message-State":"AHPjjUgnZBez4T/lO5gsKvHjJdzgFHiocPT4lahyMRH4S6yWqqlYEi8X\n\thNIHCQrwj/NTuK3hsgNqvgiz7WARYw==","X-Google-Smtp-Source":"ADKCNb5o7x+6gK/AG4m58cAbr0fLaw0t2fdmKNmt4rx61SbJkpusKz648sL+Stby+0ao9nqB27lo92lnZsqan/kVT9w=","X-Received":"by 10.37.173.2 with SMTP id y2mr2733648ybi.113.1504883725800;\n\tFri, 08 Sep 2017 08:15:25 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"","References":"<1504784522-26841-1-git-send-email-yamada.masahiro@socionext.com>\n\t<1504784522-26841-7-git-send-email-yamada.masahiro@socionext.com>\n\t","From":"Masahiro Yamada ","Date":"Sat, 9 Sep 2017 00:14:45 +0900","X-Gmail-Original-Message-ID":"","Message-ID":"","Subject":"Re: [PATCH v4 6/6] gpio: uniphier: add UniPhier GPIO controller\n\tdriver","To":"Rob Herring ","Cc":"Marc Zyngier , Thomas Gleixner ,\n\tLinus Walleij ,\n\t\"linux-gpio@vger.kernel.org\" ,\n\tJassi Brar ,\n\t\"devicetree@vger.kernel.org\" ,\n\tJason Cooper ,\n\tMasami Hiramatsu ,\n\tDavid Daney ,\n\t\"linux-kernel@vger.kernel.org\" ,\n\tMark Rutland ,\n\t\"linux-arm-kernel@lists.infradead.org\" \n\t","Content-Type":"text/plain; charset=\"UTF-8\"","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1765941,"web_url":"http://patchwork.ozlabs.org/comment/1765941/","msgid":"<201709102009.mXD4Fpgu%fengguang.wu@intel.com>","list_archive_url":null,"date":"2017-09-10T12:13:23","subject":"Re: [PATCH v4 6/6] gpio: uniphier: add UniPhier GPIO controller\n\tdriver","submitter":{"id":67315,"url":"http://patchwork.ozlabs.org/api/people/67315/","name":"kernel test robot","email":"lkp@intel.com"},"content":"Hi Masahiro,\n\n[auto build test ERROR on tip/irq/core]\n[also build test ERROR on next-20170908]\n[cannot apply to v4.13]\n[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]\n\nurl: https://github.com/0day-ci/linux/commits/Masahiro-Yamada/irqdomain-gpio-expand-irq_domain_push_irq-for-DT-use-and-use-it-for-GPIO/20170910-160507\nconfig: i386-allmodconfig (attached as .config)\ncompiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901\nreproduce:\n # save the attached .config to linux build tree\n make ARCH=i386 \n\nAll errors (new ones prefixed by >>):\n\n>> ERROR: \"of_irq_count\" [drivers/gpio/gpio-uniphier.ko] undefined!\n\n---\n0-DAY kernel test infrastructure Open Source Technology Center\nhttps://lists.01.org/pipermail/kbuild-all Intel Corporation","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xqqjw6GNCz9sNw\n\tfor ;\n\tSun, 10 Sep 2017 22:14:28 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751460AbdIJMOZ (ORCPT\n\t);\n\tSun, 10 Sep 2017 08:14:25 -0400","from mga04.intel.com ([192.55.52.120]:10091 \"EHLO mga04.intel.com\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1751451AbdIJMOY (ORCPT );\n\tSun, 10 Sep 2017 08:14:24 -0400","from orsmga003.jf.intel.com ([10.7.209.27])\n\tby fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t10 Sep 2017 05:14:23 -0700","from bee.sh.intel.com (HELO bee) ([10.239.97.14])\n\tby orsmga003.jf.intel.com with ESMTP; 10 Sep 2017 05:14:19 -0700","from kbuild by bee with local (Exim 4.84_2)\n\t(envelope-from )\n\tid 1dr1Cq-000C2b-KU; Sun, 10 Sep 2017 20:19:20 +0800"],"X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos;i=\"5.42,372,1500966000\"; \n\td=\"gz'50?scan'50,208,50\";a=\"1012891897\"","Date":"Sun, 10 Sep 2017 20:13:23 +0800","From":"kbuild test robot ","To":"Masahiro Yamada ","Cc":"kbuild-all@01.org, Marc Zyngier ,\n\tThomas Gleixner ,\n\tLinus Walleij ,\n\tlinux-gpio@vger.kernel.org, Rob Herring ,\n\tJassi Brar ,\n\tdevicetree@vger.kernel.org, Jason Cooper ,\n\tMasami Hiramatsu ,\n\tDavid Daney ,\n\tMasahiro Yamada ,\n\tlinux-kernel@vger.kernel.org, Mark Rutland ,\n\tlinux-arm-kernel@lists.infradead.org","Subject":"Re: [PATCH v4 6/6] gpio: uniphier: add UniPhier GPIO controller\n\tdriver","Message-ID":"<201709102009.mXD4Fpgu%fengguang.wu@intel.com>","MIME-Version":"1.0","Content-Type":"multipart/mixed; boundary=\"BOKacYhQ+x31HxR3\"","Content-Disposition":"inline","In-Reply-To":"<1504784522-26841-7-git-send-email-yamada.masahiro@socionext.com>","User-Agent":"Mutt/1.5.23 (2014-03-12)","X-SA-Exim-Connect-IP":"","X-SA-Exim-Mail-From":"fengguang.wu@intel.com","X-SA-Exim-Scanned":"No (on bee); SAEximRunCond expanded to false","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1766507,"web_url":"http://patchwork.ozlabs.org/comment/1766507/","msgid":"<20170911201515.d4vki3yhrywpmdvc@rob-hp-laptop>","list_archive_url":null,"date":"2017-09-11T20:15:15","subject":"Re: [PATCH v4 6/6] gpio: uniphier: add UniPhier GPIO controller\n\tdriver","submitter":{"id":62529,"url":"http://patchwork.ozlabs.org/api/people/62529/","name":"Rob Herring (Arm)","email":"robh@kernel.org"},"content":"On Sat, Sep 09, 2017 at 12:14:45AM +0900, Masahiro Yamada wrote:\n> Hi Rob,\n> \n> \n> 2017-09-08 4:41 GMT+09:00 Rob Herring :\n> > On Thu, Sep 7, 2017 at 6:42 AM, Masahiro Yamada\n> > wrote:\n> >> This GPIO controller device is used on UniPhier SoCs.\n> >>\n> >> It also serves as an interrupt controller, but interrupt signals are\n> >> just delivered to the parent irqchip without any latching or OR'ing.\n> >> This is implemented by using hierarchy IRQ domain.\n> >>\n> >> Implementation note:\n> >> Unfortunately, the IRQ mapping from this controller to the parent is\n> >> random. (48, 49, ..., 63, 154, 155, ...)\n> >> If \"interrupts\" property is used, IRQ resources may be statically\n> >> allocated when platform devices are populated from DT. This can be\n> >> a problem for the hierarchy IRQ domain because IRQ allocation must\n> >> happen from the outer-most domain up to the root domain in order to\n> >> build up the stacked IRQ. (https://lkml.org/lkml/2017/7/6/758)\n> >> Solutions to work around it could be to hard-code parent hwirqs or\n> >> to invent a driver-specific DT property.\n> >>\n> >> Here, the new API irq_domain_push_irq() was merged by v4.14-rc1.\n> >> It allows to add irq_data to the existing hierarchy. It will help\n> >> to make this driver work whether the parent has already initialized\n> >> the hierarchy or not.\n> >>\n> >> Signed-off-by: Masahiro Yamada \n> >> ---\n> >>\n> >> Changes in v4:\n> >> - Add COMPILE_TEST and select IRQ_DOMAIN_HIERARCHY\n> >> - Reimplement irqchip part by using irq_domain_push_irq()\n> >>\n> >> Changes in v3:\n> >> - Add .irq_set_affinity() hook\n> >> - Use irq_domain_create_hierarchy() instead of legacy\n> >> irq_domain_add_hierarchy()\n> >>\n> >> Changes in v2:\n> >> - Remove +32 offset for parent interrupts to follow the GIC\n> >> binding convention\n> >> - Let uniphier_gpio_irq_alloc() fail if nr_irqs != 1\n> >> - Allocate gpio_chip statically because just one instance is\n> >> supported\n> >> - Fix suspend and resume hooks\n> >>\n> >> .../devicetree/bindings/gpio/gpio-uniphier.txt | 43 ++\n> >\n> > What happened to my ack? One line here more that before, but I'm not\n> > going to diff your patches for you.\n> \n> I changed the binding for this version.\n> It includes a new one you have not acked yet.\n> \n> Maybe I was too worried about it.\n\nProbably so, but I still don't know what you changed.\n\nRob\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xrfLZ39Rjz9sBZ\n\tfor ;\n\tTue, 12 Sep 2017 06:15:34 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751392AbdIKUPT (ORCPT\n\t);\n\tMon, 11 Sep 2017 16:15:19 -0400","from mail-io0-f195.google.com ([209.85.223.195]:36151 \"EHLO\n\tmail-io0-f195.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751076AbdIKUPR (ORCPT\n\t); Mon, 11 Sep 2017 16:15:17 -0400","by mail-io0-f195.google.com with SMTP id n69so2637942ioi.3;\n\tMon, 11 Sep 2017 13:15:17 -0700 (PDT)","from localhost (216-188-254-6.dyn.grandenetworks.net.\n\t[216.188.254.6]) by smtp.gmail.com with ESMTPSA id\n\ta199sm2726454oii.37.2017.09.11.13.15.15\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tMon, 11 Sep 2017 13:15:16 -0700 (PDT)"],"X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:date:from:to:cc:subject:message-id:references\n\t:mime-version:content-disposition:in-reply-to:user-agent;\n\tbh=bppTqGUNW0E1YsqOkW9w8YDAdVpI/0zRnWmEYPYrV5o=;\n\tb=W6N5kR5vzA/o0x3VigxF4oCFbNbPGt5kkkd4E/Lz6Z80bpq9BgFq0rv8BQou10GfH6\n\t2KWx60QM2U3rVnbcH0ClgkLOHTMTs5p5sPUIGk9HtMnKXQtRpm+D92tcBxTngJu6chSA\n\t4FjavXFiTFkw5xOgMAl40+Tb0avL429mL+bYSR4Iiy+sWB6fLdWwX1fmtZRoIE3/7aHi\n\tM0BvCVFhv1kYayLLkVUof7BUZefHS+Z633vTjo4Uxryc/Fin/3a4r7d9qRz26zeDpNiq\n\t35AqWSjnrVNQxIsPzqnrugaRGwgarlb16Q7Y5EuyF9cJg3h94EzmyXV29YYujBmG7y+k\n\t2Mrw==","X-Gm-Message-State":"AHPjjUhHogfhnvzRyhBj8GJM8nGi/knZURP9L2bRQV+ZehGKQugTL0Zr\n\tvNWNIh5oLWvY2sc4t2E=","X-Google-Smtp-Source":"AOwi7QC2MH+RoDg4JW6gA87IsdlcoDschUhdTxzaLxFFfui9El9YlI6R2qcOVoMDa8L7K1fiF79bGg==","X-Received":"by 10.202.73.76 with SMTP id w73mr13286488oia.233.1505160916656; \n\tMon, 11 Sep 2017 13:15:16 -0700 (PDT)","Date":"Mon, 11 Sep 2017 15:15:15 -0500","From":"Rob Herring ","To":"Masahiro Yamada ","Cc":"Marc Zyngier , Thomas Gleixner ,\n\tLinus Walleij ,\n\t\"linux-gpio@vger.kernel.org\" ,\n\tJassi Brar ,\n\t\"devicetree@vger.kernel.org\" ,\n\tJason Cooper ,\n\tMasami Hiramatsu ,\n\tDavid Daney ,\n\t\"linux-kernel@vger.kernel.org\" ,\n\tMark Rutland ,\n\t\"linux-arm-kernel@lists.infradead.org\" \n\t","Subject":"Re: [PATCH v4 6/6] gpio: uniphier: add UniPhier GPIO controller\n\tdriver","Message-ID":"<20170911201515.d4vki3yhrywpmdvc@rob-hp-laptop>","References":"<1504784522-26841-1-git-send-email-yamada.masahiro@socionext.com>\n\t<1504784522-26841-7-git-send-email-yamada.masahiro@socionext.com>\n\t\n\t","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"","User-Agent":"NeoMutt/20170113 (1.7.2)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1767089,"web_url":"http://patchwork.ozlabs.org/comment/1767089/","msgid":"","list_archive_url":null,"date":"2017-09-12T14:03:56","subject":"Re: [PATCH v4 6/6] gpio: uniphier: add UniPhier GPIO controller\n\tdriver","submitter":{"id":7055,"url":"http://patchwork.ozlabs.org/api/people/7055/","name":"Linus Walleij","email":"linus.walleij@linaro.org"},"content":"On Thu, Sep 7, 2017 at 1:42 PM, Masahiro Yamada\n wrote:\n\n> This GPIO controller device is used on UniPhier SoCs.\n>\n> It also serves as an interrupt controller, but interrupt signals are\n> just delivered to the parent irqchip without any latching or OR'ing.\n> This is implemented by using hierarchy IRQ domain.\n>\n> Implementation note:\n> Unfortunately, the IRQ mapping from this controller to the parent is\n> random. (48, 49, ..., 63, 154, 155, ...)\n> If \"interrupts\" property is used, IRQ resources may be statically\n> allocated when platform devices are populated from DT. This can be\n> a problem for the hierarchy IRQ domain because IRQ allocation must\n> happen from the outer-most domain up to the root domain in order to\n> build up the stacked IRQ. (https://lkml.org/lkml/2017/7/6/758)\n> Solutions to work around it could be to hard-code parent hwirqs or\n> to invent a driver-specific DT property.\n>\n> Here, the new API irq_domain_push_irq() was merged by v4.14-rc1.\n> It allows to add irq_data to the existing hierarchy. It will help\n> to make this driver work whether the parent has already initialized\n> the hierarchy or not.\n>\n> Signed-off-by: Masahiro Yamada \n> ---\n>\n> Changes in v4:\n> - Add COMPILE_TEST and select IRQ_DOMAIN_HIERARCHY\n> - Reimplement irqchip part by using irq_domain_push_irq()\n\nAwesome improvement. There was a build error and I also\nwould like David Daney to have a look at this so we know we\nuse things the right way, but overall I am happy after this\nso I hope I will be able to apply next version.\n\nYours,\nLinus Walleij\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"WfrqYiQh\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xs63N3JGmz9s7B\n\tfor ;\n\tWed, 13 Sep 2017 00:04:00 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751471AbdILOD6 (ORCPT\n\t);\n\tTue, 12 Sep 2017 10:03:58 -0400","from mail-io0-f176.google.com ([209.85.223.176]:36479 \"EHLO\n\tmail-io0-f176.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751469AbdILOD5 (ORCPT\n\t); Tue, 12 Sep 2017 10:03:57 -0400","by mail-io0-f176.google.com with SMTP id d16so47527196ioj.3\n\tfor ;\n\tTue, 12 Sep 2017 07:03:57 -0700 (PDT)","by 10.79.164.78 with HTTP; Tue, 12 Sep 2017 07:03:56 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=mime-version:in-reply-to:references:from:date:message-id:subject:to\n\t:cc; bh=RqGncLt1gYrVgWHFEsuiCU1z2o1QTE1nlUUC7PtGvrw=;\n\tb=WfrqYiQhsUr5NySr/vNsY69/kmuKhSbqn6uz+/eK3zafnhLVHn7LZ6SlQWvpK+3hIP\n\tQ+7qck6kFkWzZo3Cp9ba8Dhn7gh1pY+BIr/aPHzJgFSJ2bsJnuUR/WqeFkTwxMTudrI3\n\t9ZOZz/He6wipqi5k7dHG9dT4VXc2ZnURJqrqQ=","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:mime-version:in-reply-to:references:from:date\n\t:message-id:subject:to:cc;\n\tbh=RqGncLt1gYrVgWHFEsuiCU1z2o1QTE1nlUUC7PtGvrw=;\n\tb=n2cMGGTxQzRgL2lncdZUOJnW6QK2XXcvWPSEBAkh/UEayLQrn4WMTK/gecGhS7wNvP\n\t4JA8DP8fAgJNdvySdXAyu1re08JtW58tBiuwArz/nd1iKQfxL5/iTL/kRjQQCGhM6KGH\n\tN656J8CP8Xj6uIpeyBBtnSwZKa5+2Pc5RkC97DJfBrNitfhD4hzKyvuzZWcwIDpsBGzv\n\th1FhtyPf0c/H+4K5CVmilWXJeNXyDgbclpmRfcZntKEgiIOJSFLxdQJSuPOxyBgNJ/vl\n\tSX3TZUVNoC1j/jUcQxE7LeMhvPhN1Qx18T9ulbf9wjTTuhYdogMc7KjgA9bqW2vcIDf3\n\ttwRA==","X-Gm-Message-State":"AHPjjUgIlQD0JsoRjAVET/yHmPKrmG2z/KFOS0MsneAGLhnARHsPVvNz\n\tZaYsdHuy9A/viSgz/9LDqwlY/PIJf+j5","X-Google-Smtp-Source":"AOwi7QAfRoYrdC053VIBcTV5J9UrEPQUYiTUmDnhyx6PIouY/q3Vyf+26syc6wzmWerwpsiF7iZ33Za6ep+1KTKc4KI=","X-Received":"by 10.107.197.198 with SMTP id v189mr1625997iof.94.1505225037138;\n\tTue, 12 Sep 2017 07:03:57 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"<1504784522-26841-7-git-send-email-yamada.masahiro@socionext.com>","References":"<1504784522-26841-1-git-send-email-yamada.masahiro@socionext.com>\n\t<1504784522-26841-7-git-send-email-yamada.masahiro@socionext.com>","From":"Linus Walleij ","Date":"Tue, 12 Sep 2017 16:03:56 +0200","Message-ID":"","Subject":"Re: [PATCH v4 6/6] gpio: uniphier: add UniPhier GPIO controller\n\tdriver","To":"Masahiro Yamada ,\n\tDavid Daney ","Cc":"Marc Zyngier , Thomas Gleixner ,\n\t\"linux-gpio@vger.kernel.org\" ,\n\tRob Herring ,\n\tJassi Brar , \n\t\"devicetree@vger.kernel.org\" ,\n\tJason Cooper ,\n\tMasami Hiramatsu ,\n\t\"linux-kernel@vger.kernel.org\" ,\n\tMark Rutland ,\n\t\"linux-arm-kernel@lists.infradead.org\" \n\t","Content-Type":"text/plain; charset=\"UTF-8\"","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1767176,"web_url":"http://patchwork.ozlabs.org/comment/1767176/","msgid":"<7e46f2a3-114f-0c34-d3c5-49e6422b9200@caviumnetworks.com>","list_archive_url":null,"date":"2017-09-12T15:44:09","subject":"Re: [PATCH v4 6/6] gpio: uniphier: add UniPhier GPIO controller\n\tdriver","submitter":{"id":721,"url":"http://patchwork.ozlabs.org/api/people/721/","name":"David Daney","email":"ddaney@caviumnetworks.com"},"content":"On 09/12/2017 07:03 AM, Linus Walleij wrote:\n> On Thu, Sep 7, 2017 at 1:42 PM, Masahiro Yamada\n> wrote:\n> \n>> This GPIO controller device is used on UniPhier SoCs.\n>>\n>> It also serves as an interrupt controller, but interrupt signals are\n>> just delivered to the parent irqchip without any latching or OR'ing.\n>> This is implemented by using hierarchy IRQ domain.\n>>\n>> Implementation note:\n>> Unfortunately, the IRQ mapping from this controller to the parent is\n>> random. (48, 49, ..., 63, 154, 155, ...)\n>> If \"interrupts\" property is used, IRQ resources may be statically\n>> allocated when platform devices are populated from DT. This can be\n>> a problem for the hierarchy IRQ domain because IRQ allocation must\n>> happen from the outer-most domain up to the root domain in order to\n>> build up the stacked IRQ. (https://lkml.org/lkml/2017/7/6/758)\n>> Solutions to work around it could be to hard-code parent hwirqs or\n>> to invent a driver-specific DT property.\n>>\n>> Here, the new API irq_domain_push_irq() was merged by v4.14-rc1.\n>> It allows to add irq_data to the existing hierarchy. It will help\n>> to make this driver work whether the parent has already initialized\n>> the hierarchy or not.\n>>\n>> Signed-off-by: Masahiro Yamada \n>> ---\n>>\n>> Changes in v4:\n>> - Add COMPILE_TEST and select IRQ_DOMAIN_HIERARCHY\n>> - Reimplement irqchip part by using irq_domain_push_irq()\n> \n> Awesome improvement. There was a build error and I also\n> would like David Daney to have a look at this so we know we\n> use things the right way,\n\nIt looks correct to me.\n\nI haven't verified it, but I think the OF device-tree probing code for \nthe platform devices will automatically xlat-and-map all those irqs, so \nthat the irq_domain_push_irq() is required to get the domain hierarchy \nproperly configured. It would be similar to the PCI case where we \nconfigure all the MSI-X and then do the irq_domain_push_irq() in the \nCavium ThunderX driver.\n\nIf interrupt handling has been verified to work with this driver, I \nwould say that we are probably using things \"the right way\".\n\nDavid.\n\n\n\n> but overall I am happy after this\n> so I hope I will be able to apply next version.\n> \n> Yours,\n> Linus Walleij\n> \n\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=CAVIUMNETWORKS.onmicrosoft.com\n\theader.i=@CAVIUMNETWORKS.onmicrosoft.com header.b=\"ggHxa2Cr\"; \n\tdkim-atps=neutral","spf=none (sender IP is )\n\tsmtp.mailfrom=David.Daney@cavium.com; "],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xs8H94mrqz9s82\n\tfor ;\n\tWed, 13 Sep 2017 01:44:21 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751757AbdILPoS (ORCPT\n\t);\n\tTue, 12 Sep 2017 11:44:18 -0400","from mail-by2nam03on0068.outbound.protection.outlook.com\n\t([104.47.42.68]:14560\n\t\"EHLO NAM03-BY2-obe.outbound.protection.outlook.com\"\n\trhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP\n\tid S1751652AbdILPoQ (ORCPT );\n\tTue, 12 Sep 2017 11:44:16 -0400","from ddl.caveonetworks.com (50.233.148.156) by\n\tDM5PR07MB3500.namprd07.prod.outlook.com (10.164.153.31) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id\n\t15.20.35.12; Tue, 12 Sep 2017 15:44:13 +0000"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version;\n\tbh=xbXuGrY4mGOQxBp1flZ1U+Lm336RdN2zGUpozAgi1Zk=;\n\tb=ggHxa2CrnjPDXAgFy8AtoPgeou6U44ZYRwTbwB77lmbrYIq6fD8po6mxT9kVtmJkfstyxRutSZXPGhw+I/ylN2HJUEIpiHxNc5Oz4r+fP47hIpPnw3m+7jmB7JFCtlV0ScxBkrsFeqlpzrTc4pkBqLWDdzh1xSVCY8AHNfa6nnI=","Subject":"Re: [PATCH v4 6/6] gpio: uniphier: add UniPhier GPIO controller\n\tdriver","To":"Linus Walleij ,\n\tMasahiro Yamada ,\n\tDavid Daney ","Cc":"Marc Zyngier , Thomas Gleixner ,\n\t\"linux-gpio@vger.kernel.org\" ,\n\tRob Herring ,\n\tJassi Brar , \n\t\"devicetree@vger.kernel.org\" ,\n\tJason Cooper ,\n\tMasami Hiramatsu ,\n\t\"linux-kernel@vger.kernel.org\" ,\n\tMark Rutland ,\n\t\"linux-arm-kernel@lists.infradead.org\" \n\t","References":"<1504784522-26841-1-git-send-email-yamada.masahiro@socionext.com>\n\t<1504784522-26841-7-git-send-email-yamada.masahiro@socionext.com>\n\t","From":"David Daney ","Message-ID":"<7e46f2a3-114f-0c34-d3c5-49e6422b9200@caviumnetworks.com>","Date":"Tue, 12 Sep 2017 08:44:09 -0700","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"","Content-Type":"text/plain; charset=utf-8; format=flowed","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","X-Originating-IP":"[50.233.148.156]","X-ClientProxiedBy":"CO2PR07CA0063.namprd07.prod.outlook.com (10.174.192.31) To\n\tDM5PR07MB3500.namprd07.prod.outlook.com (10.164.153.31)","X-MS-PublicTrafficType":"Email","X-MS-Office365-Filtering-Correlation-Id":"fb0c4a69-3f34-4575-d016-08d4f9f51ef6","X-Microsoft-Antispam":"UriScan:; BCL:0; PCL:0;\n\tRULEID:(300000500095)(300135000095)(300000501095)(300135300095)(300000502095)(300135100095)(22001)(2017030254152)(300000503095)(300135400095)(2017052603199)(201703131423075)(201703031133081)(201702281549075)(300000504095)(300135200095)(300000505095)(300135600095)(300000506095)(300135500095);\n\tSRVR:DM5PR07MB3500; ","X-Microsoft-Exchange-Diagnostics":["1; DM5PR07MB3500;\n\t3:1oDUkso9rdNJ+J5fKeZXKUoD/cp9EeQAtCrkAyWDMDbiD01icBql3CtdJ0/oTjPSmm64o0uDJhpyw9x3N+TuWxhELIgBB0ZWKlZAj6BJJAWC8/yziPCEVyxUxdkrWnp44toxc5GnlIwIT6iEK3TpL+n5rVNDdUIbHftQsXlesQQxBxqQEXpdy75baxmLp4USTk56zwqZmXmW+scvGUpszK5CJUKZDHpA+6fjkwHHkOHflGzYmOkAdoTHbqvs1zBg;\n\t25:JRE9+rEm6OpW5tgARH/CsBoL7t/nldo3TiREgopOxTWqEy6z9M6BrtbZJ2JEgdQM00shQz968lfIulRXqOQzbMLA3hkgwZBk9qA1nyfEIqzPacwyAuq7CyVCJOeMMBGlficzD+gjFTl6ZdCMzPFs0Ye8OBzyedSJCF5hFVDgG2GV2tKUtJFWzjn3SLVP+C7gCN/GdHIFWd3uBHZuRAdCkFw5BIusVPzG/BKCM8p3h2on+JZeh30uBFMQ1DNbc3vggk2lo/W0vr6tMVdYey4lRH5lnSL1HDRo4fZWILAsOaqbO80ol6Z3PIrc5a+6sXOs4eywaMT4GRJm8YCEvEy0qw==;\n\t31:BOHuDRrbO1UqZy0M5acF/v+6Ok9nEJHXClea7zepuIORUXungL9AsAlx5OGtubZf1zei83gIypxB9v990AW7FWQmxO3+4DQCUTkNTMpuWaqgx54+HVtb04dwTucCjd1f0dHRrkPatqmbb2zvFrfMn5VLX8TudWYl5ZjH1SK5QkI7646jsm2mGiiQNXn30hhfQMg6C2aFHAxeipf6ks3LQ312XifWnzHI5txIc7yHH/g=","1; DM5PR07MB3500;\n\t20:2jUoBzOCHAxyDc232KPcEtSnSbw0W6ONPMgdt5rPczJApz4E1s+/RvM4knI1LDPx1T1GjcG2P7m2XbDq7uvdFM9HxAX+az/1+SpA1PGZpDX2bRMr3PuPaQaj7czCy64ePyEWSXNniI5AuLs7L7c3+UFDxq1w78SYjNEGJXMFcjpPabFoIwFfWqLFPtcWwI6YiuKSfXzXnodYBqRQnl9/7Qyl4VG4r9+vNxEwztLwr8TEGcJ7Cv1hW9guf7wLZyTZdIDGo6mI2pZfdtwsTn5p4P/8vBhaWBAjgU8ERfTP6lWB6Vnku545gxEpSD9c1c5AGjmj7sdwkFjs0cUOQtAz8FKIxLXe8n05Q0BtLCVe5oc6ZS0ifhSohJ1aQ0WraQFAtyDB8lP1qJB8+q8oYllhrIMPDN8fq1Fozk+koclJExi24cZh24cJCRCT+1rVj5kWLpYj9AD8QhjAEqkt1+E9nBBeDtXei7iweKGwWeowUmzqEvoLqaQLDQ04TcoSMXNMtYzWjw16X4f0JctD5Ve0nhTcv/AMdXQpbFRPDMj8tuRgF1zC9JGrYAgOP2NwFXkWhrMbCHFyInhpbHS0TdmZg8RT8kOizzBX2IV1wwhSwV4=;\n\t4:b4EPdxPxcWTKM0rjNztawyh8IULhjXlB6iHFNMGlPSTd0O94LOd5Nc9uY9LLEtXYxHF0CAzNwSIAruQ+huROuewNke4bNe0Vf9JZKnfWbVyuoM5JIVc9wQpKZF1aZfUpgXj3qwJwOwwMSluZwZnx/zF7TtcEvVA9Ctys9iO0i/r9gV98NwlClVzfEGJ4lXVGoZ07K1B4A+AeVj70poaG/ezsANmPaJymP8wf+ctUzX4CE+gLYdXMYsDXj80R0K5b","=?utf-8?q?1=3BDM5PR07MB3500=3B23=3A/nox?=\n\t=?utf-8?q?wScnXeb8nx5QZ+PUkhxZNBheYLfVqBYB4WUlA34ccDo26JOLjAnaxQjz?=\n\t=?utf-8?q?FxM4kpLnE3cHDi0bVYS7I2MmG4+kOf2Av3rg/vyD72l5bWwfJ5vA82Ym?=\n\t=?utf-8?q?Qym4EHyYaNlJym646WWSIhf6le+A4MTDdLC+04gLQbbQ9996eeHkI7zL?=\n\t=?utf-8?q?xuG6dRJNPdcYeWvDZ1iPaWeCnJaNbsz6Igl/4NlRnxuO8nYdBnXqd0M/?=\n\t=?utf-8?q?VxH3HU3d2UL6v6H8zEWcAFPBKDS34/18MzQ9YI6WBG7E4iQoOFqoCGJZ?=\n\t=?utf-8?q?obcPsbLfP0bQYmG1u3uDxsbUR1OHSDRde+RwmqyzJx3k/ehjX2ECrQ5g?=\n\t=?utf-8?q?2JAvsnkGs5dn1eQ7FS3poJUgRxnUbcHZtszTSpDLT3etvdVOcgM/iDnz?=\n\t=?utf-8?q?ARrH0cCtQ1l8hSS4n6rOuXHY9CbPNIUGe+2/zFXXMKVANotPTLLrFQFA?=\n\t=?utf-8?q?Ftb6+YZyqoGomDXKVcQxaU3TtfqJpZcYX2DDjLuFJMaX35mWqcz2It93?=\n\t=?utf-8?q?kpE8lOuxID9SZe5nQxSab3bvwph0JY9UgqIsu12So4g95+Yy7IxlaIC/?=\n\t=?utf-8?q?X6X5DrDEwkcgZ4nzS/zIrUBhaV/hClJqcPM246HG+YEK9k6NaQz0d1LY?=\n\t=?utf-8?q?p9zVZrO/5MgLyn+a3f8xwzBhBee/ZsS8WqzEKs4sUSCmM7WGVz7CBR0E?=\n\t=?utf-8?q?nnTV90EDkrBiSgIyiPSMGEGRoT1uhKsCVbtbNtyQzDAdHc5ZRIxTGMg5?=\n\t=?utf-8?q?28hxPUsBLUygXPwfBKK3rxiZzWbuWnFZcrKi9qSgy913M5XI7Qoe0YSK?=\n\t=?utf-8?q?bnDGw32eNtenilDWz5sSdoSsnQk1VuSI84azon7hYcILa+3UvcXltNOy?=\n\t=?utf-8?q?Y4WXk+Goh4l8XTEMdWVFEV7bq+tuN3yTobjrC91zJ1uEQhJOsxeEnSVI?=\n\t=?utf-8?q?jcVmnwAXLdNtBvu0PNAXlEGmVxr6vD8SmPRSyyUVb6p1Hq1CVVndb79T?=\n\t=?utf-8?q?o1rBUbIx23vPZ1A/JebM5hNXF+eBcaGiY3UUmY/2pFpxrXnCFsFP9QXG?=\n\t=?utf-8?q?ZeqaPmJmaQYmuR7fR+Hfd14BAZfMvQPkzv16hjrg1nkENW8uVUlHyeaX?=\n\t=?utf-8?q?t0RF7b0CtZs9M0toijcwgn+a0fGvdlLQUju4LDwO/pJNFGp4iu8mPS6M?=\n\t=?utf-8?q?uteQX1SbTgf030d5b6tk1N7RSZcMO6o1K7bf1wKh2ivSr9nuS46sZeLd?=\n\t=?utf-8?q?1zK/McdBt9bCMVP4udnWf0L+uDsuy9/ywzYoU6aF4kvDBJeD+IMYRMsb?=\n\t=?utf-8?q?vf0Ih9hYHxZ9vcNFU4nDQXKy9HJw1n7q2byG4eUNqBMSRDWfTDM00zm5?=\n\t=?utf-8?q?e4XOYoDBfo8F+Dbz1FWj/FGa39212TacinbLM1G0OElsHlpcfwrqN3Pn?=\n\t=?utf-8?q?J/Q3jhATUCp25cgLkiiD/VZD29w8QKe+5bI1TNfJE1SsJgd626czzQh3?=\n\t=?utf-8?q?YyLA?=","1; DM5PR07MB3500;\n\t6:2ZQjYn8MRStLXXLhvjagnDasjokkTQc337GdQwEUypowZ5G1jy7w1w/H/BRZm4GAciySDtit9ewr2PoX+8kkG2cVke7q0JGJKBTOVFG7GUlIIoHYDuSk59xy+F+Or/Q5xSMHPmT2+S/Rn0GvjnbD9wL3Emh5rwOabopijRNCPpufEW1ULmTTncjlxOXQHWOlMjY2e9MhNszmF7KfMAWwNdaAoqUX0TIsFLTfrpHJGmJfYV2O0ptIW4UEUXH14zph4UCMW7cqgZForTZLNq1m9gRvf69b398DpQlMU/ZQfRmfyrRaMvsq8k6ZAQ2Ce8mnPBq9JT6hnR1w/QtXWpslpA==;\n\t5:nJTLyb9P70icVDdDl3val0qmDjwuuXYOnxBkwa+YJS5kQ4Gt8YsCp7FNiP6zsBsA2KobYZa9C3kua60CGfzm7vgpdUklUkgJz1hETQpSSb9EClZVaC0auPKhoCO+M4EQ/ZwRHH9XOB1b2DihH76fMQ==;\n\t24:4++7PDHksRdVW9b1VbnnRpRE+qaDdA0pC9Tdjg6kK3ySL3+Y2Co78BzzFslH78y7bYbHVuqsbExiRG3rWICR/1+ZPoC43qBoWO1UrrXJ77g=;\n\t7:6KJ0G1PTrM1YLVHEQAQkS+wqZ3q1yCWeH6kKWwZLINVor4MpOY9iZWWxqW6C60mV/uDL3Y8sfvdrPtmbBGFt+olfcJA8H6gqqq1I/K33CIZIFQl8MEVN0AhU/S2RkQbXuvx9A26FU1iLNNb6UY1+qBqhGhBDS2rsdwqN08/UGcGiI0E1AwdLUuDNrOTm70pB3P4EN2Us6DrNuKsb6MQspVUoqsaC1QPv4RJohPDStR8="],"X-MS-TrafficTypeDiagnostic":"DM5PR07MB3500:","X-Exchange-Antispam-Report-Test":"UriScan:;","X-Microsoft-Antispam-PRVS":"","X-Exchange-Antispam-Report-CFA-Test":"BCL:0; PCL:0;\n\tRULEID:(100000700101)(100105000095)(100000701101)(100105300095)(100000702101)(100105100095)(6040450)(2401047)(5005006)(8121501046)(3002001)(100000703101)(100105400095)(10201501046)(93006095)(6041248)(20161123562025)(20161123555025)(20161123564025)(20161123558100)(201703131423075)(201702281528075)(201703061421075)(201703061406153)(20161123560025)(6072148)(201708071742011)(100000704101)(100105200095)(100000705101)(100105500095);\n\tSRVR:DM5PR07MB3500; BCL:0; PCL:0;\n\tRULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(100000804101)(100110200095)(100000805101)(100110500095);\n\tSRVR:DM5PR07MB3500; ","X-Forefront-PRVS":"042857DBB5","X-Forefront-Antispam-Report":"SFV:NSPM;\n\tSFS:(10009020)(6009001)(199003)(377454003)(24454002)(189002)(31686004)(81156014)(8936002)(6512007)(2906002)(7416002)(6246003)(42882006)(2950100002)(65826007)(6306002)(54906002)(83506001)(72206003)(230700001)(189998001)(5660300001)(478600001)(97736004)(53546010)(4326008)(316002)(25786009)(53936002)(69596002)(42186005)(81166006)(6666003)(8676002)(6486002)(305945005)(65806001)(106356001)(33646002)(105586002)(4001350100001)(7736002)(47776003)(66066001)(6506006)(65956001)(68736007)(23676002)(3846002)(101416001)(6116002)(31696002)(76176999)(54356999)(229853002)(50466002)(53416004)(50986999)(36756003)(64126003);\n\tDIR:OUT; SFP:1101; SCL:1; SRVR:DM5PR07MB3500; H:ddl.caveonetworks.com;\n\tFPR:; \n\tSPF:None; PTR:InfoNoRecords; A:1; MX:1; LANG:en; ","Received-SPF":"None (protection.outlook.com: cavium.com does not designate\n\tpermitted sender hosts)","SpamDiagnosticOutput":"1:99","SpamDiagnosticMetadata":"NSPM","X-OriginatorOrg":"caviumnetworks.com","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"12 Sep 2017 15:44:13.1638\n\t(UTC)","X-MS-Exchange-CrossTenant-FromEntityHeader":"Hosted","X-MS-Exchange-CrossTenant-Id":"711e4ccf-2e9b-4bcf-a551-4094005b6194","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"DM5PR07MB3500","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1767674,"web_url":"http://patchwork.ozlabs.org/comment/1767674/","msgid":"","list_archive_url":null,"date":"2017-09-13T08:31:26","subject":"Re: [PATCH v4 6/6] gpio: uniphier: add UniPhier GPIO controller\n\tdriver","submitter":{"id":65882,"url":"http://patchwork.ozlabs.org/api/people/65882/","name":"Masahiro Yamada","email":"yamada.masahiro@socionext.com"},"content":"Hi.\n\n2017-09-13 0:44 GMT+09:00 David Daney :\n> On 09/12/2017 07:03 AM, Linus Walleij wrote:\n>>\n>> On Thu, Sep 7, 2017 at 1:42 PM, Masahiro Yamada\n>> wrote:\n>>\n>>> This GPIO controller device is used on UniPhier SoCs.\n>>>\n>>> It also serves as an interrupt controller, but interrupt signals are\n>>> just delivered to the parent irqchip without any latching or OR'ing.\n>>> This is implemented by using hierarchy IRQ domain.\n>>>\n>>> Implementation note:\n>>> Unfortunately, the IRQ mapping from this controller to the parent is\n>>> random. (48, 49, ..., 63, 154, 155, ...)\n>>> If \"interrupts\" property is used, IRQ resources may be statically\n>>> allocated when platform devices are populated from DT. This can be\n>>> a problem for the hierarchy IRQ domain because IRQ allocation must\n>>> happen from the outer-most domain up to the root domain in order to\n>>> build up the stacked IRQ. (https://lkml.org/lkml/2017/7/6/758)\n>>> Solutions to work around it could be to hard-code parent hwirqs or\n>>> to invent a driver-specific DT property.\n>>>\n>>> Here, the new API irq_domain_push_irq() was merged by v4.14-rc1.\n>>> It allows to add irq_data to the existing hierarchy. It will help\n>>> to make this driver work whether the parent has already initialized\n>>> the hierarchy or not.\n>>>\n>>> Signed-off-by: Masahiro Yamada \n>>> ---\n>>>\n>>> Changes in v4:\n>>> - Add COMPILE_TEST and select IRQ_DOMAIN_HIERARCHY\n>>> - Reimplement irqchip part by using irq_domain_push_irq()\n>>\n>>\n>> Awesome improvement. There was a build error and I also\n>> would like David Daney to have a look at this so we know we\n>> use things the right way,\n>\n>\n> It looks correct to me.\n>\n> I haven't verified it, but I think the OF device-tree probing code for the\n> platform devices will automatically xlat-and-map all those irqs, so that the\n> irq_domain_push_irq() is required to get the domain hierarchy properly\n> configured. It would be similar to the PCI case where we configure all the\n> MSI-X and then do the irq_domain_push_irq() in the Cavium ThunderX driver.\n>\n> If interrupt handling has been verified to work with this driver, I would\n> say that we are probably using things \"the right way\".\n>\n> David.\n>\n\nV4 depends on 5 patches that got negative feedback in irqdomain subsystem.\nOne more problem for this approach is to virtual IRQs are statically\nallocated during the driver probe.\nThis looks a step backward to me.\nRecently, gpio_irqchip migrated to on-the-fly allocation in case some\ncontrollers may have lots of\nGPIO lines.\n\n\nFinally, I came up with another (I think, better) solution.\nI think v5 is less controversial,\nand works very well in on-the-fly manner.\n\nI am sending it shortly...","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=nifty.com header.i=@nifty.com\n\theader.b=\"PoejE+eb\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xsZfK2cTNz9sNr\n\tfor ;\n\tWed, 13 Sep 2017 18:32:25 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751737AbdIMIcX (ORCPT\n\t);\n\tWed, 13 Sep 2017 04:32:23 -0400","from conssluserg-01.nifty.com ([210.131.2.80]:42818 \"EHLO\n\tconssluserg-01.nifty.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751121AbdIMIcU (ORCPT\n\t); Wed, 13 Sep 2017 04:32:20 -0400","from mail-yw0-f182.google.com (mail-yw0-f182.google.com\n\t[209.85.161.182]) (authenticated)\n\tby conssluserg-01.nifty.com with ESMTP id v8D8W764012572;\n\tWed, 13 Sep 2017 17:32:07 +0900","by mail-yw0-f182.google.com with SMTP id s62so33358635ywg.0;\n\tWed, 13 Sep 2017 01:32:07 -0700 (PDT)","by 10.37.164.225 with HTTP; Wed, 13 Sep 2017 01:31:26 -0700 (PDT)"],"DKIM-Filter":"OpenDKIM Filter v2.10.3 conssluserg-01.nifty.com v8D8W764012572","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com;\n\ts=dec2015msa; t=1505291528;\n\tbh=6jso4SJE47ANfjin7Zg4Us+F2DlIXHfRfZ0EMmEjCjY=;\n\th=In-Reply-To:References:From:Date:Subject:To:Cc:From;\n\tb=PoejE+eb3pBoAWJx2O7jPBD6ip/wflVr1ljKkPPP+TW/ZGsx8WZhN074Qu4W687pe\n\tgkOYomqCylHCCQbXLBBpbUumTUQtm5yGgPliMaOB09TPd3AaZzaRNyJRKPBoDTe3Xm\n\tD88YApIvCIzUrmVemsRwccMzFi6kR474Rmxiu6ODX3VG68j83ma5BGMEnFqmK32Ogl\n\t08qpf1GcZThIaMbvRQRBvDradAjs1n154+fZ/n8Cu95/LbCiYy9oW9zU6MvPDCh/6j\n\t258/+HCU++Pp4VCme/dlbN6Trl9cQwgaHebwrFgvYjO0XcHyL+Z6q0Gr/ZecsVmPqu\n\t0U1ZBqF52KZLw==","X-Nifty-SrcIP":"[209.85.161.182]","X-Gm-Message-State":"AHPjjUhno9XthYbzWxFXOJEAeAfF8c3BAdd0szg3R1BrtxTesHj0QazX\n\tItnvREkfaPIjsfIpwKW3KgczSdpRvSEGPaUyhvk=","X-Google-Smtp-Source":"AOwi7QA06Z11d52UtW6GwTyVF4fipIwETMuTMFzMK+5W6d1A254cTsWWSvGmWSFHzbJWXgycLVN/Qu2/wXlr+YpMyR8=","X-Received":"by 10.37.234.68 with SMTP id o4mr14277233ybe.119.1505291526446; \n\tWed, 13 Sep 2017 01:32:06 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"<7e46f2a3-114f-0c34-d3c5-49e6422b9200@caviumnetworks.com>","References":"<1504784522-26841-1-git-send-email-yamada.masahiro@socionext.com>\n\t<1504784522-26841-7-git-send-email-yamada.masahiro@socionext.com>\n\t\n\t<7e46f2a3-114f-0c34-d3c5-49e6422b9200@caviumnetworks.com>","From":"Masahiro Yamada ","Date":"Wed, 13 Sep 2017 17:31:26 +0900","X-Gmail-Original-Message-ID":"","Message-ID":"","Subject":"Re: [PATCH v4 6/6] gpio: uniphier: add UniPhier GPIO controller\n\tdriver","To":"David Daney ","Cc":"Linus Walleij ,\n\tDavid Daney ,\n\tMarc Zyngier , \n\tThomas Gleixner ,\n\t\"linux-gpio@vger.kernel.org\" ,\n\tRob Herring ,\n\tJassi Brar , \n\t\"devicetree@vger.kernel.org\" ,\n\tJason Cooper ,\n\tMasami Hiramatsu ,\n\t\"linux-kernel@vger.kernel.org\" ,\n\tMark Rutland ,\n\t\"linux-arm-kernel@lists.infradead.org\" \n\t","Content-Type":"text/plain; charset=\"UTF-8\"","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}}]