[{"id":1764595,"web_url":"http://patchwork.ozlabs.org/comment/1764595/","msgid":"<6A2C052D-0C27-4566-B5A3-6DEC332633C4@theobroma-systems.com>","list_archive_url":null,"date":"2017-09-07T08:53:30","subject":"Re: [U-Boot] [PATCH] rockchip: firefly-rk3399: enable SPL_SYSRESET\n\tconfig","submitter":{"id":53488,"url":"http://patchwork.ozlabs.org/api/people/53488/","name":"Philipp Tomsich","email":"philipp.tomsich@theobroma-systems.com"},"content":"Kever,\n\nI’ll try to get this in for the current release (i.e get it applied and send out a pull\nlater this week), as it’s a defconfig-only bugfix for a regression introduced in the\ncurrent release.\n\nRegards,\nPhilipp.\n\n> On 7 Sep 2017, at 05:30, Kever Yang wrote:\n> \n> After the patch below, we need to add SPL_SYSRESET for do_reset()\n> in SPL:\n> 87c16d4 drivers: spl: consistently use the $(SPL_TPL_) macro\n> \n> Signed-off-by: Kever Yang \n\nReviewed-by: Philipp Tomsich \n\n> ---\n> \n> configs/firefly-rk3399_defconfig | 3 ++-\n> 1 file changed, 2 insertions(+), 1 deletion(-)\n> \n> diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig\n> index d8ea4cb..eead166 100644\n> --- a/configs/firefly-rk3399_defconfig\n> +++ b/configs/firefly-rk3399_defconfig\n> @@ -9,7 +9,6 @@ CONFIG_DEFAULT_DEVICE_TREE=\"rk3399-firefly\"\n> CONFIG_DEBUG_UART=y\n> CONFIG_FIT=y\n> CONFIG_SPL_LOAD_FIT=y\n> -CONFIG_ENV_IS_IN_MMC=y\n> CONFIG_SPL_FIT_GENERATOR=\"board/rockchip/evb_rk3399/mk_fit_atf.sh\"\n> # CONFIG_DISPLAY_CPUINFO is not set\n> CONFIG_SPL_STACK_R=y\n> @@ -36,6 +35,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y\n> CONFIG_CMD_TIME=y\n> CONFIG_SPL_OF_CONTROL=y\n> CONFIG_OF_SPL_REMOVE_PROPS=\"pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents\"\n> +CONFIG_ENV_IS_IN_MMC=y\n> CONFIG_REGMAP=y\n> CONFIG_SPL_REGMAP=y\n> CONFIG_SYSCON=y\n> @@ -70,6 +70,7 @@ CONFIG_DEBUG_UART_CLOCK=24000000\n> CONFIG_DEBUG_UART_SHIFT=2\n> CONFIG_SYS_NS16550=y\n> CONFIG_SYSRESET=y\n> +CONFIG_SPL_SYSRESET=y\n> CONFIG_USB=y\n> CONFIG_USB_XHCI_HCD=y\n> CONFIG_USB_XHCI_DWC3=y\n> -- \n> 1.9.1\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xnvPd2Jpjz9s8J\n\tfor ;\n\tThu, 7 Sep 2017 18:53:41 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid D2636C21E2C; Thu, 7 Sep 2017 08:53:39 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 5086DC21C97;\n\tThu, 7 Sep 2017 08:53:38 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid B4CFBC21C97; Thu, 7 Sep 2017 08:53:36 +0000 (UTC)","from mail.theobroma-systems.com (vegas.theobroma-systems.com\n\t[144.76.126.164])\n\tby lists.denx.de (Postfix) with ESMTPS id 6F909C21C72\n\tfor ; Thu, 7 Sep 2017 08:53:36 +0000 (UTC)","from 89-104-28-141.customer.bnet.at ([89.104.28.141]:51898\n\thelo=[192.168.2.129]) by mail.theobroma-systems.com with esmtpsa\n\t(TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80)\n\t(envelope-from )\n\tid 1dpsZ1-00023X-Gx; Thu, 07 Sep 2017 10:53:31 +0200"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"*","X-Spam-Status":"No, score=1.0 required=5.0 tests=HK_NAME_DR autolearn=no\n\tautolearn_force=no version=3.4.0","Mime-Version":"1.0 (Mac OS X Mail 10.3 \\(3273\\))","From":"\"Dr. Philipp Tomsich\" ","In-Reply-To":"<1504755006-6521-1-git-send-email-kever.yang@rock-chips.com>","Date":"Thu, 7 Sep 2017 10:53:30 +0200","Message-Id":"<6A2C052D-0C27-4566-B5A3-6DEC332633C4@theobroma-systems.com>","References":"<1504755006-6521-1-git-send-email-kever.yang@rock-chips.com>","To":"Kever Yang ","X-Mailer":"Apple Mail (2.3273)","Cc":"U-Boot Mailing List ","Subject":"Re: [U-Boot] [PATCH] rockchip: firefly-rk3399: enable SPL_SYSRESET\n\tconfig","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1765050,"web_url":"http://patchwork.ozlabs.org/comment/1765050/","msgid":"","list_archive_url":null,"date":"2017-09-08T03:02:39","subject":"Re: [U-Boot] [PATCH] rockchip: firefly-rk3399: enable SPL_SYSRESET\n\tconfig","submitter":{"id":64532,"url":"http://patchwork.ozlabs.org/api/people/64532/","name":"Kever Yang","email":"kever.yang@rock-chips.com"},"content":"Hi Philipp,\n\n I think this patch is not enough, pls drop this.\n\nI have send another patch to add SPL_SYSRESET for all Rockchip SoCs,\n\nbecause all of them need this, eg. rk3288 have many boards, all have \nthis issue.\n\n\nThanks,\n- Kever\nOn 09/07/2017 04:53 PM, Dr. Philipp Tomsich wrote:\n> Kever,\n>\n> I’ll try to get this in for the current release (i.e get it applied and send out a pull\n> later this week), as it’s a defconfig-only bugfix for a regression introduced in the\n> current release.\n>\n> Regards,\n> Philipp.\n>\n>> On 7 Sep 2017, at 05:30, Kever Yang wrote:\n>>\n>> After the patch below, we need to add SPL_SYSRESET for do_reset()\n>> in SPL:\n>> 87c16d4 drivers: spl: consistently use the $(SPL_TPL_) macro\n>>\n>> Signed-off-by: Kever Yang \n> Reviewed-by: Philipp Tomsich \n>\n>> ---\n>>\n>> configs/firefly-rk3399_defconfig | 3 ++-\n>> 1 file changed, 2 insertions(+), 1 deletion(-)\n>>\n>> diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig\n>> index d8ea4cb..eead166 100644\n>> --- a/configs/firefly-rk3399_defconfig\n>> +++ b/configs/firefly-rk3399_defconfig\n>> @@ -9,7 +9,6 @@ CONFIG_DEFAULT_DEVICE_TREE=\"rk3399-firefly\"\n>> CONFIG_DEBUG_UART=y\n>> CONFIG_FIT=y\n>> CONFIG_SPL_LOAD_FIT=y\n>> -CONFIG_ENV_IS_IN_MMC=y\n>> CONFIG_SPL_FIT_GENERATOR=\"board/rockchip/evb_rk3399/mk_fit_atf.sh\"\n>> # CONFIG_DISPLAY_CPUINFO is not set\n>> CONFIG_SPL_STACK_R=y\n>> @@ -36,6 +35,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y\n>> CONFIG_CMD_TIME=y\n>> CONFIG_SPL_OF_CONTROL=y\n>> CONFIG_OF_SPL_REMOVE_PROPS=\"pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents\"\n>> +CONFIG_ENV_IS_IN_MMC=y\n>> CONFIG_REGMAP=y\n>> CONFIG_SPL_REGMAP=y\n>> CONFIG_SYSCON=y\n>> @@ -70,6 +70,7 @@ CONFIG_DEBUG_UART_CLOCK=24000000\n>> CONFIG_DEBUG_UART_SHIFT=2\n>> CONFIG_SYS_NS16550=y\n>> CONFIG_SYSRESET=y\n>> +CONFIG_SPL_SYSRESET=y\n>> CONFIG_USB=y\n>> CONFIG_USB_XHCI_HCD=y\n>> CONFIG_USB_XHCI_DWC3=y\n>> -- \n>> 1.9.1\n>>\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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Linux x86_64; rv:45.0) Gecko/20100101\n\tThunderbird/45.8.0","MIME-Version":"1.0","In-Reply-To":"<6A2C052D-0C27-4566-B5A3-6DEC332633C4@theobroma-systems.com>","Cc":"U-Boot Mailing List ","Subject":"Re: [U-Boot] [PATCH] rockchip: firefly-rk3399: enable SPL_SYSRESET\n\tconfig","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Transfer-Encoding":"base64","Content-Type":"text/plain; charset=\"utf-8\"; Format=\"flowed\"","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}}]