[{"id":1768057,"web_url":"http://patchwork.ozlabs.org/comment/1768057/","msgid":"<20170913174032.u33zzo64ipk22vgp@rob-hp-laptop>","list_archive_url":null,"date":"2017-09-13T17:40:32","subject":"Re: [PATCH V3] clk: qcom: Add spmi_pmic clock divider support","submitter":{"id":62529,"url":"http://patchwork.ozlabs.org/api/people/62529/","name":"Rob Herring","email":"robh@kernel.org"},"content":"On Wed, Sep 06, 2017 at 05:30:07PM +0530, Tirupathi Reddy wrote:\n> Clkdiv module provides a clock output on the PMIC with CXO as\n> the source. This clock can be routed through PMIC GPIOs. Add\n> a device driver to configure this clkdiv module.\n> \n> Signed-off-by: Tirupathi Reddy <tirupath@codeaurora.org>\n> ---\n>  .../bindings/clock/clk-spmi-pmic-div.txt           |  51 +++\n>  drivers/clk/qcom/Kconfig                           |   9 +\n>  drivers/clk/qcom/Makefile                          |   1 +\n>  drivers/clk/qcom/clk-spmi-pmic-div.c               | 342 +++++++++++++++++++++\n>  4 files changed, 403 insertions(+)\n>  create mode 100644 Documentation/devicetree/bindings/clock/clk-spmi-pmic-div.txt\n>  create mode 100644 drivers/clk/qcom/clk-spmi-pmic-div.c\n> \n> diff --git a/Documentation/devicetree/bindings/clock/clk-spmi-pmic-div.txt b/Documentation/devicetree/bindings/clock/clk-spmi-pmic-div.txt\n> new file mode 100644\n> index 0000000..8b84b32\n> --- /dev/null\n> +++ b/Documentation/devicetree/bindings/clock/clk-spmi-pmic-div.txt\n> @@ -0,0 +1,51 @@\n> +Qualcomm Technologies, Inc. SPMI PMIC clock divider (clkdiv)\n> +\n> +clkdiv configures the clock frequency of a set of outputs on the PMIC.\n> +These clocks are typically wired through alternate functions on\n> +gpio pins.\n> +\n> +=======================\n> +Properties\n> +=======================\n> +\n> +- compatible\n> +\tUsage:      required\n> +\tValue type: <string>\n> +\tDefinition: must be one of:\n> +\t\t    \"qcom,spmi-clkdiv\"\n\nIf this is not a fallback, drop it.\n\n> +\t\t    \"qcom,pm8998-clkdiv\"\n> +\n> +- reg\n> +\tUsage:      required\n> +\tValue type: <prop-encoded-array>\n> +\tDefinition: Addresses and sizes for the memory of this CLKDIV\n> +\t\t    peripheral.\n> +\n> +- clocks:\n> +\tUsage: required\n> +\tValue type: <prop-encoded-array>\n> +\tDefinition: reference to the xo clock.\n> +\n> +- clock-names:\n> +\tUsage: required\n> +\tValue type: <stringlist>\n> +\tDefinition: must be \"xo\".\n\nMissing #clock-cells\n\n> +\n> +=======\n> +Example\n> +=======\n> +\n> +pm8998_clk_divs: qcom,clkdiv@5b00 {\n\nclock@5b00\n\n> +\tcompatible = \"qcom,pm8998-clkdiv\";\n> +\treg = <0x5b00>;\n> +\t#clock-cells = <1>;\n> +\tclocks = <&xo_board>;\n> +\tclock-names = \"xo\";\n> +\n> +\tassigned-clocks = <&pm8998_clk_divs 1>,\n> +\t\t\t  <&pm8998_clk_divs 2>,\n> +\t\t\t  <&pm8998_clk_divs 3>;\n> +\tassigned-clock-rates = <9600000>,\n> +\t\t\t       <9600000>,\n> +\t\t\t       <9600000>;\n> +};\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at  http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"<devicetree-owner@vger.kernel.org>","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=<UNKNOWN>)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xspq9527Wz9sNV\n\tfor <incoming-dt@patchwork.ozlabs.org>;\n\tThu, 14 Sep 2017 03:40:53 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751440AbdIMRkj (ORCPT\n\t<rfc822;incoming-dt@patchwork.ozlabs.org>);\n\tWed, 13 Sep 2017 13:40:39 -0400","from mail-io0-f194.google.com ([209.85.223.194]:36075 \"EHLO\n\tmail-io0-f194.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751365AbdIMRkf (ORCPT\n\t<rfc822; devicetree@vger.kernel.org>); Wed, 13 Sep 2017 13:40:35 -0400","by mail-io0-f194.google.com with SMTP id n69so931399ioi.3;\n\tWed, 13 Sep 2017 10:40:34 -0700 (PDT)","from localhost (216-188-254-6.dyn.grandenetworks.net.\n\t[216.188.254.6]) by smtp.gmail.com with ESMTPSA id\n\tj19sm6111287oib.9.2017.09.13.10.40.33\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tWed, 13 Sep 2017 10:40:33 -0700 (PDT)"],"X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:date:from:to:cc:subject:message-id:references\n\t:mime-version:content-disposition:in-reply-to:user-agent;\n\tbh=EocJYKMwNZvDt1xZUd3TGj+GepYf/ML786FPPyY5oBU=;\n\tb=FgRPocG4moWNUq2l63YDKmn6EuPwDexgnU3RzorDmIfCJCdJXR3k1Y03x6mJnxMed3\n\tV9tnc9C4W0s+RfrEDQsYonq77hYkCbiBbR5/QnGBaUXuh/3oglAD2U+QnnRf8SyBm/M8\n\tSTH0wAIlmOwxXWPArjPAKtdHpPo9Mz+TdnQSGAwf0VZvLo/UM3qo0/tKqCxfI3Tnj52P\n\tNqcucAiJxBUlSSvKPZIiIpMNXboE4gcUX1oyT134J3FwfF+O/uG8qaZXzjspv+xwtLhb\n\tJrlab1vN4dGpq35GgwRhFwAMp+WAEDWojlJh6gfYLyKnlKUdf8NVyWvb0jvWB1+90vOQ\n\tSq+A==","X-Gm-Message-State":"AHPjjUjqNEevzE66Cs3E+wNFJe7Al/hi8asNypvbPjrGbw6Lgh/Xz6DD\n\tDuyJ0gltL1zqmA==","X-Google-Smtp-Source":"AOwi7QBVITcthrdIvO0cx2PqEGskHXTa5pNTegiEZ/jBaUKYXOQchyzNkZu7WgDbM0zgbR3wpQGKcg==","X-Received":"by 10.202.102.194 with SMTP id m63mr6677372oik.296.1505324434321;\n\tWed, 13 Sep 2017 10:40:34 -0700 (PDT)","Date":"Wed, 13 Sep 2017 12:40:32 -0500","From":"Rob Herring <robh@kernel.org>","To":"Tirupathi Reddy <tirupath@codeaurora.org>","Cc":"sboyd@codeaurora.org, mturquette@baylibre.com,\n\tmark.rutland@arm.com, andy.gross@linaro.org,\n\tdavid.brown@linaro.org, linux-clk@vger.kernel.org,\n\tdevicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tlinux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org","Subject":"Re: [PATCH V3] clk: qcom: Add spmi_pmic clock divider support","Message-ID":"<20170913174032.u33zzo64ipk22vgp@rob-hp-laptop>","References":"<1504699207-9568-1-git-send-email-tirupath@codeaurora.org>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<1504699207-9568-1-git-send-email-tirupath@codeaurora.org>","User-Agent":"NeoMutt/20170113 (1.7.2)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"<devicetree.vger.kernel.org>","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1770093,"web_url":"http://patchwork.ozlabs.org/comment/1770093/","msgid":"<b1a48f0e-7a96-079e-0e68-3d89368316ba@codeaurora.org>","list_archive_url":null,"date":"2017-09-18T11:30:55","subject":"Re: [PATCH V3] clk: qcom: Add spmi_pmic clock divider support","submitter":{"id":71968,"url":"http://patchwork.ozlabs.org/api/people/71968/","name":"Tirupathi Reddy","email":"tirupath@codeaurora.org"},"content":"On 9/13/2017 11:10 PM, Rob Herring wrote:\n> On Wed, Sep 06, 2017 at 05:30:07PM +0530, Tirupathi Reddy wrote:\n>> Clkdiv module provides a clock output on the PMIC with CXO as\n>> the source. This clock can be routed through PMIC GPIOs. Add\n>> a device driver to configure this clkdiv module.\n>>\n>> Signed-off-by: Tirupathi Reddy <tirupath@codeaurora.org>\n>> ---\n>>   .../bindings/clock/clk-spmi-pmic-div.txt           |  51 +++\n>>   drivers/clk/qcom/Kconfig                           |   9 +\n>>   drivers/clk/qcom/Makefile                          |   1 +\n>>   drivers/clk/qcom/clk-spmi-pmic-div.c               | 342 +++++++++++++++++++++\n>>   4 files changed, 403 insertions(+)\n>>   create mode 100644 Documentation/devicetree/bindings/clock/clk-spmi-pmic-div.txt\n>>   create mode 100644 drivers/clk/qcom/clk-spmi-pmic-div.c\n>>\n>> diff --git a/Documentation/devicetree/bindings/clock/clk-spmi-pmic-div.txt b/Documentation/devicetree/bindings/clock/clk-spmi-pmic-div.txt\n>> new file mode 100644\n>> index 0000000..8b84b32\n>> --- /dev/null\n>> +++ b/Documentation/devicetree/bindings/clock/clk-spmi-pmic-div.txt\n>> @@ -0,0 +1,51 @@\n>> +Qualcomm Technologies, Inc. SPMI PMIC clock divider (clkdiv)\n>> +\n>> +clkdiv configures the clock frequency of a set of outputs on the PMIC.\n>> +These clocks are typically wired through alternate functions on\n>> +gpio pins.\n>> +\n>> +=======================\n>> +Properties\n>> +=======================\n>> +\n>> +- compatible\n>> +\tUsage:      required\n>> +\tValue type: <string>\n>> +\tDefinition: must be one of:\n>> +\t\t    \"qcom,spmi-clkdiv\"\n> If this is not a fallback, drop it.\nHere \"qcom,spmi-clkdiv\" is used as generic string for registering only \none clk and\nthe pmic specific strings are used for registering more than one clk \nfollowing\nthe given base address in \"reg\" property.\n>\n>> +\t\t    \"qcom,pm8998-clkdiv\"\n>> +\n>> +- reg\n>> +\tUsage:      required\n>> +\tValue type: <prop-encoded-array>\n>> +\tDefinition: Addresses and sizes for the memory of this CLKDIV\n>> +\t\t    peripheral.\n>> +\n>> +- clocks:\n>> +\tUsage: required\n>> +\tValue type: <prop-encoded-array>\n>> +\tDefinition: reference to the xo clock.\n>> +\n>> +- clock-names:\n>> +\tUsage: required\n>> +\tValue type: <stringlist>\n>> +\tDefinition: must be \"xo\".\n> Missing #clock-cells\nAdded in next patch set.\n>\n>> +\n>> +=======\n>> +Example\n>> +=======\n>> +\n>> +pm8998_clk_divs: qcom,clkdiv@5b00 {\n> clock@5b00\nAddressed in next patch.\n>\n>> +\tcompatible = \"qcom,pm8998-clkdiv\";\n>> +\treg = <0x5b00>;\n>> +\t#clock-cells = <1>;\n>> +\tclocks = <&xo_board>;\n>> +\tclock-names = \"xo\";\n>> +\n>> +\tassigned-clocks = <&pm8998_clk_divs 1>,\n>> +\t\t\t  <&pm8998_clk_divs 2>,\n>> +\t\t\t  <&pm8998_clk_divs 3>;\n>> +\tassigned-clock-rates = <9600000>,\n>> +\t\t\t       <9600000>,\n>> +\t\t\t       <9600000>;\n>> +};\n\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at  http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"<devicetree-owner@vger.kernel.org>","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=<UNKNOWN>)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"iBF2dRDu\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key)\n\theader.d=codeaurora.org header.i=@codeaurora.org header.b=\"T38SwAG4\"; \n\tdkim-atps=neutral","pdx-caf-mail.web.codeaurora.org;\n\tdmarc=none (p=none dis=none) header.from=codeaurora.org","pdx-caf-mail.web.codeaurora.org;\n\tspf=none smtp.mailfrom=tirupath@codeaurora.org"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xwkNB05CZz9s7G\n\tfor <incoming-dt@patchwork.ozlabs.org>;\n\tMon, 18 Sep 2017 21:31:06 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1753488AbdIRLbE (ORCPT\n\t<rfc822;incoming-dt@patchwork.ozlabs.org>);\n\tMon, 18 Sep 2017 07:31:04 -0400","from smtp.codeaurora.org ([198.145.29.96]:50238 \"EHLO\n\tsmtp.codeaurora.org\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1752637AbdIRLbC (ORCPT\n\t<rfc822; devicetree@vger.kernel.org>); Mon, 18 Sep 2017 07:31:02 -0400","by smtp.codeaurora.org (Postfix, from userid 1000)\n\tid 4E7E860718; Mon, 18 Sep 2017 11:31:01 +0000 (UTC)","from [10.206.28.109]\n\t(blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com\n\t[103.229.19.19])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\t(Authenticated sender: tirupath@smtp.codeaurora.org)\n\tby smtp.codeaurora.org (Postfix) with ESMTPSA id 3ABAE602B3;\n\tMon, 18 Sep 2017 11:30:57 +0000 (UTC)"],"DKIM-Signature":["v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1505734262;\n\tbh=FExCdWkkFoOiNmZ4hEL3fHMo2mXHNC4hELpE2Ea7G8E=;\n\th=Subject:To:Cc:References:From:Date:In-Reply-To:From;\n\tb=iBF2dRDuvNBEe/d0Eia7TChZxPuBgMlGkAPDXXFDsj59Q9vogqU7ayiQ1//lAEjZb\n\tLwaotw4RAeqbZIB9tH2dK68mHPzNeQhsUN6muScxzzXb3QSs2TVvORSpN2yiHi58m6\n\t2WQpNRHfo39T/SlbOCT9IN7h9BmqoRnlXWIU0ywo=","v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1505734261;\n\tbh=FExCdWkkFoOiNmZ4hEL3fHMo2mXHNC4hELpE2Ea7G8E=;\n\th=Subject:To:Cc:References:From:Date:In-Reply-To:From;\n\tb=T38SwAG4HXk1bVfE34kCBfp6EH029IwBwfJFzObczQwhXBRXSJ26JtCuFGsNJ1pTi\n\t4u2Ot1MhQaqqD6EgWVC5IA7xcHEu0ZSCU9KL2onckAchkwB5FvmAtLbEd3hsrrVZwK\n\tHvagMR4yer5b0VGZPd3whwOHIpbsnAG64sUSW0FE="],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tpdx-caf-mail.web.codeaurora.org","X-Spam-Level":"","X-Spam-Status":"No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00,\n\tDKIM_SIGNED,\n\tT_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0","DMARC-Filter":"OpenDMARC Filter v1.3.2 smtp.codeaurora.org 3ABAE602B3","Subject":"Re: [PATCH V3] clk: qcom: Add spmi_pmic clock divider support","To":"Rob Herring <robh@kernel.org>","Cc":"sboyd@codeaurora.org, mturquette@baylibre.com,\n\tmark.rutland@arm.com, andy.gross@linaro.org,\n\tdavid.brown@linaro.org, linux-clk@vger.kernel.org,\n\tdevicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tlinux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org","References":"<1504699207-9568-1-git-send-email-tirupath@codeaurora.org>\n\t<20170913174032.u33zzo64ipk22vgp@rob-hp-laptop>","From":"Tirupathi Reddy T <tirupath@codeaurora.org>","Message-ID":"<b1a48f0e-7a96-079e-0e68-3d89368316ba@codeaurora.org>","Date":"Mon, 18 Sep 2017 17:00:55 +0530","User-Agent":"Mozilla/5.0 (Windows NT 10.0; WOW64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<20170913174032.u33zzo64ipk22vgp@rob-hp-laptop>","Content-Type":"text/plain; charset=utf-8; format=flowed","Content-Transfer-Encoding":"7bit","Content-Language":"en-US","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"<devicetree.vger.kernel.org>","X-Mailing-List":"devicetree@vger.kernel.org"}}]