[{"id":1767285,"web_url":"http://patchwork.ozlabs.org/comment/1767285/","msgid":"<871snbbwdo.fsf@linaro.org>","list_archive_url":null,"date":"2017-09-12T18:32:51","subject":"Re: [AArch64] Merge stores of D register values of different modes","submitter":{"id":5450,"url":"http://patchwork.ozlabs.org/api/people/5450/","name":"Richard Sandiford","email":"richard.sandiford@linaro.org"},"content":"Thanks for doing this, looks good to me FWIW. I was just wondering:\n\nJackson Woodruff writes:\n> @@ -14712,6 +14712,11 @@ aarch64_operands_ok_for_ldpstp (rtx *operands, bool load,\n> if (!rtx_equal_p (base_1, base_2))\n> return false;\n> \n> + /* Check that the operands are of the same size. */\n> + if (GET_MODE_SIZE (GET_MODE (mem_1))\n> + != GET_MODE_SIZE (GET_MODE (mem_2)))\n> + return false;\n> +\n> offval_1 = INTVAL (offset_1);\n> offval_2 = INTVAL (offset_2);\n> msize = GET_MODE_SIZE (mode);\n\nwhen can this trigger? Your iterators always seem to enforce correct\npairings, so maybe this should be an assert instead.\n\nThanks,\nRichard","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list gcc-patches@gcc.gnu.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=gcc-patches-return-461982-incoming=patchwork.ozlabs.org@gcc.gnu.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org\n\theader.b=\"sodixtjT\"; dkim-atps=neutral","sourceware.org; auth=none"],"Received":["from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xsD1s0j7Jz9s81\n\tfor ;\n\tWed, 13 Sep 2017 04:33:04 +1000 (AEST)","(qmail 105737 invoked by alias); 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I was just wondering:\n> \n> Jackson Woodruff writes:\n>> @@ -14712,6 +14712,11 @@ aarch64_operands_ok_for_ldpstp (rtx *operands, bool load,\n>> if (!rtx_equal_p (base_1, base_2))\n>> return false;\n>> \n>> + /* Check that the operands are of the same size. */\n>> + if (GET_MODE_SIZE (GET_MODE (mem_1))\n>> + != GET_MODE_SIZE (GET_MODE (mem_2)))\n>> + return false;\n>> +\n>> offval_1 = INTVAL (offset_1);\n>> offval_2 = INTVAL (offset_2);\n>> msize = GET_MODE_SIZE (mode);\n> \n> when can this trigger? Your iterators always seem to enforce correct\n> pairings, so maybe this should be an assert instead.\n\nYes, it's true that this should never be triggered. I've changed it to \nan assert.\n\nI have also rebased on top of the renaming of load/store attributes \npatch https://gcc.gnu.org/ml/gcc-patches/2017-09/msg00702.html which had \nsome conflicts with this.\n\nIs the updated patch OK for trunk?\n\nThanks,\nJackson.\n\n> \n> Thanks,\n> Richard\n>\ndiff --git a/gcc/config/aarch64/aarch64-ldpstp.md b/gcc/config/aarch64/aarch64-ldpstp.md\nindex e8dda42c2dd1e30c4607c67a2156ff7813bd89ea..14e860d258e548d4118d957675f8bdbb74615337 100644\n--- a/gcc/config/aarch64/aarch64-ldpstp.md\n+++ b/gcc/config/aarch64/aarch64-ldpstp.md\n@@ -99,10 +99,10 @@\n })\n \n (define_peephole2\n- [(set (match_operand:VD 0 \"register_operand\" \"\")\n-\t(match_operand:VD 1 \"aarch64_mem_pair_operand\" \"\"))\n- (set (match_operand:VD 2 \"register_operand\" \"\")\n-\t(match_operand:VD 3 \"memory_operand\" \"\"))]\n+ [(set (match_operand:DREG 0 \"register_operand\" \"\")\n+\t(match_operand:DREG 1 \"aarch64_mem_pair_operand\" \"\"))\n+ (set (match_operand:DREG2 2 \"register_operand\" \"\")\n+\t(match_operand:DREG2 3 \"memory_operand\" \"\"))]\n \"aarch64_operands_ok_for_ldpstp (operands, true, mode)\"\n [(parallel [(set (match_dup 0) (match_dup 1))\n \t (set (match_dup 2) (match_dup 3))])]\n@@ -119,11 +119,12 @@\n })\n \n (define_peephole2\n- [(set (match_operand:VD 0 \"aarch64_mem_pair_operand\" \"\")\n-\t(match_operand:VD 1 \"register_operand\" \"\"))\n- (set (match_operand:VD 2 \"memory_operand\" \"\")\n-\t(match_operand:VD 3 \"register_operand\" \"\"))]\n- \"TARGET_SIMD && aarch64_operands_ok_for_ldpstp (operands, false, mode)\"\n+ [(set (match_operand:DREG 0 \"aarch64_mem_pair_operand\" \"\")\n+\t(match_operand:DREG 1 \"register_operand\" \"\"))\n+ (set (match_operand:DREG2 2 \"memory_operand\" \"\")\n+\t(match_operand:DREG2 3 \"register_operand\" \"\"))]\n+ \"TARGET_SIMD\n+ && aarch64_operands_ok_for_ldpstp (operands, false, mode)\"\n [(parallel [(set (match_dup 0) (match_dup 1))\n \t (set (match_dup 2) (match_dup 3))])]\n {\n@@ -138,7 +139,6 @@\n }\n })\n \n-\n ;; Handle sign/zero extended consecutive load/store.\n \n (define_peephole2\n@@ -181,6 +181,30 @@\n }\n })\n \n+;; Handle storing of a floating point zero.\n+;; We can match modes that won't work for a stp instruction\n+;; as aarch64_operands_ok_for_ldpstp checks that the modes are\n+;; compatible.\n+(define_peephole2\n+ [(set (match_operand:DSX 0 \"aarch64_mem_pair_operand\" \"\")\n+\t(match_operand:DSX 1 \"aarch64_reg_zero_or_fp_zero\" \"\"))\n+ (set (match_operand: 2 \"memory_operand\" \"\")\n+\t(match_operand: 3 \"aarch64_reg_zero_or_fp_zero\" \"\"))]\n+ \"aarch64_operands_ok_for_ldpstp (operands, false, DImode)\"\n+ [(parallel [(set (match_dup 0) (match_dup 1))\n+\t (set (match_dup 2) (match_dup 3))])]\n+{\n+ rtx base, offset_1, offset_2;\n+\n+ extract_base_offset_in_addr (operands[0], &base, &offset_1);\n+ extract_base_offset_in_addr (operands[2], &base, &offset_2);\n+ if (INTVAL (offset_1) > INTVAL (offset_2))\n+ {\n+ std::swap (operands[0], operands[2]);\n+ std::swap (operands[1], operands[3]);\n+ }\n+})\n+\n ;; Handle consecutive load/store whose offset is out of the range\n ;; supported by ldp/ldpsw/stp. We firstly adjust offset in a scratch\n ;; register, then merge them into ldp/ldpsw/stp by using the adjusted\ndiff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md\nindex 8f045c210502330af9d47f6adfd46a9e36328b74..90f9415b3986eb737ecdfeed43fe798cdbb8334e 100644\n--- a/gcc/config/aarch64/aarch64-simd.md\n+++ b/gcc/config/aarch64/aarch64-simd.md\n@@ -172,11 +172,11 @@\n [(set_attr \"type\" \"neon_store1_1reg\")]\n )\n \n-(define_insn \"load_pair\"\n- [(set (match_operand:VD 0 \"register_operand\" \"=w\")\n-\t(match_operand:VD 1 \"aarch64_mem_pair_operand\" \"Ump\"))\n- (set (match_operand:VD 2 \"register_operand\" \"=w\")\n-\t(match_operand:VD 3 \"memory_operand\" \"m\"))]\n+(define_insn \"load_pair\"\n+ [(set (match_operand:DREG 0 \"register_operand\" \"=w\")\n+\t(match_operand:DREG 1 \"aarch64_mem_pair_operand\" \"Ump\"))\n+ (set (match_operand:DREG2 2 \"register_operand\" \"=w\")\n+\t(match_operand:DREG2 3 \"memory_operand\" \"m\"))]\n \"TARGET_SIMD\n && rtx_equal_p (XEXP (operands[3], 0),\n \t\t plus_constant (Pmode,\n@@ -186,11 +186,11 @@\n [(set_attr \"type\" \"neon_ldp\")]\n )\n \n-(define_insn \"store_pair\"\n- [(set (match_operand:VD 0 \"aarch64_mem_pair_operand\" \"=Ump\")\n-\t(match_operand:VD 1 \"register_operand\" \"w\"))\n- (set (match_operand:VD 2 \"memory_operand\" \"=m\")\n-\t(match_operand:VD 3 \"register_operand\" \"w\"))]\n+(define_insn \"vec_store_pair\"\n+ [(set (match_operand:DREG 0 \"aarch64_mem_pair_operand\" \"=Ump\")\n+\t(match_operand:DREG 1 \"register_operand\" \"w\"))\n+ (set (match_operand:DREG2 2 \"memory_operand\" \"=m\")\n+\t(match_operand:DREG2 3 \"register_operand\" \"w\"))]\n \"TARGET_SIMD\n && rtx_equal_p (XEXP (operands[2], 0),\n \t\t plus_constant (Pmode,\ndiff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c\nindex de1fbdca950b452f5616f37eb0ea719ee793cfdc..ea2ff88f91a18b3fcd43bd0dcafd9ebdcc0b2366 100644\n--- a/gcc/config/aarch64/aarch64.c\n+++ b/gcc/config/aarch64/aarch64.c\n@@ -3191,10 +3191,10 @@ aarch64_gen_store_pair (machine_mode mode, rtx mem1, rtx reg1, rtx mem2,\n switch (mode)\n {\n case E_DImode:\n- return gen_store_pairdi (mem1, reg1, mem2, reg2);\n+ return gen_store_pair_dw_DIDI (mem1, reg1, mem2, reg2);\n \n case E_DFmode:\n- return gen_store_pairdf (mem1, reg1, mem2, reg2);\n+ return gen_store_pair_dw_DFDF (mem1, reg1, mem2, reg2);\n \n default:\n gcc_unreachable ();\n@@ -3211,10 +3211,10 @@ aarch64_gen_load_pair (machine_mode mode, rtx reg1, rtx mem1, rtx reg2,\n switch (mode)\n {\n case E_DImode:\n- return gen_load_pairdi (reg1, mem1, reg2, mem2);\n+ return gen_load_pair_dw_DIDI (reg1, mem1, reg2, mem2);\n \n case E_DFmode:\n- return gen_load_pairdf (reg1, mem1, reg2, mem2);\n+ return gen_load_pair_dw_DFDF (reg1, mem1, reg2, mem2);\n \n default:\n gcc_unreachable ();\n@@ -14751,6 +14751,10 @@ aarch64_operands_ok_for_ldpstp (rtx *operands, bool load,\n if (!rtx_equal_p (base_1, base_2))\n return false;\n \n+ /* The operands must be of the same size. */\n+ gcc_assert (GET_MODE_SIZE (GET_MODE (mem_1))\n+\t == GET_MODE_SIZE (GET_MODE (mem_2)));\n+\n offval_1 = INTVAL (offset_1);\n offval_2 = INTVAL (offset_2);\n msize = GET_MODE_SIZE (mode);\ndiff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md\nindex f8cdb063546afaf3ca977d078da6417729af88a6..46af41379621927ab54835c7adc4cd2b5057fbfe 100644\n--- a/gcc/config/aarch64/aarch64.md\n+++ b/gcc/config/aarch64/aarch64.md\n@@ -1224,15 +1224,15 @@\n \n ;; Operands 1 and 3 are tied together by the final condition; so we allow\n ;; fairly lax checking on the second memory operation.\n-(define_insn \"load_pairsi\"\n- [(set (match_operand:SI 0 \"register_operand\" \"=r,*w\")\n-\t(match_operand:SI 1 \"aarch64_mem_pair_operand\" \"Ump,Ump\"))\n- (set (match_operand:SI 2 \"register_operand\" \"=r,*w\")\n-\t(match_operand:SI 3 \"memory_operand\" \"m,m\"))]\n- \"rtx_equal_p (XEXP (operands[3], 0),\n-\t\tplus_constant (Pmode,\n-\t\t\t XEXP (operands[1], 0),\n-\t\t\t GET_MODE_SIZE (SImode)))\"\n+(define_insn \"load_pair_sw_\"\n+ [(set (match_operand:SX 0 \"register_operand\" \"=r,w\")\n+\t(match_operand:SX 1 \"aarch64_mem_pair_operand\" \"Ump,Ump\"))\n+ (set (match_operand:SX2 2 \"register_operand\" \"=r,w\")\n+\t(match_operand:SX2 3 \"memory_operand\" \"m,m\"))]\n+ \"rtx_equal_p (XEXP (operands[3], 0),\n+\t\t plus_constant (Pmode,\n+\t\t\t\tXEXP (operands[1], 0),\n+\t\t\t\tGET_MODE_SIZE (mode)))\"\n \"@\n ldp\\\\t%w0, %w2, %1\n ldp\\\\t%s0, %s2, %1\"\n@@ -1240,15 +1240,16 @@\n (set_attr \"fp\" \"*,yes\")]\n )\n \n-(define_insn \"load_pairdi\"\n- [(set (match_operand:DI 0 \"register_operand\" \"=r,*w\")\n-\t(match_operand:DI 1 \"aarch64_mem_pair_operand\" \"Ump,Ump\"))\n- (set (match_operand:DI 2 \"register_operand\" \"=r,*w\")\n-\t(match_operand:DI 3 \"memory_operand\" \"m,m\"))]\n- \"rtx_equal_p (XEXP (operands[3], 0),\n-\t\tplus_constant (Pmode,\n-\t\t\t XEXP (operands[1], 0),\n-\t\t\t GET_MODE_SIZE (DImode)))\"\n+;; Storing different modes that can still be merged\n+(define_insn \"load_pair_dw_\"\n+ [(set (match_operand:DX 0 \"register_operand\" \"=r,w\")\n+\t(match_operand:DX 1 \"aarch64_mem_pair_operand\" \"Ump,Ump\"))\n+ (set (match_operand:DX2 2 \"register_operand\" \"=r,w\")\n+\t(match_operand:DX2 3 \"memory_operand\" \"m,m\"))]\n+ \"rtx_equal_p (XEXP (operands[3], 0),\n+\t\t plus_constant (Pmode,\n+\t\t\t\tXEXP (operands[1], 0),\n+\t\t\t\tGET_MODE_SIZE (mode)))\"\n \"@\n ldp\\\\t%x0, %x2, %1\n ldp\\\\t%d0, %d2, %1\"\n@@ -1257,17 +1258,18 @@\n )\n \n \n+\n ;; Operands 0 and 2 are tied together by the final condition; so we allow\n ;; fairly lax checking on the second memory operation.\n-(define_insn \"store_pairsi\"\n- [(set (match_operand:SI 0 \"aarch64_mem_pair_operand\" \"=Ump,Ump\")\n-\t(match_operand:SI 1 \"aarch64_reg_or_zero\" \"rZ,*w\"))\n- (set (match_operand:SI 2 \"memory_operand\" \"=m,m\")\n-\t(match_operand:SI 3 \"aarch64_reg_or_zero\" \"rZ,*w\"))]\n- \"rtx_equal_p (XEXP (operands[2], 0),\n-\t\tplus_constant (Pmode,\n-\t\t\t XEXP (operands[0], 0),\n-\t\t\t GET_MODE_SIZE (SImode)))\"\n+(define_insn \"store_pair_sw_\"\n+ [(set (match_operand:SX 0 \"aarch64_mem_pair_operand\" \"=Ump,Ump\")\n+\t(match_operand:SX 1 \"aarch64_reg_zero_or_fp_zero\" \"rYZ,w\"))\n+ (set (match_operand:SX2 2 \"memory_operand\" \"=m,m\")\n+\t(match_operand:SX2 3 \"aarch64_reg_zero_or_fp_zero\" \"rYZ,w\"))]\n+ \"rtx_equal_p (XEXP (operands[2], 0),\n+\t\t plus_constant (Pmode,\n+\t\t\t\tXEXP (operands[0], 0),\n+\t\t\t\tGET_MODE_SIZE (mode)))\"\n \"@\n stp\\\\t%w1, %w3, %0\n stp\\\\t%s1, %s3, %0\"\n@@ -1275,15 +1277,16 @@\n (set_attr \"fp\" \"*,yes\")]\n )\n \n-(define_insn \"store_pairdi\"\n- [(set (match_operand:DI 0 \"aarch64_mem_pair_operand\" \"=Ump,Ump\")\n-\t(match_operand:DI 1 \"aarch64_reg_or_zero\" \"rZ,*w\"))\n- (set (match_operand:DI 2 \"memory_operand\" \"=m,m\")\n-\t(match_operand:DI 3 \"aarch64_reg_or_zero\" \"rZ,*w\"))]\n- \"rtx_equal_p (XEXP (operands[2], 0),\n-\t\tplus_constant (Pmode,\n-\t\t\t XEXP (operands[0], 0),\n-\t\t\t GET_MODE_SIZE (DImode)))\"\n+;; Storing different modes that can still be merged\n+(define_insn \"store_pair_dw_\"\n+ [(set (match_operand:DX 0 \"aarch64_mem_pair_operand\" \"=Ump,Ump\")\n+\t(match_operand:DX 1 \"aarch64_reg_zero_or_fp_zero\" \"rYZ,w\"))\n+ (set (match_operand:DX2 2 \"memory_operand\" \"=m,m\")\n+\t(match_operand:DX2 3 \"aarch64_reg_zero_or_fp_zero\" \"rYZ,w\"))]\n+ \"rtx_equal_p (XEXP (operands[2], 0),\n+\t\t plus_constant (Pmode,\n+\t\t\t\tXEXP (operands[0], 0),\n+\t\t\t\tGET_MODE_SIZE (mode)))\"\n \"@\n stp\\\\t%x1, %x3, %0\n stp\\\\t%d1, %d3, %0\"\n@@ -1291,74 +1294,6 @@\n (set_attr \"fp\" \"*,yes\")]\n )\n \n-;; Operands 1 and 3 are tied together by the final condition; so we allow\n-;; fairly lax checking on the second memory operation.\n-(define_insn \"load_pairsf\"\n- [(set (match_operand:SF 0 \"register_operand\" \"=w,*r\")\n-\t(match_operand:SF 1 \"aarch64_mem_pair_operand\" \"Ump,Ump\"))\n- (set (match_operand:SF 2 \"register_operand\" \"=w,*r\")\n-\t(match_operand:SF 3 \"memory_operand\" \"m,m\"))]\n- \"rtx_equal_p (XEXP (operands[3], 0),\n-\t\tplus_constant (Pmode,\n-\t\t\t XEXP (operands[1], 0),\n-\t\t\t GET_MODE_SIZE (SFmode)))\"\n- \"@\n- ldp\\\\t%s0, %s2, %1\n- ldp\\\\t%w0, %w2, %1\"\n- [(set_attr \"type\" \"neon_load1_2reg,load_8\")\n- (set_attr \"fp\" \"yes,*\")]\n-)\n-\n-(define_insn \"load_pairdf\"\n- [(set (match_operand:DF 0 \"register_operand\" \"=w,*r\")\n-\t(match_operand:DF 1 \"aarch64_mem_pair_operand\" \"Ump,Ump\"))\n- (set (match_operand:DF 2 \"register_operand\" \"=w,*r\")\n-\t(match_operand:DF 3 \"memory_operand\" \"m,m\"))]\n- \"rtx_equal_p (XEXP (operands[3], 0),\n-\t\tplus_constant (Pmode,\n-\t\t\t XEXP (operands[1], 0),\n-\t\t\t GET_MODE_SIZE (DFmode)))\"\n- \"@\n- ldp\\\\t%d0, %d2, %1\n- ldp\\\\t%x0, %x2, %1\"\n- [(set_attr \"type\" \"neon_load1_2reg,load_16\")\n- (set_attr \"fp\" \"yes,*\")]\n-)\n-\n-;; Operands 0 and 2 are tied together by the final condition; so we allow\n-;; fairly lax checking on the second memory operation.\n-(define_insn \"store_pairsf\"\n- [(set (match_operand:SF 0 \"aarch64_mem_pair_operand\" \"=Ump,Ump\")\n-\t(match_operand:SF 1 \"aarch64_reg_or_fp_zero\" \"w,*rY\"))\n- (set (match_operand:SF 2 \"memory_operand\" \"=m,m\")\n-\t(match_operand:SF 3 \"aarch64_reg_or_fp_zero\" \"w,*rY\"))]\n- \"rtx_equal_p (XEXP (operands[2], 0),\n-\t\tplus_constant (Pmode,\n-\t\t\t XEXP (operands[0], 0),\n-\t\t\t GET_MODE_SIZE (SFmode)))\"\n- \"@\n- stp\\\\t%s1, %s3, %0\n- stp\\\\t%w1, %w3, %0\"\n- [(set_attr \"type\" \"neon_store1_2reg,store_8\")\n- (set_attr \"fp\" \"yes,*\")]\n-)\n-\n-(define_insn \"store_pairdf\"\n- [(set (match_operand:DF 0 \"aarch64_mem_pair_operand\" \"=Ump,Ump\")\n-\t(match_operand:DF 1 \"aarch64_reg_or_fp_zero\" \"w,*rY\"))\n- (set (match_operand:DF 2 \"memory_operand\" \"=m,m\")\n-\t(match_operand:DF 3 \"aarch64_reg_or_fp_zero\" \"w,*rY\"))]\n- \"rtx_equal_p (XEXP (operands[2], 0),\n-\t\tplus_constant (Pmode,\n-\t\t\t XEXP (operands[0], 0),\n-\t\t\t GET_MODE_SIZE (DFmode)))\"\n- \"@\n- stp\\\\t%d1, %d3, %0\n- stp\\\\t%x1, %x3, %0\"\n- [(set_attr \"type\" \"neon_store1_2reg,store_16\")\n- (set_attr \"fp\" \"yes,*\")]\n-)\n-\n ;; Load pair with post-index writeback. This is primarily used in function\n ;; epilogues.\n (define_insn \"loadwb_pair_\"\ndiff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md\nindex 477dc35daf6a1184be15d942c62a111604f62f3c..0e1e9704e3866136959c08ba10077fa31c72c0ce 100644\n--- a/gcc/config/aarch64/iterators.md\n+++ b/gcc/config/aarch64/iterators.md\n@@ -69,6 +69,12 @@\n ;; Double vector modes.\n (define_mode_iterator VD [V8QI V4HI V4HF V2SI V2SF])\n \n+;; All modes stored in registers d0-d31.\n+(define_mode_iterator DREG [V8QI V4HI V4HF V2SI V2SF DF])\n+\n+;; Copy of the above.\n+(define_mode_iterator DREG2 [V8QI V4HI V4HF V2SI V2SF DF])\n+\n ;; vector, 64-bit container, all integer modes\n (define_mode_iterator VD_BHSI [V8QI V4HI V2SI])\n \n@@ -235,6 +241,18 @@\n ;; Double scalar modes\n (define_mode_iterator DX [DI DF])\n \n+;; Duplicate of the above\n+(define_mode_iterator DX2 [DI DF])\n+\n+;; Single scalar modes\n+(define_mode_iterator SX [SI SF])\n+\n+;; Duplicate of the above\n+(define_mode_iterator SX2 [SI SF])\n+\n+;; Single and double integer and float modes\n+(define_mode_iterator DSX [DF DI SF SI])\n+\n ;; Modes available for mul lane operations.\n (define_mode_iterator VMUL [V4HI V8HI V2SI V4SI\n \t\t\t (V4HF \"TARGET_SIMD_F16INST\")\ndiff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md\nindex 11243c4ce00aa7d16a886bb24b01180801c68f4e..ee6e050dd839c329baa05bdfe878b786f1def969 100644\n--- a/gcc/config/aarch64/predicates.md\n+++ b/gcc/config/aarch64/predicates.md\n@@ -62,6 +62,10 @@\n \t(and (match_code \"const_double\")\n \t (match_test \"aarch64_float_const_zero_rtx_p (op)\"))))\n \n+(define_predicate \"aarch64_reg_zero_or_fp_zero\"\n+ (ior (match_operand 0 \"aarch64_reg_or_fp_zero\")\n+ (match_operand 0 \"aarch64_reg_or_zero\")))\n+\n (define_predicate \"aarch64_reg_zero_or_m1_or_1\"\n (and (match_code \"reg,subreg,const_int\")\n (ior (match_operand 0 \"register_operand\")\ndiff --git a/gcc/testsuite/gcc.target/aarch64/ldp_stp_6.c b/gcc/testsuite/gcc.target/aarch64/ldp_stp_6.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..2d982f3389b668f2042d48ba3db04e619fd999f3\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/ldp_stp_6.c\n@@ -0,0 +1,20 @@\n+/* { dg-options \"-O2\" } */\n+\n+typedef float __attribute__ ((vector_size (8))) vec;\n+\n+struct pair\n+{\n+ vec e1;\n+ double e2;\n+};\n+\n+vec tmp;\n+\n+void\n+stp (struct pair *p)\n+{\n+ p->e1 = tmp;\n+ p->e2 = 1.0;\n+\n+ /* { dg-final { scan-assembler \"stp\\td\\[0-9\\]+, d\\[0-9\\]+, \\\\\\[x\\[0-9\\]+\\\\\\]\" } } */\n+}\ndiff --git a/gcc/testsuite/gcc.target/aarch64/ldp_stp_7.c b/gcc/testsuite/gcc.target/aarch64/ldp_stp_7.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..06607de6b3e36a4d759d915a9f7880284391aa08\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/ldp_stp_7.c\n@@ -0,0 +1,47 @@\n+/* { dg-options \"-O2\" } */\n+\n+struct pair\n+{\n+ double a;\n+ long int b;\n+};\n+\n+void\n+stp (struct pair *p)\n+{\n+ p->a = 0.0;\n+ p->b = 1;\n+}\n+\n+/* { dg-final { scan-assembler \"stp\\txzr, x\\[0-9\\]+, \\\\\\[x\\[0-9\\]+\\\\\\]\" } } */\n+\n+void\n+stp2 (struct pair *p)\n+{\n+ p->a = 0.0;\n+ p->b = 0;\n+}\n+\n+struct reverse_pair\n+{\n+ long int a;\n+ double b;\n+};\n+\n+void\n+stp_reverse (struct reverse_pair *p)\n+{\n+ p->a = 1;\n+ p->b = 0.0;\n+}\n+\n+/* { dg-final { scan-assembler \"stp\\tx\\[0-9\\]+, xzr, \\\\\\[x\\[0-9\\]+\\\\\\]\" } } */\n+\n+void\n+stp_reverse2 (struct reverse_pair *p)\n+{\n+ p->a = 0;\n+ p->b = 0.0;\n+}\n+\n+/* { dg-final { scan-assembler-times \"stp\\txzr, xzr, \\\\\\[x\\[0-9\\]+\\\\\\]\" 2 } } */\ndiff --git a/gcc/testsuite/gcc.target/aarch64/ldp_stp_8.c b/gcc/testsuite/gcc.target/aarch64/ldp_stp_8.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..1a47e233814e564d549245683a4e59fdb422bdad\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/ldp_stp_8.c\n@@ -0,0 +1,30 @@\n+/* { dg-options \"-O2\" } */\n+\n+typedef float __attribute__ ((vector_size (8))) fvec;\n+typedef int __attribute__ ((vector_size (8))) ivec;\n+\n+struct pair\n+{\n+ double a;\n+ fvec b;\n+};\n+\n+void ldp (double *a, fvec *b, struct pair *p)\n+{\n+ *a = p->a;\n+ *b = p->b;\n+}\n+\n+struct vec_pair\n+{\n+ fvec a;\n+ ivec b;\n+};\n+\n+void ldp2 (fvec *a, ivec *b, struct vec_pair *p)\n+{\n+ *a = p->a;\n+ *b = p->b;\n+}\n+\n+/* { dg-final { scan-assembler-times \"ldp\\td\\[0-9\\], d\\[0-9\\]+, \\\\\\[x\\[0-9\\]+\\\\\\]\" 2 } } */","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list gcc-patches@gcc.gnu.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org\n\t(client-ip=209.132.180.131; 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