[{"id":1764457,"web_url":"http://patchwork.ozlabs.org/comment/1764457/","msgid":"","list_archive_url":null,"date":"2017-09-06T20:27:56","subject":"Re: [PATCH v4 1/3] arm: npcm: add basic support for Nuvoton BMCs","submitter":{"id":72311,"url":"http://patchwork.ozlabs.org/api/people/72311/","name":"Avi Fishman","email":"avifishman70@gmail.com"},"content":"2017-09-06 11:07 GMT+03:00 Brendan Higgins :\n\n> Adds basic support for the Nuvoton NPCM750 BMC.\n>\n> Signed-off-by: Brendan Higgins \n> ---\n> arch/arm/Kconfig | 2 +\n> arch/arm/Makefile | 1 +\n> arch/arm/mach-npcm/Kconfig | 50 +++++++++++++++++++++++++\n> arch/arm/mach-npcm/Makefile | 3 ++\n> arch/arm/mach-npcm/headsmp.S | 17 +++++++++\n> arch/arm/mach-npcm/npcm7xx.c | 34 +++++++++++++++++\n> arch/arm/mach-npcm/platsmp.c | 89 ++++++++++++++++++++++++++++++\n> ++++++++++++++\n> 7 files changed, 196 insertions(+)\n> create mode 100644 arch/arm/mach-npcm/Kconfig\n> create mode 100644 arch/arm/mach-npcm/Makefile\n> create mode 100644 arch/arm/mach-npcm/headsmp.S\n> create mode 100644 arch/arm/mach-npcm/npcm7xx.c\n> create mode 100644 arch/arm/mach-npcm/platsmp.c\n>\n> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig\n> index 61a0cb15067e..05543f1cfbde 100644\n> --- a/arch/arm/Kconfig\n> +++ b/arch/arm/Kconfig\n> @@ -782,6 +782,8 @@ source \"arch/arm/mach-netx/Kconfig\"\n>\n> source \"arch/arm/mach-nomadik/Kconfig\"\n>\n> +source \"arch/arm/mach-npcm/Kconfig\"\n> +\n> source \"arch/arm/mach-nspire/Kconfig\"\n>\n> source \"arch/arm/plat-omap/Kconfig\"\n> diff --git a/arch/arm/Makefile b/arch/arm/Makefile\n> index 47d3a1ab08d2..60ca50c7d762 100644\n> --- a/arch/arm/Makefile\n> +++ b/arch/arm/Makefile\n> @@ -191,6 +191,7 @@ machine-$(CONFIG_ARCH_MEDIATEK) +=\n> mediatek\n> machine-$(CONFIG_ARCH_MXS) += mxs\n> machine-$(CONFIG_ARCH_NETX) += netx\n> machine-$(CONFIG_ARCH_NOMADIK) += nomadik\n> +machine-$(CONFIG_ARCH_NPCM) += npcm\n> machine-$(CONFIG_ARCH_NSPIRE) += nspire\n> machine-$(CONFIG_ARCH_OXNAS) += oxnas\n> machine-$(CONFIG_ARCH_OMAP1) += omap1\n> diff --git a/arch/arm/mach-npcm/Kconfig b/arch/arm/mach-npcm/Kconfig\n> new file mode 100644\n> index 000000000000..d47061855439\n> --- /dev/null\n> +++ b/arch/arm/mach-npcm/Kconfig\n> @@ -0,0 +1,50 @@\n> +menuconfig ARCH_NPCM\n> + bool \"Nuvoton NPCM Architecture\"\n> + select ARCH_REQUIRE_GPIOLIB\n> + select USE_OF\n> + select PINCTRL\n> + select PINCTRL_NPCM7XX\n> +\n> +if ARCH_NPCM\n> +\n> +comment \"NPCMX50 CPU type\"\n> +\n> +config CPU_NPCM750\n> + depends on ARCH_NPCM && ARCH_MULTI_V7\n> + bool \"Support for NPCM750 BMC CPU (Poleg)\"\n> + select CACHE_L2X0\n> + select CPU_V7\n> + select ARM_GIC\n> + select HAVE_SMP\n> + select SMP\n> + select SMP_ON_UP\n> + select HAVE_ARM_SCU\n> + select HAVE_ARM_TWD if SMP\n> + select ARM_ERRATA_458693\n> + select ARM_ERRATA_720789\n> + select ARM_ERRATA_742231\n> + select ARM_ERRATA_754322\n> + select ARM_ERRATA_764369\n> + select ARM_ERRATA_794072\n> + select PL310_ERRATA_588369\n> + select PL310_ERRATA_727915\n> + select USB_EHCI_ROOT_HUB_TT\n> + select USB_ARCH_HAS_HCD\n> + select USB_ARCH_HAS_EHCI\n> + select USB_EHCI_HCD\n> + select USB_ARCH_HAS_OHCI\n> + select USB_OHCI_HCD\n> + select USB\n> + select FIQ\n> + select CPU_USE_DOMAINS\n> + select GENERIC_CLOCKEVENTS\n> + select CLKDEV_LOOKUP\n> + select COMMON_CLK if OF\n> + select NPCM750_TIMER\n> + select MFD_SYSCON\n> + help\n> + Support for NPCM750 BMC CPU (Poleg).\n> +\n> + Nuvoton NPCM750 BMC based on the Cortex A9.\n> +\n> +endif\n> diff --git a/arch/arm/mach-npcm/Makefile b/arch/arm/mach-npcm/Makefile\n> new file mode 100644\n> index 000000000000..78416055b854\n> --- /dev/null\n> +++ b/arch/arm/mach-npcm/Makefile\n> @@ -0,0 +1,3 @@\n> +AFLAGS_headsmp.o += -march=armv7-a\n> +\n> +obj-$(CONFIG_CPU_NPCM750) += npcm7xx.o platsmp.o headsmp.o\n> diff --git a/arch/arm/mach-npcm/headsmp.S b/arch/arm/mach-npcm/headsmp.S\n> new file mode 100644\n> index 000000000000..9fccbbd49ed4\n> --- /dev/null\n> +++ b/arch/arm/mach-npcm/headsmp.S\n> @@ -0,0 +1,17 @@\n> +/*\n> + * Copyright 2017 Google, Inc.\n> + *\n> + * This program is free software; you can redistribute it and/or modify\n> + * it under the terms of the GNU General Public License version 2 as\n> + * published by the Free Software Foundation.\n> + */\n> +\n> +#include \n> +#include \n> +#include \n> +\n> +ENTRY(npcm7xx_secondary_startup)\n> + safe_svcmode_maskall r0\n>\n\nI saw you answered to Florian Fainelli that the BootRom is not starting\nthe secondary CPU in SVC mode. Are you sure? In our engineering npcm7xx\nrevision, Z1, the BootRom indeed started to run it in IRQ mode but we fixed\nit in the production version, A1, (quite long time ago), I hope you didn't\nget an EB with Z1 you can check that in BootBlock console print:\n> ADC CLK is set to 25000000\n>Last reset was CORST\n>vgaioen=1 and mux gspi.\n>A1 <<====== this is what you should see, if you see Z1 we need to replace\nyour EB\n\n+\n> + b secondary_startup\n> +ENDPROC(npcm7xx_secondary_startup)\n> diff --git a/arch/arm/mach-npcm/npcm7xx.c b/arch/arm/mach-npcm/npcm7xx.c\n> new file mode 100644\n> index 000000000000..132e9d587857\n> --- /dev/null\n> +++ b/arch/arm/mach-npcm/npcm7xx.c\n> @@ -0,0 +1,34 @@\n> +/*\n> + * Copyright (c) 2017 Nuvoton Technology corporation.\n> + * Copyright 2017 Google, Inc.\n> + *\n> + * This program is free software; you can redistribute it and/or modify\n> + * it under the terms of the GNU General Public License version 2 as\n> + * published by the Free Software Foundation.\n> + */\n> +\n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +\n> +#define NPCM7XX_AUX_VAL (L310_AUX_CTRL_INSTR_PREFETCH |\n> \\\n> + L310_AUX_CTRL_DATA_PREFETCH |\n> \\\n> + L310_AUX_CTRL_NS_LOCKDOWN |\n> \\\n> + L310_AUX_CTRL_CACHE_REPLACE_RR |\n> \\\n> + L2C_AUX_CTRL_SHARED_OVERRIDE |\n> \\\n> + L310_AUX_CTRL_FULL_LINE_ZERO)\n> +\n> +static const char *const npcm7xx_dt_match[] = {\n> + \"nuvoton,npcm750\",\n> + NULL\n> +};\n> +\n> +DT_MACHINE_START(NPCM7XX_DT, \"NPCMX50 Chip family\")\n> + .atag_offset = 0x100,\n> + .dt_compat = npcm7xx_dt_match,\n> + .l2c_aux_val = NPCM7XX_AUX_VAL,\n> + .l2c_aux_mask = ~NPCM7XX_AUX_VAL,\n> +MACHINE_END\n> diff --git a/arch/arm/mach-npcm/platsmp.c b/arch/arm/mach-npcm/platsmp.c\n> new file mode 100644\n> index 000000000000..144e3e7ec7e6\n> --- /dev/null\n> +++ b/arch/arm/mach-npcm/platsmp.c\n> @@ -0,0 +1,89 @@\n> +/*\n> + * Copyright 2017 Google, Inc.\n> + *\n> + * This program is free software; you can redistribute it and/or modify\n> + * it under the terms of the GNU General Public License version 2 as\n> + * published by the Free Software Foundation.\n> + */\n> +\n> +#define pr_fmt(fmt) \"PLATSMP: \" fmt\n> +\n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +\n> +#define NPCM7XX_SCRPAD_REG 0x13c\n> +\n> +extern void npcm7xx_secondary_startup(void);\n> +\n> +static int npcm7xx_smp_boot_secondary(unsigned int cpu,\n> + struct task_struct *idle)\n> +{\n> + struct device_node *gcr_np;\n> + void __iomem *gcr_base;\n> + int ret = 0;\n> +\n> + gcr_np = of_find_compatible_node(NULL, NULL,\n> \"nuvoton,npcm750-gcr\");\n> + if (!gcr_np) {\n> + pr_err(\"no gcr device node\\n\");\n> + ret = -EFAULT;\n> + goto out;\n> + }\n> + gcr_base = of_iomap(gcr_np, 0);\n> + if (!gcr_base) {\n> + pr_err(\"could not iomap gcr at: 0x%llx\\n\", gcr_base);\n> + ret = -EFAULT;\n> + goto out;\n> + }\n> +\n> + /* give boot ROM kernel start address. */\n> + iowrite32(__pa_symbol(npcm7xx_secondary_startup), gcr_base +\n> + NPCM7XX_SCRPAD_REG);\n> + /* make sure npcm7xx_secondary_startup is seen by all observers. */\n> + smp_wmb();\n> + dsb_sev();\n> + /* make sure write buffer is drained */\n> + mb();\n> +\n> +out:\n> + iounmap(gcr_base);\n> + return ret;\n> +}\n> +\n> +static void __init npcm7xx_smp_prepare_cpus(unsigned int max_cpus)\n> +{\n> + struct device_node *scu_np;\n> + void __iomem *scu_base;\n> +\n> + scu_np = of_find_compatible_node(NULL, NULL, \"arm,cortex-a9-scu\");\n> + if (!scu_np) {\n> + pr_err(\"no scu device node\\n\");\n> + return;\n> + }\n> + scu_base = of_iomap(scu_np, 0);\n> + if (!scu_base) {\n> + pr_err(\"could not iomap scu at: 0x%llx\\n\", scu_base);\n> + return;\n> + }\n> +\n> + scu_enable(scu_base);\n> +\n> +out:\n> + iounmap(scu_base);\n> +}\n> +\n> +static struct smp_operations npcm7xx_smp_ops __initdata = {\n> + .smp_prepare_cpus = npcm7xx_smp_prepare_cpus,\n> + .smp_boot_secondary = npcm7xx_smp_boot_secondary,\n> +};\n> +\n> +CPU_METHOD_OF_DECLARE(npcm7xx_smp, \"nuvoton,npcm7xx-smp\",\n> &npcm7xx_smp_ops);\n> --\n> 2.14.1.581.gf28d330327-goog\n>\n>\n


2017-09-06 11:07 GMT+03:00 Brendan Higgins <brendanhiggins@google.com>:
Adds basic support for the Nuvoton NPCM750 BMC.

\n
Signed-off-by: Brendan Higgins <brendanhiggins@google.com>
---
 arch/arm/Kconfig             |  2 +
 arch/arm/Makefile            |  1 +
\n
 arch/arm/mach-npcm/Kconfig   | 50 +++++++++++++++++++++++++
 arch/arm/mach-npcm/Makefile  |  3 ++
 arch/arm/mach-npcm/headsmp.S | 17 +++++++++
 arch/arm/mach-npcm/npcm7xx.c | 34 +++++++++++++++++
 arch/arm/mach-npcm/platsmp.c | 89 ++++++++++++++++++++++++++++++++++++++++++++
 7 files changed, 196 insertions(+)
\n
 create mode 100644 arch/arm/mach-npcm/Kconfig
 create mode 100644 arch/arm/mach-npcm/Makefile
 create mode 100644 arch/arm/mach-npcm/headsmp.S
 create mode 100644 arch/arm/mach-npcm/npcm7xx.c
 create mode 100644 arch/arm/mach-npcm/platsmp.c
\n

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 61a0cb15067e..05543f1cfbde 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -782,6 +782,8 @@ source "arch/arm/mach-netx/Kconfig"
\n

 source "arch/arm/mach-nomadik/Kconfig"
\n

+source "arch/arm/mach-npcm/Kconfig"
+
 source "arch/arm/mach-nspire/Kconfig"
\n

 source "arch/arm/plat-omap/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 47d3a1ab08d2..60ca50c7d762 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -191,6 +191,7 @@ machine-$(CONFIG_ARCH_MEDIATEK)             += mediatek
 machine-$(CONFIG_ARCH_MXS)             += mxs
 machine-$(CONFIG_ARCH_NETX)            += netx
 machine-$(CONFIG_ARCH_NOMADIK)         += nomadik
+machine-$(CONFIG_ARCH_NPCM)            += npcm
 machine-$(CONFIG_ARCH_NSPIRE)          += nspire
 machine-$(CONFIG_ARCH_OXNAS)           += oxnas
 machine-$(CONFIG_ARCH_OMAP1)           += omap1
diff --git a/arch/arm/mach-npcm/Kconfig b/arch/arm/mach-npcm/Kconfig
new file mode 100644
\n
index 000000000000..d47061855439
--- /dev/null
+++ b/arch/arm/mach-npcm/Kconfig
@@ -0,0 +1,50 @@
\n
+menuconfig ARCH_NPCM
+       bool "Nuvoton NPCM Architecture"
+       select ARCH_REQUIRE_GPIOLIB
+       select USE_OF
+       select PINCTRL
+       select PINCTRL_NPCM7XX
+
+if ARCH_NPCM
+
+comment "NPCMX50 CPU type"
+
+config CPU_NPCM750
+       depends on ARCH_NPCM && ARCH_MULTI_V7
\n
+       bool "Support for NPCM750 BMC CPU (Poleg)"
+       select CACHE_L2X0
+       select CPU_V7
+       select ARM_GIC
\n
+       select HAVE_SMP
+       select SMP
+       select SMP_ON_UP
+       select HAVE_ARM_SCU
\n
+       select HAVE_ARM_TWD if SMP
\n
+       select ARM_ERRATA_458693
+       select ARM_ERRATA_720789
+       select ARM_ERRATA_742231
\n
+       select ARM_ERRATA_754322
+       select ARM_ERRATA_764369
\n
+       select ARM_ERRATA_794072
+       select PL310_ERRATA_588369
+       select PL310_ERRATA_727915
\n
+       select USB_EHCI_ROOT_HUB_TT
+       select USB_ARCH_HAS_HCD
+       select USB_ARCH_HAS_EHCI
+       select USB_EHCI_HCD
+       select USB_ARCH_HAS_OHCI
+       select USB_OHCI_HCD
+       select USB
+       select FIQ
+       select CPU_USE_DOMAINS
\n
+       select GENERIC_CLOCKEVENTS
\n
+       select CLKDEV_LOOKUP
+       select COMMON_CLK if OF
\n
+       select NPCM750_TIMER
+       select MFD_SYSCON
+       help
\n
+         Support for NPCM750 BMC CPU (Poleg).
+
+         Nuvoton NPCM750 BMC based on the Cortex A9.
+
\n
+endif
diff --git a/arch/arm/mach-npcm/Makefile b/arch/arm/mach-npcm/Makefile
\n
new file mode 100644
index 000000000000..78416055b854
\n
--- /dev/null
+++ b/arch/arm/mach-npcm/Makefile
@@ -0,0 +1,3 @@
\n
+AFLAGS_headsmp.o               += -march=armv7-a
+
+obj-$(CONFIG_CPU_NPCM750)      += npcm7xx.o platsmp.o headsmp.o
\n
diff --git a/arch/arm/mach-npcm/headsmp.S b/arch/arm/mach-npcm/headsmp.S
new file mode 100644
\n
index 000000000000..9fccbbd49ed4
--- /dev/null
+++ b/arch/arm/mach-npcm/headsmp.S
@@ -0,0 +1,17 @@
+/*
\n
+ * Copyright 2017 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
\n
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/linkage.h>
+#include <linux/init.h>
\n
+#include <asm/assembler.h>
+
+ENTRY(npcm7xx_secondary_startup)
+       safe_svcmode_maskall r0

I saw you  answered to Florian Fainelli that the BootRom is not starting the secondary CPU in SVC mode. Are you sure? In our engineering npcm7xx revision, Z1, the BootRom indeed started to run it in IRQ mode but we fixed it in the production version, A1, (quite long time ago), I hope you didn't get an EB with Z1 you can check that in BootBlock console print:
> ADC CLK is set to 25000000
>Last reset was CORST
>vgaioen=1 and mux gspi.
>A1 <<====== this is what you should see, if you see Z1 we need to replace your EB

+
+       b       secondary_startup
+ENDPROC(npcm7xx_secondary_startup)
\n
diff --git a/arch/arm/mach-npcm/npcm7xx.c b/arch/arm/mach-npcm/npcm7xx.c
new file mode 100644
\n
index 000000000000..132e9d587857
\n
--- /dev/null
+++ b/arch/arm/mach-npcm/npcm7xx.c
@@ -0,0 +1,34 @@
+/*
\n
+ * Copyright (c) 2017 Nuvoton Technology corporation.
\n
+ * Copyright 2017 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
\n
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
\n
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+#include <asm/mach/map.h>
+#include <asm/hardware/cache-l2x0.h>
+
+#define NPCM7XX_AUX_VAL (L310_AUX_CTRL_INSTR_PREFETCH |                               \\
+                        L310_AUX_CTRL_DATA_PREFETCH |                         \\
+                        L310_AUX_CTRL_NS_LOCKDOWN |                           \\
+                        L310_AUX_CTRL_CACHE_REPLACE_RR |                      \\
+                        L2C_AUX_CTRL_SHARED_OVERRIDE |                        \\
+                        L310_AUX_CTRL_FULL_LINE_ZERO)
+
+static const char *const npcm7xx_dt_match[] = {
+       "nuvoton,npcm750",
+       NULL
+};
+
+DT_MACHINE_START(NPCM7XX_DT, "NPCMX50 Chip family")
+       .atag_offset    = 0x100,
+       .dt_compat      = npcm7xx_dt_match,
+       .l2c_aux_val    = NPCM7XX_AUX_VAL,
+       .l2c_aux_mask   = ~NPCM7XX_AUX_VAL,
+MACHINE_END
diff --git a/arch/arm/mach-npcm/platsmp.c b/arch/arm/mach-npcm/platsmp.c
new file mode 100644
\n
index 000000000000..144e3e7ec7e6
--- /dev/null
+++ b/arch/arm/mach-npcm/platsmp.c
@@ -0,0 +1,89 @@
+/*
\n
+ * Copyright 2017 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
\n
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define pr_fmt(fmt) "PLATSMP: " fmt
+
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/smp.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_platform.h>
+#include <linux/of_address.h>
+#include <asm/cacheflush.h>
+#include <asm/smp.h>
+#include <asm/smp_plat.h>
+#include <asm/smp_scu.h>
+
+#define NPCM7XX_SCRPAD_REG 0x13c
+
\n
+extern void npcm7xx_secondary_startup(void);
\n
+
+static int npcm7xx_smp_boot_secondary(unsigned int cpu,
\n
+                                     struct task_struct *idle)
+{
+       struct device_node *gcr_np;
+       void __iomem *gcr_base;
+       int ret = 0;
\n
+
+       gcr_np = of_find_compatible_node(NULL, NULL, "nuvoton,npcm750-gcr");
+       if (!gcr_np) {
+               pr_err("no gcr device node\\n");
\n
+               ret = -EFAULT;
+               goto out;
\n
+       }
+       gcr_base = of_iomap(gcr_np, 0);
+       if (!gcr_base) {
+               pr_err("could not iomap gcr at: 0x%llx\\n", gcr_base);
\n
+               ret = -EFAULT;
+               goto out;
+       }
+
+       /* give boot ROM kernel start address. */
+       iowrite32(__pa_symbol(npcm7xx_secondary_startup), gcr_base +
+                 NPCM7XX_SCRPAD_REG);
\n
+       /* make sure npcm7xx_secondary_startup is seen by all observers. */
+       smp_wmb();
+       dsb_sev();
+       /* make sure write buffer is drained */
+       mb();
+
\n
+out:
+       iounmap(gcr_base);
+       return ret;
\n
+}
+
+static void __init npcm7xx_smp_prepare_cpus(unsigned int max_cpus)
+{
\n
+       struct device_node *scu_np;
+       void __iomem *scu_base;
\n
+
+       scu_np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
+       if (!scu_np) {
+               pr_err("no scu device node\\n");
+               return;
+       }
+       scu_base = of_iomap(scu_np, 0);
+       if (!scu_base) {
\n
+               pr_err("could not iomap scu at: 0x%llx\\n", scu_base);
\n
+               return;
+       }
+
+       scu_enable(scu_base);
+
\n
+out:
+       iounmap(scu_base);
\n
+}
+
+static struct smp_operations npcm7xx_smp_ops __initdata = {
+       .smp_prepare_cpus = npcm7xx_smp_prepare_cpus,
+       .smp_boot_secondary = npcm7xx_smp_boot_secondary,
\n
+};
+
+CPU_METHOD_OF_DECLARE(npcm7xx_smp, "nuvoton,npcm7xx-smp", &npcm7xx_smp_ops);
--
2.14.1.581.gf28d330327-goog
\n

\n

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boundary=\"001a113f5b90e3503605588b2de1\"","X-Mailman-Approved-At":"Thu, 07 Sep 2017 11:31:25 +1000","X-BeenThere":"openbmc@lists.ozlabs.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"Development list for OpenBMC ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"mark.rutland@arm.com, devicetree@vger.kernel.org, f.fainelli@gmail.com, \n\ttmaimon77@gmail.com, openbmc@lists.ozlabs.org, linux@armlinux.org.uk,\n\tlinux-kernel@vger.kernel.org, robh+dt@kernel.org,\n\tlinux-arm-kernel@lists.infradead.org","Errors-To":"openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org","Sender":"\"openbmc\"\n\t"}},{"id":1764458,"web_url":"http://patchwork.ozlabs.org/comment/1764458/","msgid":"","list_archive_url":null,"date":"2017-09-06T20:31:43","subject":"Re: [PATCH v4 1/3] arm: npcm: add basic support for Nuvoton BMCs","submitter":{"id":72311,"url":"http://patchwork.ozlabs.org/api/people/72311/","name":"Avi Fishman","email":"avifishman70@gmail.com"},"content":"2017-09-06 11:07 GMT+03:00 Brendan Higgins :\n>\n> Adds basic support for the Nuvoton NPCM750 BMC.\n>\n> Signed-off-by: Brendan Higgins \n> ---\n> arch/arm/Kconfig | 2 +\n> arch/arm/Makefile | 1 +\n> arch/arm/mach-npcm/Kconfig | 50 +++++++++++++++++++++++++\n> arch/arm/mach-npcm/Makefile | 3 ++\n> arch/arm/mach-npcm/headsmp.S | 17 +++++++++\n> arch/arm/mach-npcm/npcm7xx.c | 34 +++++++++++++++++\n> arch/arm/mach-npcm/platsmp.c | 89\n++++++++++++++++++++++++++++++++++++++++++++\n> 7 files changed, 196 insertions(+)\n> create mode 100644 arch/arm/mach-npcm/Kconfig\n> create mode 100644 arch/arm/mach-npcm/Makefile\n> create mode 100644 arch/arm/mach-npcm/headsmp.S\n> create mode 100644 arch/arm/mach-npcm/npcm7xx.c\n> create mode 100644 arch/arm/mach-npcm/platsmp.c\n>\n> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig\n> index 61a0cb15067e..05543f1cfbde 100644\n> --- a/arch/arm/Kconfig\n> +++ b/arch/arm/Kconfig\n> @@ -782,6 +782,8 @@ source \"arch/arm/mach-netx/Kconfig\"\n>\n> source \"arch/arm/mach-nomadik/Kconfig\"\n>\n> +source \"arch/arm/mach-npcm/Kconfig\"\n> +\n> source \"arch/arm/mach-nspire/Kconfig\"\n>\n> source \"arch/arm/plat-omap/Kconfig\"\n> diff --git a/arch/arm/Makefile b/arch/arm/Makefile\n> index 47d3a1ab08d2..60ca50c7d762 100644\n> --- a/arch/arm/Makefile\n> +++ b/arch/arm/Makefile\n> @@ -191,6 +191,7 @@ machine-$(CONFIG_ARCH_MEDIATEK) +=\nmediatek\n> machine-$(CONFIG_ARCH_MXS) += mxs\n> machine-$(CONFIG_ARCH_NETX) += netx\n> machine-$(CONFIG_ARCH_NOMADIK) += nomadik\n> +machine-$(CONFIG_ARCH_NPCM) += npcm\n> machine-$(CONFIG_ARCH_NSPIRE) += nspire\n> machine-$(CONFIG_ARCH_OXNAS) += oxnas\n> machine-$(CONFIG_ARCH_OMAP1) += omap1\n> diff --git a/arch/arm/mach-npcm/Kconfig b/arch/arm/mach-npcm/Kconfig\n> new file mode 100644\n> index 000000000000..d47061855439\n> --- /dev/null\n> +++ b/arch/arm/mach-npcm/Kconfig\n> @@ -0,0 +1,50 @@\n> +menuconfig ARCH_NPCM\n> + bool \"Nuvoton NPCM Architecture\"\n> + select ARCH_REQUIRE_GPIOLIB\n> + select USE_OF\n> + select PINCTRL\n> + select PINCTRL_NPCM7XX\n> +\n> +if ARCH_NPCM\n> +\n> +comment \"NPCMX50 CPU type\"\n> +\n> +config CPU_NPCM750\n> + depends on ARCH_NPCM && ARCH_MULTI_V7\n> + bool \"Support for NPCM750 BMC CPU (Poleg)\"\n> + select CACHE_L2X0\n> + select CPU_V7\n> + select ARM_GIC\n> + select HAVE_SMP\n> + select SMP\n> + select SMP_ON_UP\n> + select HAVE_ARM_SCU\n> + select HAVE_ARM_TWD if SMP\n> + select ARM_ERRATA_458693\n> + select ARM_ERRATA_720789\n> + select ARM_ERRATA_742231\n> + select ARM_ERRATA_754322\n> + select ARM_ERRATA_764369\n> + select ARM_ERRATA_794072\n> + select PL310_ERRATA_588369\n> + select PL310_ERRATA_727915\n> + select USB_EHCI_ROOT_HUB_TT\n> + select USB_ARCH_HAS_HCD\n> + select USB_ARCH_HAS_EHCI\n> + select USB_EHCI_HCD\n> + select USB_ARCH_HAS_OHCI\n> + select USB_OHCI_HCD\n> + select USB\n> + select FIQ\n> + select CPU_USE_DOMAINS\n> + select GENERIC_CLOCKEVENTS\n> + select CLKDEV_LOOKUP\n> + select COMMON_CLK if OF\n> + select NPCM750_TIMER\n> + select MFD_SYSCON\n> + help\n> + Support for NPCM750 BMC CPU (Poleg).\n> +\n> + Nuvoton NPCM750 BMC based on the Cortex A9.\n> +\n> +endif\n> diff --git a/arch/arm/mach-npcm/Makefile b/arch/arm/mach-npcm/Makefile\n> new file mode 100644\n> index 000000000000..78416055b854\n> --- /dev/null\n> +++ b/arch/arm/mach-npcm/Makefile\n> @@ -0,0 +1,3 @@\n> +AFLAGS_headsmp.o += -march=armv7-a\n> +\n> +obj-$(CONFIG_CPU_NPCM750) += npcm7xx.o platsmp.o headsmp.o\n> diff --git a/arch/arm/mach-npcm/headsmp.S b/arch/arm/mach-npcm/headsmp.S\n> new file mode 100644\n> index 000000000000..9fccbbd49ed4\n> --- /dev/null\n> +++ b/arch/arm/mach-npcm/headsmp.S\n> @@ -0,0 +1,17 @@\n> +/*\n> + * Copyright 2017 Google, Inc.\n> + *\n> + * This program is free software; you can redistribute it and/or modify\n> + * it under the terms of the GNU General Public License version 2 as\n> + * published by the Free Software Foundation.\n> + */\n> +\n> +#include \n> +#include \n> +#include \n> +\n> +ENTRY(npcm7xx_secondary_startup)\n> + safe_svcmode_maskall r0\n\nI saw you answered to Florian Fainelli that the BootRom is not starting\nthe secondary CPU in SVC mode. Are you sure? In our engineering npcm7xx\nrevision, Z1, the BootRom indeed started to run it in IRQ mode but we fixed\nit in the production version, A1, (quite long time ago), I hope you didn't\nget an EB with Z1 you can check that in BootBlock console print:\n> ADC CLK is set to 25000000\n>Last reset was CORST\n>vgaioen=1 and mux gspi.\n>A1 <<====== this is what you should see, if you see Z1 we need to replace\nyour EB\n\n> +\n> + b secondary_startup\n> +ENDPROC(npcm7xx_secondary_startup)\n> diff --git a/arch/arm/mach-npcm/npcm7xx.c b/arch/arm/mach-npcm/npcm7xx.c\n> new file mode 100644\n> index 000000000000..132e9d587857\n> --- /dev/null\n> +++ b/arch/arm/mach-npcm/npcm7xx.c\n> @@ -0,0 +1,34 @@\n> +/*\n> + * Copyright (c) 2017 Nuvoton Technology corporation.\n> + * Copyright 2017 Google, Inc.\n> + *\n> + * This program is free software; you can redistribute it and/or modify\n> + * it under the terms of the GNU General Public License version 2 as\n> + * published by the Free Software Foundation.\n> + */\n> +\n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +\n> +#define NPCM7XX_AUX_VAL (L310_AUX_CTRL_INSTR_PREFETCH |\n \\\n> + L310_AUX_CTRL_DATA_PREFETCH |\n \\\n> + L310_AUX_CTRL_NS_LOCKDOWN |\n \\\n> + L310_AUX_CTRL_CACHE_REPLACE_RR |\n \\\n> + L2C_AUX_CTRL_SHARED_OVERRIDE |\n \\\n> + L310_AUX_CTRL_FULL_LINE_ZERO)\n> +\n> +static const char *const npcm7xx_dt_match[] = {\n> + \"nuvoton,npcm750\",\n> + NULL\n> +};\n> +\n> +DT_MACHINE_START(NPCM7XX_DT, \"NPCMX50 Chip family\")\n> + .atag_offset = 0x100,\n> + .dt_compat = npcm7xx_dt_match,\n> + .l2c_aux_val = NPCM7XX_AUX_VAL,\n> + .l2c_aux_mask = ~NPCM7XX_AUX_VAL,\n> +MACHINE_END\n> diff --git a/arch/arm/mach-npcm/platsmp.c b/arch/arm/mach-npcm/platsmp.c\n> new file mode 100644\n> index 000000000000..144e3e7ec7e6\n> --- /dev/null\n> +++ b/arch/arm/mach-npcm/platsmp.c\n> @@ -0,0 +1,89 @@\n> +/*\n> + * Copyright 2017 Google, Inc.\n> + *\n> + * This program is free software; you can redistribute it and/or modify\n> + * it under the terms of the GNU General Public License version 2 as\n> + * published by the Free Software Foundation.\n> + */\n> +\n> +#define pr_fmt(fmt) \"PLATSMP: \" fmt\n> +\n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +\n> +#define NPCM7XX_SCRPAD_REG 0x13c\n> +\n> +extern void npcm7xx_secondary_startup(void);\n> +\n> +static int npcm7xx_smp_boot_secondary(unsigned int cpu,\n> + struct task_struct *idle)\n> +{\n> + struct device_node *gcr_np;\n> + void __iomem *gcr_base;\n> + int ret = 0;\n> +\n> + gcr_np = of_find_compatible_node(NULL, NULL,\n\"nuvoton,npcm750-gcr\");\n> + if (!gcr_np) {\n> + pr_err(\"no gcr device node\\n\");\n> + ret = -EFAULT;\n> + goto out;\n> + }\n> + gcr_base = of_iomap(gcr_np, 0);\n> + if (!gcr_base) {\n> + pr_err(\"could not iomap gcr at: 0x%llx\\n\", gcr_base);\n> + ret = -EFAULT;\n> + goto out;\n> + }\n> +\n> + /* give boot ROM kernel start address. */\n> + iowrite32(__pa_symbol(npcm7xx_secondary_startup), gcr_base +\n> + NPCM7XX_SCRPAD_REG);\n> + /* make sure npcm7xx_secondary_startup is seen by all observers.\n*/\n> + smp_wmb();\n> + dsb_sev();\n> + /* make sure write buffer is drained */\n> + mb();\n> +\n> +out:\n> + iounmap(gcr_base);\n> + return ret;\n> +}\n> +\n> +static void __init npcm7xx_smp_prepare_cpus(unsigned int max_cpus)\n> +{\n> + struct device_node *scu_np;\n> + void __iomem *scu_base;\n> +\n> + scu_np = of_find_compatible_node(NULL, NULL, \"arm,cortex-a9-scu\");\n> + if (!scu_np) {\n> + pr_err(\"no scu device node\\n\");\n> + return;\n> + }\n> + scu_base = of_iomap(scu_np, 0);\n> + if (!scu_base) {\n> + pr_err(\"could not iomap scu at: 0x%llx\\n\", scu_base);\n> + return;\n> + }\n> +\n> + scu_enable(scu_base);\n> +\n> +out:\n> + iounmap(scu_base);\n> +}\n> +\n> +static struct smp_operations npcm7xx_smp_ops __initdata = {\n> + .smp_prepare_cpus = npcm7xx_smp_prepare_cpus,\n> + .smp_boot_secondary = npcm7xx_smp_boot_secondary,\n> +};\n> +\n> +CPU_METHOD_OF_DECLARE(npcm7xx_smp, \"nuvoton,npcm7xx-smp\",\n&npcm7xx_smp_ops);\n> --\n> 2.14.1.581.gf28d330327-goog\n>\n


2017-09-06 11:07 GMT+03:00 Brendan Higgins <brendanhiggins@google.com>:
>
> Adds basic support for the Nuvoton NPCM750 BMC.
>
> Signed-off-by: Brendan Higgins <brendanhiggins@google.com>
> ---
>  arch/arm/Kconfig             |  2 +
>  arch/arm/Makefile            |  1 +
>  arch/arm/mach-npcm/Kconfig   | 50 +++++++++++++++++++++++++
>  arch/arm/mach-npcm/Makefile  |  3 ++
>  arch/arm/mach-npcm/headsmp.S | 17 +++++++++
>  arch/arm/mach-npcm/npcm7xx.c | 34 +++++++++++++++++
>  arch/arm/mach-npcm/platsmp.c | 89 ++++++++++++++++++++++++++++++++++++++++++++
>  7 files changed, 196 insertions(+)
>  create mode 100644 arch/arm/mach-npcm/Kconfig
>  create mode 100644 arch/arm/mach-npcm/Makefile
>  create mode 100644 arch/arm/mach-npcm/headsmp.S
>  create mode 100644 arch/arm/mach-npcm/npcm7xx.c
>  create mode 100644 arch/arm/mach-npcm/platsmp.c
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 61a0cb15067e..05543f1cfbde 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -782,6 +782,8 @@ source "arch/arm/mach-netx/Kconfig"
>
>  source "arch/arm/mach-nomadik/Kconfig"
>
> +source "arch/arm/mach-npcm/Kconfig"
> +
>  source "arch/arm/mach-nspire/Kconfig"
>
>  source "arch/arm/plat-omap/Kconfig"
> diff --git a/arch/arm/Makefile b/arch/arm/Makefile
> index 47d3a1ab08d2..60ca50c7d762 100644
> --- a/arch/arm/Makefile
> +++ b/arch/arm/Makefile
> @@ -191,6 +191,7 @@ machine-$(CONFIG_ARCH_MEDIATEK)             += mediatek
>  machine-$(CONFIG_ARCH_MXS)             += mxs
>  machine-$(CONFIG_ARCH_NETX)            += netx
>  machine-$(CONFIG_ARCH_NOMADIK)         += nomadik
> +machine-$(CONFIG_ARCH_NPCM)            += npcm
>  machine-$(CONFIG_ARCH_NSPIRE)          += nspire
>  machine-$(CONFIG_ARCH_OXNAS)           += oxnas
>  machine-$(CONFIG_ARCH_OMAP1)           += omap1
> diff --git a/arch/arm/mach-npcm/Kconfig b/arch/arm/mach-npcm/Kconfig
> new file mode 100644
> index 000000000000..d47061855439
> --- /dev/null
> +++ b/arch/arm/mach-npcm/Kconfig
> @@ -0,0 +1,50 @@
> +menuconfig ARCH_NPCM
> +       bool "Nuvoton NPCM Architecture"
> +       select ARCH_REQUIRE_GPIOLIB
> +       select USE_OF
> +       select PINCTRL
> +       select PINCTRL_NPCM7XX
> +
> +if ARCH_NPCM
> +
> +comment "NPCMX50 CPU type"
> +
> +config CPU_NPCM750
> +       depends on ARCH_NPCM && ARCH_MULTI_V7
> +       bool "Support for NPCM750 BMC CPU (Poleg)"
> +       select CACHE_L2X0
> +       select CPU_V7
> +       select ARM_GIC
> +       select HAVE_SMP
> +       select SMP
> +       select SMP_ON_UP
> +       select HAVE_ARM_SCU
> +       select HAVE_ARM_TWD if SMP
> +       select ARM_ERRATA_458693
> +       select ARM_ERRATA_720789
> +       select ARM_ERRATA_742231
> +       select ARM_ERRATA_754322
> +       select ARM_ERRATA_764369
> +       select ARM_ERRATA_794072
> +       select PL310_ERRATA_588369
> +       select PL310_ERRATA_727915
> +       select USB_EHCI_ROOT_HUB_TT
> +       select USB_ARCH_HAS_HCD
> +       select USB_ARCH_HAS_EHCI
> +       select USB_EHCI_HCD
> +       select USB_ARCH_HAS_OHCI
> +       select USB_OHCI_HCD
> +       select USB
> +       select FIQ
> +       select CPU_USE_DOMAINS
> +       select GENERIC_CLOCKEVENTS
> +       select CLKDEV_LOOKUP
> +       select COMMON_CLK if OF
> +       select NPCM750_TIMER
> +       select MFD_SYSCON
> +       help
> +         Support for NPCM750 BMC CPU (Poleg).
> +
> +         Nuvoton NPCM750 BMC based on the Cortex A9.
> +
> +endif
> diff --git a/arch/arm/mach-npcm/Makefile b/arch/arm/mach-npcm/Makefile
> new file mode 100644
> index 000000000000..78416055b854
> --- /dev/null
> +++ b/arch/arm/mach-npcm/Makefile
> @@ -0,0 +1,3 @@
> +AFLAGS_headsmp.o               += -march=armv7-a
> +
> +obj-$(CONFIG_CPU_NPCM750)      += npcm7xx.o platsmp.o headsmp.o
> diff --git a/arch/arm/mach-npcm/headsmp.S b/arch/arm/mach-npcm/headsmp.S
> new file mode 100644
> index 000000000000..9fccbbd49ed4
> --- /dev/null
> +++ b/arch/arm/mach-npcm/headsmp.S
> @@ -0,0 +1,17 @@
> +/*
> + * Copyright 2017 Google, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/linkage.h>
> +#include <linux/init.h>
> +#include <asm/assembler.h>
> +
> +ENTRY(npcm7xx_secondary_startup)
> +       safe_svcmode_maskall r0

I saw you  answered to Florian Fainelli that the BootRom is not starting the secondary CPU in SVC mode. Are you sure? In our engineering npcm7xx revision, Z1, the BootRom indeed started to run it in IRQ mode but we fixed it in the production version, A1, (quite long time ago), I hope you didn't get an EB with Z1 you can check that in BootBlock console print:
> ADC CLK is set to 25000000
>Last reset was CORST
>vgaioen=1 and mux gspi.
>A1 <<====== this is what you should see, if you see Z1 we need to replace your EB

> +
> +       b       secondary_startup
> +ENDPROC(npcm7xx_secondary_startup)
> diff --git a/arch/arm/mach-npcm/npcm7xx.c b/arch/arm/mach-npcm/npcm7xx.c
> new file mode 100644
> index 000000000000..132e9d587857
> --- /dev/null
> +++ b/arch/arm/mach-npcm/npcm7xx.c
> @@ -0,0 +1,34 @@
> +/*
> + * Copyright (c) 2017 Nuvoton Technology corporation.
> + * Copyright 2017 Google, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/types.h>
> +#include <asm/mach/arch.h>
> +#include <asm/mach-types.h>
> +#include <asm/mach/map.h>
> +#include <asm/hardware/cache-l2x0.h>
> +
> +#define NPCM7XX_AUX_VAL (L310_AUX_CTRL_INSTR_PREFETCH |                               \\
> +                        L310_AUX_CTRL_DATA_PREFETCH |                         \\
> +                        L310_AUX_CTRL_NS_LOCKDOWN |                           \\
> +                        L310_AUX_CTRL_CACHE_REPLACE_RR |                      \\
> +                        L2C_AUX_CTRL_SHARED_OVERRIDE |                        \\
> +                        L310_AUX_CTRL_FULL_LINE_ZERO)
> +
> +static const char *const npcm7xx_dt_match[] = {
> +       "nuvoton,npcm750",
> +       NULL
> +};
> +
> +DT_MACHINE_START(NPCM7XX_DT, "NPCMX50 Chip family")
> +       .atag_offset    = 0x100,
> +       .dt_compat      = npcm7xx_dt_match,
> +       .l2c_aux_val    = NPCM7XX_AUX_VAL,
> +       .l2c_aux_mask   = ~NPCM7XX_AUX_VAL,
> +MACHINE_END
> diff --git a/arch/arm/mach-npcm/platsmp.c b/arch/arm/mach-npcm/platsmp.c
> new file mode 100644
> index 000000000000..144e3e7ec7e6
> --- /dev/null
> +++ b/arch/arm/mach-npcm/platsmp.c
> @@ -0,0 +1,89 @@
> +/*
> + * Copyright 2017 Google, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#define pr_fmt(fmt) "PLATSMP: " fmt
> +
> +#include <linux/delay.h>
> +#include <linux/device.h>
> +#include <linux/smp.h>
> +#include <linux/io.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/of_platform.h>
> +#include <linux/of_address.h>
> +#include <asm/cacheflush.h>
> +#include <asm/smp.h>
> +#include <asm/smp_plat.h>
> +#include <asm/smp_scu.h>
> +
> +#define NPCM7XX_SCRPAD_REG 0x13c
> +
> +extern void npcm7xx_secondary_startup(void);
> +
> +static int npcm7xx_smp_boot_secondary(unsigned int cpu,
> +                                     struct task_struct *idle)
> +{
> +       struct device_node *gcr_np;
> +       void __iomem *gcr_base;
> +       int ret = 0;
> +
> +       gcr_np = of_find_compatible_node(NULL, NULL, "nuvoton,npcm750-gcr");
> +       if (!gcr_np) {
> +               pr_err("no gcr device node\\n");
> +               ret = -EFAULT;
> +               goto out;
> +       }
> +       gcr_base = of_iomap(gcr_np, 0);
> +       if (!gcr_base) {
> +               pr_err("could not iomap gcr at: 0x%llx\\n", gcr_base);
> +               ret = -EFAULT;
> +               goto out;
> +       }
> +
> +       /* give boot ROM kernel start address. */
> +       iowrite32(__pa_symbol(npcm7xx_secondary_startup), gcr_base +
> +                 NPCM7XX_SCRPAD_REG);
> +       /* make sure npcm7xx_secondary_startup is seen by all observers. */
> +       smp_wmb();
> +       dsb_sev();
> +       /* make sure write buffer is drained */
> +       mb();
> +
> +out:
> +       iounmap(gcr_base);
> +       return ret;
> +}
> +
> +static void __init npcm7xx_smp_prepare_cpus(unsigned int max_cpus)
> +{
> +       struct device_node *scu_np;
> +       void __iomem *scu_base;
> +
> +       scu_np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
> +       if (!scu_np) {
> +               pr_err("no scu device node\\n");
> +               return;
> +       }
> +       scu_base = of_iomap(scu_np, 0);
> +       if (!scu_base) {
> +               pr_err("could not iomap scu at: 0x%llx\\n", scu_base);
> +               return;
> +       }
> +
> +       scu_enable(scu_base);
> +
> +out:
> +       iounmap(scu_base);
> +}
> +
> +static struct smp_operations npcm7xx_smp_ops __initdata = {
> +       .smp_prepare_cpus = npcm7xx_smp_prepare_cpus,
> +       .smp_boot_secondary = npcm7xx_smp_boot_secondary,
> +};
> +
> +CPU_METHOD_OF_DECLARE(npcm7xx_smp, "nuvoton,npcm7xx-smp", &npcm7xx_smp_ops);
> --
> 2.14.1.581.gf28d330327-goog
>
","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","openbmc@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","openbmc@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xnjbn5W3Vz9t2r\n\tfor ;\n\tThu, 7 Sep 2017 11:31:49 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xnjbn3fpzzDrWC\n\tfor ;\n\tThu, 7 Sep 2017 11:31:49 +1000 (AEST)","from mail-oi0-x243.google.com (mail-oi0-x243.google.com\n\t[IPv6:2607:f8b0:4003:c06::243])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xnZxZ3ZZFzDqgy\n\tfor ; Thu, 7 Sep 2017 06:31:46 +1000 (AEST)","by mail-oi0-x243.google.com with SMTP id h70so5182355oic.4\n\tfor ; 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boundary=\"001a113e39486d0c9905588b3b33\"","X-Mailman-Approved-At":"Thu, 07 Sep 2017 11:31:25 +1000","X-BeenThere":"openbmc@lists.ozlabs.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"Development list for OpenBMC ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"mark.rutland@arm.com, devicetree@vger.kernel.org, f.fainelli@gmail.com, \n\ttmaimon77@gmail.com, openbmc@lists.ozlabs.org, linux@armlinux.org.uk,\n\tlinux-kernel@vger.kernel.org, robh+dt@kernel.org,\n\tlinux-arm-kernel@lists.infradead.org","Errors-To":"openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org","Sender":"\"openbmc\"\n\t"}},{"id":1764459,"web_url":"http://patchwork.ozlabs.org/comment/1764459/","msgid":"","list_archive_url":null,"date":"2017-09-06T21:04:09","subject":"Re: [PATCH v4 1/3] arm: npcm: add basic support for Nuvoton BMCs","submitter":{"id":72311,"url":"http://patchwork.ozlabs.org/api/people/72311/","name":"Avi Fishman","email":"avifishman70@gmail.com"},"content":"Sorry for sending again some mailing list rejected it due to HTML\ninvolved (althoug I tried Plain Text), Trying again.\n\n2017-09-06 11:07 GMT+03:00 Brendan Higgins :\n> Adds basic support for the Nuvoton NPCM750 BMC.\n>\n> Signed-off-by: Brendan Higgins \n> ---\n> arch/arm/Kconfig | 2 +\n> arch/arm/Makefile | 1 +\n> arch/arm/mach-npcm/Kconfig | 50 +++++++++++++++++++++++++\n> arch/arm/mach-npcm/Makefile | 3 ++\n> arch/arm/mach-npcm/headsmp.S | 17 +++++++++\n> arch/arm/mach-npcm/npcm7xx.c | 34 +++++++++++++++++\n> arch/arm/mach-npcm/platsmp.c | 89 ++++++++++++++++++++++++++++++++++++++++++++\n> 7 files changed, 196 insertions(+)\n> create mode 100644 arch/arm/mach-npcm/Kconfig\n> create mode 100644 arch/arm/mach-npcm/Makefile\n> create mode 100644 arch/arm/mach-npcm/headsmp.S\n> create mode 100644 arch/arm/mach-npcm/npcm7xx.c\n> create mode 100644 arch/arm/mach-npcm/platsmp.c\n>\n> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig\n> index 61a0cb15067e..05543f1cfbde 100644\n> --- a/arch/arm/Kconfig\n> +++ b/arch/arm/Kconfig\n> @@ -782,6 +782,8 @@ source \"arch/arm/mach-netx/Kconfig\"\n>\n> source \"arch/arm/mach-nomadik/Kconfig\"\n>\n> +source \"arch/arm/mach-npcm/Kconfig\"\n> +\n> source \"arch/arm/mach-nspire/Kconfig\"\n>\n> source \"arch/arm/plat-omap/Kconfig\"\n> diff --git a/arch/arm/Makefile b/arch/arm/Makefile\n> index 47d3a1ab08d2..60ca50c7d762 100644\n> --- a/arch/arm/Makefile\n> +++ b/arch/arm/Makefile\n> @@ -191,6 +191,7 @@ machine-$(CONFIG_ARCH_MEDIATEK) += mediatek\n> machine-$(CONFIG_ARCH_MXS) += mxs\n> machine-$(CONFIG_ARCH_NETX) += netx\n> machine-$(CONFIG_ARCH_NOMADIK) += nomadik\n> +machine-$(CONFIG_ARCH_NPCM) += npcm\n> machine-$(CONFIG_ARCH_NSPIRE) += nspire\n> machine-$(CONFIG_ARCH_OXNAS) += oxnas\n> machine-$(CONFIG_ARCH_OMAP1) += omap1\n> diff --git a/arch/arm/mach-npcm/Kconfig b/arch/arm/mach-npcm/Kconfig\n> new file mode 100644\n> index 000000000000..d47061855439\n> --- /dev/null\n> +++ b/arch/arm/mach-npcm/Kconfig\n> @@ -0,0 +1,50 @@\n> +menuconfig ARCH_NPCM\n> + bool \"Nuvoton NPCM Architecture\"\n> + select ARCH_REQUIRE_GPIOLIB\n> + select USE_OF\n> + select PINCTRL\n> + select PINCTRL_NPCM7XX\n> +\n> +if ARCH_NPCM\n> +\n> +comment \"NPCMX50 CPU type\"\n> +\n> +config CPU_NPCM750\n> + depends on ARCH_NPCM && ARCH_MULTI_V7\n> + bool \"Support for NPCM750 BMC CPU (Poleg)\"\n> + select CACHE_L2X0\n> + select CPU_V7\n> + select ARM_GIC\n> + select HAVE_SMP\n> + select SMP\n> + select SMP_ON_UP\n> + select HAVE_ARM_SCU\n> + select HAVE_ARM_TWD if SMP\n> + select ARM_ERRATA_458693\n> + select ARM_ERRATA_720789\n> + select ARM_ERRATA_742231\n> + select ARM_ERRATA_754322\n> + select ARM_ERRATA_764369\n> + select ARM_ERRATA_794072\n> + select PL310_ERRATA_588369\n> + select PL310_ERRATA_727915\n> + select USB_EHCI_ROOT_HUB_TT\n> + select USB_ARCH_HAS_HCD\n> + select USB_ARCH_HAS_EHCI\n> + select USB_EHCI_HCD\n> + select USB_ARCH_HAS_OHCI\n> + select USB_OHCI_HCD\n> + select USB\n> + select FIQ\n> + select CPU_USE_DOMAINS\n> + select GENERIC_CLOCKEVENTS\n> + select CLKDEV_LOOKUP\n> + select COMMON_CLK if OF\n> + select NPCM750_TIMER\n> + select MFD_SYSCON\n> + help\n> + Support for NPCM750 BMC CPU (Poleg).\n> +\n> + Nuvoton NPCM750 BMC based on the Cortex A9.\n> +\n> +endif\n> diff --git a/arch/arm/mach-npcm/Makefile b/arch/arm/mach-npcm/Makefile\n> new file mode 100644\n> index 000000000000..78416055b854\n> --- /dev/null\n> +++ b/arch/arm/mach-npcm/Makefile\n> @@ -0,0 +1,3 @@\n> +AFLAGS_headsmp.o += -march=armv7-a\n> +\n> +obj-$(CONFIG_CPU_NPCM750) += npcm7xx.o platsmp.o headsmp.o\n> diff --git a/arch/arm/mach-npcm/headsmp.S b/arch/arm/mach-npcm/headsmp.S\n> new file mode 100644\n> index 000000000000..9fccbbd49ed4\n> --- /dev/null\n> +++ b/arch/arm/mach-npcm/headsmp.S\n> @@ -0,0 +1,17 @@\n> +/*\n> + * Copyright 2017 Google, Inc.\n> + *\n> + * This program is free software; you can redistribute it and/or modify\n> + * it under the terms of the GNU General Public License version 2 as\n> + * published by the Free Software Foundation.\n> + */\n> +\n> +#include \n> +#include \n> +#include \n> +\n> +ENTRY(npcm7xx_secondary_startup)\n> + safe_svcmode_maskall r0\n\nI saw you answered to Florian Fainelli that the BootRom is not\nstarting the secondary CPU in SVC mode. Are you sure? In our\nengineering npcm7xx revision, Z1, the BootRom indeed started to run it\nin IRQ mode but we fixed it in the production version, A1, (quite long\ntime ago), I hope you didn't get an EB with Z1 you can check that in\nBootBlock console print:\n> ADC CLK is set to 25000000\n>Last reset was CORST\n>vgaioen=1 and mux gspi.\n>A1 <<====== this is what you should see, if you see Z1 we need to replace your EB\n\n> +\n> + b secondary_startup\n> +ENDPROC(npcm7xx_secondary_startup)\n> diff --git a/arch/arm/mach-npcm/npcm7xx.c b/arch/arm/mach-npcm/npcm7xx.c\n> new file mode 100644\n> index 000000000000..132e9d587857\n> --- /dev/null\n> +++ b/arch/arm/mach-npcm/npcm7xx.c\n> @@ -0,0 +1,34 @@\n> +/*\n> + * Copyright (c) 2017 Nuvoton Technology corporation.\n> + * Copyright 2017 Google, Inc.\n> + *\n> + * This program is free software; you can redistribute it and/or modify\n> + * it under the terms of the GNU General Public License version 2 as\n> + * published by the Free Software Foundation.\n> + */\n> +\n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +\n> +#define NPCM7XX_AUX_VAL (L310_AUX_CTRL_INSTR_PREFETCH | \\\n> + L310_AUX_CTRL_DATA_PREFETCH | \\\n> + L310_AUX_CTRL_NS_LOCKDOWN | \\\n> + L310_AUX_CTRL_CACHE_REPLACE_RR | \\\n> + L2C_AUX_CTRL_SHARED_OVERRIDE | \\\n> + L310_AUX_CTRL_FULL_LINE_ZERO)\n> +\n> +static const char *const npcm7xx_dt_match[] = {\n> + \"nuvoton,npcm750\",\n> + NULL\n> +};\n> +\n> +DT_MACHINE_START(NPCM7XX_DT, \"NPCMX50 Chip family\")\n> + .atag_offset = 0x100,\n> + .dt_compat = npcm7xx_dt_match,\n> + .l2c_aux_val = NPCM7XX_AUX_VAL,\n> + .l2c_aux_mask = ~NPCM7XX_AUX_VAL,\n> +MACHINE_END\n> diff --git a/arch/arm/mach-npcm/platsmp.c b/arch/arm/mach-npcm/platsmp.c\n> new file mode 100644\n> index 000000000000..144e3e7ec7e6\n> --- /dev/null\n> +++ b/arch/arm/mach-npcm/platsmp.c\n> @@ -0,0 +1,89 @@\n> +/*\n> + * Copyright 2017 Google, Inc.\n> + *\n> + * This program is free software; you can redistribute it and/or modify\n> + * it under the terms of the GNU General Public License version 2 as\n> + * published by the Free Software Foundation.\n> + */\n> +\n> +#define pr_fmt(fmt) \"PLATSMP: \" fmt\n> +\n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +\n> +#define NPCM7XX_SCRPAD_REG 0x13c\n> +\n> +extern void npcm7xx_secondary_startup(void);\n> +\n> +static int npcm7xx_smp_boot_secondary(unsigned int cpu,\n> + struct task_struct *idle)\n> +{\n> + struct device_node *gcr_np;\n> + void __iomem *gcr_base;\n> + int ret = 0;\n> +\n> + gcr_np = of_find_compatible_node(NULL, NULL, \"nuvoton,npcm750-gcr\");\n> + if (!gcr_np) {\n> + pr_err(\"no gcr device node\\n\");\n> + ret = -EFAULT;\n> + goto out;\n> + }\n> + gcr_base = of_iomap(gcr_np, 0);\n> + if (!gcr_base) {\n> + pr_err(\"could not iomap gcr at: 0x%llx\\n\", gcr_base);\n> + ret = -EFAULT;\n> + goto out;\n> + }\n> +\n> + /* give boot ROM kernel start address. */\n> + iowrite32(__pa_symbol(npcm7xx_secondary_startup), gcr_base +\n> + NPCM7XX_SCRPAD_REG);\n> + /* make sure npcm7xx_secondary_startup is seen by all observers. */\n> + smp_wmb();\n> + dsb_sev();\n> + /* make sure write buffer is drained */\n> + mb();\n> +\n> +out:\n> + iounmap(gcr_base);\n> + return ret;\n> +}\n> +\n> +static void __init npcm7xx_smp_prepare_cpus(unsigned int max_cpus)\n> +{\n> + struct device_node *scu_np;\n> + void __iomem *scu_base;\n> +\n> + scu_np = of_find_compatible_node(NULL, NULL, \"arm,cortex-a9-scu\");\n> + if (!scu_np) {\n> + pr_err(\"no scu device node\\n\");\n> + return;\n> + }\n> + scu_base = of_iomap(scu_np, 0);\n> + if (!scu_base) {\n> + pr_err(\"could not iomap scu at: 0x%llx\\n\", scu_base);\n> + return;\n> + }\n> +\n> + scu_enable(scu_base);\n> +\n> +out:\n> + iounmap(scu_base);\n> +}\n> +\n> +static struct smp_operations npcm7xx_smp_ops __initdata = {\n> + .smp_prepare_cpus = npcm7xx_smp_prepare_cpus,\n> + .smp_boot_secondary = npcm7xx_smp_boot_secondary,\n> +};\n> +\n> +CPU_METHOD_OF_DECLARE(npcm7xx_smp, \"nuvoton,npcm7xx-smp\", &npcm7xx_smp_ops);\n> --\n> 2.14.1.581.gf28d330327-goog\n>","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","openbmc@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","openbmc@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xnjc92pQlz9sCZ\n\tfor ;\n\tThu, 7 Sep 2017 11:32:09 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xnjc91dRfzDrW9\n\tfor ;\n\tThu, 7 Sep 2017 11:32:09 +1000 (AEST)","from mail-oi0-x242.google.com (mail-oi0-x242.google.com\n\t[IPv6:2607:f8b0:4003:c06::242])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 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(PDT)","MIME-Version":"1.0","In-Reply-To":"<20170906080751.6773-2-brendanhiggins@google.com>","References":"<20170906080751.6773-1-brendanhiggins@google.com>\n\t<20170906080751.6773-2-brendanhiggins@google.com>","From":"Avi Fishman ","Date":"Thu, 7 Sep 2017 00:04:09 +0300","Message-ID":"","Subject":"Re: [PATCH v4 1/3] arm: npcm: add basic support for Nuvoton BMCs","To":"Brendan Higgins ","Content-Type":"text/plain; charset=\"UTF-8\"","X-Mailman-Approved-At":"Thu, 07 Sep 2017 11:31:25 +1000","X-BeenThere":"openbmc@lists.ozlabs.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"Development list for OpenBMC ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"mark.rutland@arm.com, devicetree@vger.kernel.org, f.fainelli@gmail.com, \n\ttmaimon77@gmail.com, openbmc@lists.ozlabs.org, linux@armlinux.org.uk,\n\tlinux-kernel@vger.kernel.org, robh+dt@kernel.org,\n\tlinux-arm-kernel@lists.infradead.org","Errors-To":"openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org","Sender":"\"openbmc\"\n\t"}},{"id":1764501,"web_url":"http://patchwork.ozlabs.org/comment/1764501/","msgid":"","list_archive_url":null,"date":"2017-09-07T05:09:05","subject":"Re: [PATCH v4 1/3] arm: npcm: add basic support for Nuvoton BMCs","submitter":{"id":69647,"url":"http://patchwork.ozlabs.org/api/people/69647/","name":"Brendan Higgins","email":"brendanhiggins@google.com"},"content":"On Wed, Sep 6, 2017 at 2:04 PM, Avi Fishman wrote:\n> Sorry for sending again some mailing list rejected it due to HTML\n> involved (althoug I tried Plain Text), Trying again.\n>\n> 2017-09-06 11:07 GMT+03:00 Brendan Higgins :\n>> Adds basic support for the Nuvoton NPCM750 BMC.\n>>\n>> Signed-off-by: Brendan Higgins \n>> ---\n>> arch/arm/Kconfig | 2 +\n>> arch/arm/Makefile | 1 +\n>> arch/arm/mach-npcm/Kconfig | 50 +++++++++++++++++++++++++\n>> arch/arm/mach-npcm/Makefile | 3 ++\n>> arch/arm/mach-npcm/headsmp.S | 17 +++++++++\n>> arch/arm/mach-npcm/npcm7xx.c | 34 +++++++++++++++++\n>> arch/arm/mach-npcm/platsmp.c | 89 ++++++++++++++++++++++++++++++++++++++++++++\n>> 7 files changed, 196 insertions(+)\n>> create mode 100644 arch/arm/mach-npcm/Kconfig\n>> create mode 100644 arch/arm/mach-npcm/Makefile\n>> create mode 100644 arch/arm/mach-npcm/headsmp.S\n>> create mode 100644 arch/arm/mach-npcm/npcm7xx.c\n>> create mode 100644 arch/arm/mach-npcm/platsmp.c\n>>\n>> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig\n>> index 61a0cb15067e..05543f1cfbde 100644\n>> --- a/arch/arm/Kconfig\n>> +++ b/arch/arm/Kconfig\n>> @@ -782,6 +782,8 @@ source \"arch/arm/mach-netx/Kconfig\"\n>>\n>> source \"arch/arm/mach-nomadik/Kconfig\"\n>>\n>> +source \"arch/arm/mach-npcm/Kconfig\"\n>> +\n>> source \"arch/arm/mach-nspire/Kconfig\"\n>>\n>> source \"arch/arm/plat-omap/Kconfig\"\n>> diff --git a/arch/arm/Makefile b/arch/arm/Makefile\n>> index 47d3a1ab08d2..60ca50c7d762 100644\n>> --- a/arch/arm/Makefile\n>> +++ b/arch/arm/Makefile\n>> @@ -191,6 +191,7 @@ machine-$(CONFIG_ARCH_MEDIATEK) += mediatek\n>> machine-$(CONFIG_ARCH_MXS) += mxs\n>> machine-$(CONFIG_ARCH_NETX) += netx\n>> machine-$(CONFIG_ARCH_NOMADIK) += nomadik\n>> +machine-$(CONFIG_ARCH_NPCM) += npcm\n>> machine-$(CONFIG_ARCH_NSPIRE) += nspire\n>> machine-$(CONFIG_ARCH_OXNAS) += oxnas\n>> machine-$(CONFIG_ARCH_OMAP1) += omap1\n>> diff --git a/arch/arm/mach-npcm/Kconfig b/arch/arm/mach-npcm/Kconfig\n>> new file mode 100644\n>> index 000000000000..d47061855439\n>> --- /dev/null\n>> +++ b/arch/arm/mach-npcm/Kconfig\n>> @@ -0,0 +1,50 @@\n>> +menuconfig ARCH_NPCM\n>> + bool \"Nuvoton NPCM Architecture\"\n>> + select ARCH_REQUIRE_GPIOLIB\n>> + select USE_OF\n>> + select PINCTRL\n>> + select PINCTRL_NPCM7XX\n>> +\n>> +if ARCH_NPCM\n>> +\n>> +comment \"NPCMX50 CPU type\"\n>> +\n>> +config CPU_NPCM750\n>> + depends on ARCH_NPCM && ARCH_MULTI_V7\n>> + bool \"Support for NPCM750 BMC CPU (Poleg)\"\n>> + select CACHE_L2X0\n>> + select CPU_V7\n>> + select ARM_GIC\n>> + select HAVE_SMP\n>> + select SMP\n>> + select SMP_ON_UP\n>> + select HAVE_ARM_SCU\n>> + select HAVE_ARM_TWD if SMP\n>> + select ARM_ERRATA_458693\n>> + select ARM_ERRATA_720789\n>> + select ARM_ERRATA_742231\n>> + select ARM_ERRATA_754322\n>> + select ARM_ERRATA_764369\n>> + select ARM_ERRATA_794072\n>> + select PL310_ERRATA_588369\n>> + select PL310_ERRATA_727915\n>> + select USB_EHCI_ROOT_HUB_TT\n>> + select USB_ARCH_HAS_HCD\n>> + select USB_ARCH_HAS_EHCI\n>> + select USB_EHCI_HCD\n>> + select USB_ARCH_HAS_OHCI\n>> + select USB_OHCI_HCD\n>> + select USB\n>> + select FIQ\n>> + select CPU_USE_DOMAINS\n>> + select GENERIC_CLOCKEVENTS\n>> + select CLKDEV_LOOKUP\n>> + select COMMON_CLK if OF\n>> + select NPCM750_TIMER\n>> + select MFD_SYSCON\n>> + help\n>> + Support for NPCM750 BMC CPU (Poleg).\n>> +\n>> + Nuvoton NPCM750 BMC based on the Cortex A9.\n>> +\n>> +endif\n>> diff --git a/arch/arm/mach-npcm/Makefile b/arch/arm/mach-npcm/Makefile\n>> new file mode 100644\n>> index 000000000000..78416055b854\n>> --- /dev/null\n>> +++ b/arch/arm/mach-npcm/Makefile\n>> @@ -0,0 +1,3 @@\n>> +AFLAGS_headsmp.o += -march=armv7-a\n>> +\n>> +obj-$(CONFIG_CPU_NPCM750) += npcm7xx.o platsmp.o headsmp.o\n>> diff --git a/arch/arm/mach-npcm/headsmp.S b/arch/arm/mach-npcm/headsmp.S\n>> new file mode 100644\n>> index 000000000000..9fccbbd49ed4\n>> --- /dev/null\n>> +++ b/arch/arm/mach-npcm/headsmp.S\n>> @@ -0,0 +1,17 @@\n>> +/*\n>> + * Copyright 2017 Google, Inc.\n>> + *\n>> + * This program is free software; you can redistribute it and/or modify\n>> + * it under the terms of the GNU General Public License version 2 as\n>> + * published by the Free Software Foundation.\n>> + */\n>> +\n>> +#include \n>> +#include \n>> +#include \n>> +\n>> +ENTRY(npcm7xx_secondary_startup)\n>> + safe_svcmode_maskall r0\n>\n> I saw you answered to Florian Fainelli that the BootRom is not\n> starting the secondary CPU in SVC mode. Are you sure? In our\n> engineering npcm7xx revision, Z1, the BootRom indeed started to run it\n> in IRQ mode but we fixed it in the production version, A1, (quite long\n> time ago), I hope you didn't get an EB with Z1 you can check that in\n> BootBlock console print:\n>> ADC CLK is set to 25000000\n>>Last reset was CORST\n>>vgaioen=1 and mux gspi.\n>>A1 <<====== this is what you should see, if you see Z1 we need to replace your EB\n>\n\nNope, on boot it prints:\n\n>EB\n>Board manufacturer: Nuvoton\n\n> CPU CLK is 800000000\n> MC CLK is 800000000\n\n> ADC CLK is set to 25000000\n>Last reset was PORST\n>vgaioen=1 and mux gspi.\n>A1\n>Skip PCI config.\n\nTo reproduce, all you have to do is delete\n\n>> + safe_svcmode_maskall r0\n\nand the kernel will warn that the core is not starting in SVC mode\n\n>> +\n>> + b secondary_startup\n>> +ENDPROC(npcm7xx_secondary_startup)\n>> diff --git a/arch/arm/mach-npcm/npcm7xx.c b/arch/arm/mach-npcm/npcm7xx.c\n>> new file mode 100644\n>> index 000000000000..132e9d587857\n>> --- /dev/null\n>> +++ b/arch/arm/mach-npcm/npcm7xx.c\n>> @@ -0,0 +1,34 @@\n>> +/*\n>> + * Copyright (c) 2017 Nuvoton Technology corporation.\n>> + * Copyright 2017 Google, Inc.\n>> + *\n>> + * This program is free software; you can redistribute it and/or modify\n>> + * it under the terms of the GNU General Public License version 2 as\n>> + * published by the Free Software Foundation.\n>> + */\n>> +\n>> +#include \n>> +#include \n>> +#include \n>> +#include \n>> +#include \n>> +#include \n>> +\n>> +#define NPCM7XX_AUX_VAL (L310_AUX_CTRL_INSTR_PREFETCH | \\\n>> + L310_AUX_CTRL_DATA_PREFETCH | \\\n>> + L310_AUX_CTRL_NS_LOCKDOWN | \\\n>> + L310_AUX_CTRL_CACHE_REPLACE_RR | \\\n>> + L2C_AUX_CTRL_SHARED_OVERRIDE | \\\n>> + L310_AUX_CTRL_FULL_LINE_ZERO)\n>> +\n>> +static const char *const npcm7xx_dt_match[] = {\n>> + \"nuvoton,npcm750\",\n>> + NULL\n>> +};\n>> +\n>> +DT_MACHINE_START(NPCM7XX_DT, \"NPCMX50 Chip family\")\n>> + .atag_offset = 0x100,\n>> + .dt_compat = npcm7xx_dt_match,\n>> + .l2c_aux_val = NPCM7XX_AUX_VAL,\n>> + .l2c_aux_mask = ~NPCM7XX_AUX_VAL,\n>> +MACHINE_END\n>> diff --git a/arch/arm/mach-npcm/platsmp.c b/arch/arm/mach-npcm/platsmp.c\n>> new file mode 100644\n>> index 000000000000..144e3e7ec7e6\n>> --- /dev/null\n>> +++ b/arch/arm/mach-npcm/platsmp.c\n>> @@ -0,0 +1,89 @@\n>> +/*\n>> + * Copyright 2017 Google, Inc.\n>> + *\n>> + * This program is free software; you can redistribute it and/or modify\n>> + * it under the terms of the GNU General Public License version 2 as\n>> + * published by the Free Software Foundation.\n>> + */\n>> +\n>> +#define pr_fmt(fmt) \"PLATSMP: \" fmt\n>> +\n>> +#include \n>> +#include \n>> +#include \n>> +#include \n>> +#include \n>> +#include \n>> +#include \n>> +#include \n>> +#include \n>> +#include \n>> +#include \n>> +#include \n>> +\n>> +#define NPCM7XX_SCRPAD_REG 0x13c\n>> +\n>> +extern void npcm7xx_secondary_startup(void);\n>> +\n>> +static int npcm7xx_smp_boot_secondary(unsigned int cpu,\n>> + struct task_struct *idle)\n>> +{\n>> + struct device_node *gcr_np;\n>> + void __iomem *gcr_base;\n>> + int ret = 0;\n>> +\n>> + gcr_np = of_find_compatible_node(NULL, NULL, \"nuvoton,npcm750-gcr\");\n>> + if (!gcr_np) {\n>> + pr_err(\"no gcr device node\\n\");\n>> + ret = -EFAULT;\n>> + goto out;\n>> + }\n>> + gcr_base = of_iomap(gcr_np, 0);\n>> + if (!gcr_base) {\n>> + pr_err(\"could not iomap gcr at: 0x%llx\\n\", gcr_base);\n>> + ret = -EFAULT;\n>> + goto out;\n>> + }\n>> +\n>> + /* give boot ROM kernel start address. */\n>> + iowrite32(__pa_symbol(npcm7xx_secondary_startup), gcr_base +\n>> + NPCM7XX_SCRPAD_REG);\n>> + /* make sure npcm7xx_secondary_startup is seen by all observers. */\n>> + smp_wmb();\n>> + dsb_sev();\n>> + /* make sure write buffer is drained */\n>> + mb();\n>> +\n>> +out:\n>> + iounmap(gcr_base);\n>> + return ret;\n>> +}\n>> +\n>> +static void __init npcm7xx_smp_prepare_cpus(unsigned int max_cpus)\n>> +{\n>> + struct device_node *scu_np;\n>> + void __iomem *scu_base;\n>> +\n>> + scu_np = of_find_compatible_node(NULL, NULL, \"arm,cortex-a9-scu\");\n>> + if (!scu_np) {\n>> + pr_err(\"no scu device node\\n\");\n>> + return;\n>> + }\n>> + scu_base = of_iomap(scu_np, 0);\n>> + if (!scu_base) {\n>> + pr_err(\"could not iomap scu at: 0x%llx\\n\", scu_base);\n>> + return;\n>> + }\n>> +\n>> + scu_enable(scu_base);\n>> +\n>> +out:\n>> + iounmap(scu_base);\n>> +}\n>> +\n>> +static struct smp_operations npcm7xx_smp_ops __initdata = {\n>> + .smp_prepare_cpus = npcm7xx_smp_prepare_cpus,\n>> + .smp_boot_secondary = npcm7xx_smp_boot_secondary,\n>> +};\n>> +\n>> +CPU_METHOD_OF_DECLARE(npcm7xx_smp, \"nuvoton,npcm7xx-smp\", &npcm7xx_smp_ops);\n>> --\n>> 2.14.1.581.gf28d330327-goog\n>>","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","openbmc@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","openbmc@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org 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(PDT)","MIME-Version":"1.0","In-Reply-To":"","References":"<20170906080751.6773-1-brendanhiggins@google.com>\n\t<20170906080751.6773-2-brendanhiggins@google.com>\n\t","From":"Brendan Higgins ","Date":"Wed, 6 Sep 2017 22:09:05 -0700","Message-ID":"","Subject":"Re: [PATCH v4 1/3] arm: npcm: add basic support for Nuvoton BMCs","To":"Avi Fishman ","Content-Type":"text/plain; charset=\"UTF-8\"","X-BeenThere":"openbmc@lists.ozlabs.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"Development list for OpenBMC ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Mark Rutland ,\n\tdevicetree ,\n\tFlorian Fainelli , tmaimon77@gmail.com,\n\tOpenBMC Maillist ,\n\tRussell King ,\n\tLinux Kernel Mailing List ,\n\tRob Herring , linux-arm-kernel@lists.infradead.org","Errors-To":"openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org","Sender":"\"openbmc\"\n\t"}},{"id":1764602,"web_url":"http://patchwork.ozlabs.org/comment/1764602/","msgid":"","list_archive_url":null,"date":"2017-09-07T09:18:47","subject":"Re: [PATCH v4 1/3] arm: npcm: add basic support for Nuvoton BMCs","submitter":{"id":72291,"url":"http://patchwork.ozlabs.org/api/people/72291/","name":"Tomer Maimon","email":"tmaimon77@gmail.com"},"content":"On 6 September 2017 at 11:07, Brendan Higgins wrote:\n> Adds basic support for the Nuvoton NPCM750 BMC.\n>\n> Signed-off-by: Brendan Higgins \n> ---\n> arch/arm/Kconfig | 2 +\n> arch/arm/Makefile | 1 +\n> arch/arm/mach-npcm/Kconfig | 50 +++++++++++++++++++++++++\n> arch/arm/mach-npcm/Makefile | 3 ++\n> arch/arm/mach-npcm/headsmp.S | 17 +++++++++\n> arch/arm/mach-npcm/npcm7xx.c | 34 +++++++++++++++++\n> arch/arm/mach-npcm/platsmp.c | 89 ++++++++++++++++++++++++++++++++++++++++++++\n> 7 files changed, 196 insertions(+)\n> create mode 100644 arch/arm/mach-npcm/Kconfig\n> create mode 100644 arch/arm/mach-npcm/Makefile\n> create mode 100644 arch/arm/mach-npcm/headsmp.S\n> create mode 100644 arch/arm/mach-npcm/npcm7xx.c\n> create mode 100644 arch/arm/mach-npcm/platsmp.c\n>\n> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig\n> index 61a0cb15067e..05543f1cfbde 100644\n> --- a/arch/arm/Kconfig\n> +++ b/arch/arm/Kconfig\n> @@ -782,6 +782,8 @@ source \"arch/arm/mach-netx/Kconfig\"\n>\n> source \"arch/arm/mach-nomadik/Kconfig\"\n>\n> +source \"arch/arm/mach-npcm/Kconfig\"\n> +\n> source \"arch/arm/mach-nspire/Kconfig\"\n>\n> source \"arch/arm/plat-omap/Kconfig\"\n> diff --git a/arch/arm/Makefile b/arch/arm/Makefile\n> index 47d3a1ab08d2..60ca50c7d762 100644\n> --- a/arch/arm/Makefile\n> +++ b/arch/arm/Makefile\n> @@ -191,6 +191,7 @@ machine-$(CONFIG_ARCH_MEDIATEK) += mediatek\n> machine-$(CONFIG_ARCH_MXS) += mxs\n> machine-$(CONFIG_ARCH_NETX) += netx\n> machine-$(CONFIG_ARCH_NOMADIK) += nomadik\n> +machine-$(CONFIG_ARCH_NPCM) += npcm\n> machine-$(CONFIG_ARCH_NSPIRE) += nspire\n> machine-$(CONFIG_ARCH_OXNAS) += oxnas\n> machine-$(CONFIG_ARCH_OMAP1) += omap1\n> diff --git a/arch/arm/mach-npcm/Kconfig b/arch/arm/mach-npcm/Kconfig\n> new file mode 100644\n> index 000000000000..d47061855439\n> --- /dev/null\n> +++ b/arch/arm/mach-npcm/Kconfig\n> @@ -0,0 +1,50 @@\n> +menuconfig ARCH_NPCM\n> + bool \"Nuvoton NPCM Architecture\"\n> + select ARCH_REQUIRE_GPIOLIB\n> + select USE_OF\n> + select PINCTRL\n> + select PINCTRL_NPCM7XX\n> +\n> +if ARCH_NPCM\n> +\n> +comment \"NPCMX50 CPU type\"\n> +\n> +config CPU_NPCM750\n> + depends on ARCH_NPCM && ARCH_MULTI_V7\n> + bool \"Support for NPCM750 BMC CPU (Poleg)\"\n> + select CACHE_L2X0\n> + select CPU_V7\n> + select ARM_GIC\n> + select HAVE_SMP\n> + select SMP\n> + select SMP_ON_UP\n> + select HAVE_ARM_SCU\n> + select HAVE_ARM_TWD if SMP\n> + select ARM_ERRATA_458693\n> + select ARM_ERRATA_720789\n> + select ARM_ERRATA_742231\n> + select ARM_ERRATA_754322\n> + select ARM_ERRATA_764369\n> + select ARM_ERRATA_794072\n> + select PL310_ERRATA_588369\n> + select PL310_ERRATA_727915\n> + select USB_EHCI_ROOT_HUB_TT\n> + select USB_ARCH_HAS_HCD\n> + select USB_ARCH_HAS_EHCI\n> + select USB_EHCI_HCD\n> + select USB_ARCH_HAS_OHCI\n> + select USB_OHCI_HCD\n> + select USB\n> + select FIQ\n> + select CPU_USE_DOMAINS\n> + select GENERIC_CLOCKEVENTS\n> + select CLKDEV_LOOKUP\n> + select COMMON_CLK if OF\n> + select NPCM750_TIMER\n> + select MFD_SYSCON\n> + help\n> + Support for NPCM750 BMC CPU (Poleg).\n> +\n> + Nuvoton NPCM750 BMC based on the Cortex A9.\n> +\n> +endif\n> diff --git a/arch/arm/mach-npcm/Makefile b/arch/arm/mach-npcm/Makefile\n> new file mode 100644\n> index 000000000000..78416055b854\n> --- /dev/null\n> +++ b/arch/arm/mach-npcm/Makefile\n> @@ -0,0 +1,3 @@\n> +AFLAGS_headsmp.o += -march=armv7-a\n> +\n> +obj-$(CONFIG_CPU_NPCM750) += npcm7xx.o platsmp.o headsmp.o\n> diff --git a/arch/arm/mach-npcm/headsmp.S b/arch/arm/mach-npcm/headsmp.S\n> new file mode 100644\n> index 000000000000..9fccbbd49ed4\n> --- /dev/null\n> +++ b/arch/arm/mach-npcm/headsmp.S\n> @@ -0,0 +1,17 @@\n> +/*\n> + * Copyright 2017 Google, Inc.\n> + *\n> + * This program is free software; you can redistribute it and/or modify\n> + * it under the terms of the GNU General Public License version 2 as\n> + * published by the Free Software Foundation.\n> + */\n> +\n> +#include \n> +#include \n> +#include \n> +\n> +ENTRY(npcm7xx_secondary_startup)\n> + safe_svcmode_maskall r0\n> +\n> + b secondary_startup\n> +ENDPROC(npcm7xx_secondary_startup)\n> diff --git a/arch/arm/mach-npcm/npcm7xx.c b/arch/arm/mach-npcm/npcm7xx.c\n> new file mode 100644\n> index 000000000000..132e9d587857\n> --- /dev/null\n> +++ b/arch/arm/mach-npcm/npcm7xx.c\n> @@ -0,0 +1,34 @@\n> +/*\n> + * Copyright (c) 2017 Nuvoton Technology corporation.\n> + * Copyright 2017 Google, Inc.\n> + *\n> + * This program is free software; you can redistribute it and/or modify\n> + * it under the terms of the GNU General Public License version 2 as\n> + * published by the Free Software Foundation.\n> + */\n> +\n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +\n> +#define NPCM7XX_AUX_VAL (L310_AUX_CTRL_INSTR_PREFETCH | \\\n> + L310_AUX_CTRL_DATA_PREFETCH | \\\n> + L310_AUX_CTRL_NS_LOCKDOWN | \\\n> + L310_AUX_CTRL_CACHE_REPLACE_RR | \\\n> + L2C_AUX_CTRL_SHARED_OVERRIDE | \\\n> + L310_AUX_CTRL_FULL_LINE_ZERO)\n> +\n> +static const char *const npcm7xx_dt_match[] = {\n> + \"nuvoton,npcm750\",\n> + NULL\n> +};\n> +\n> +DT_MACHINE_START(NPCM7XX_DT, \"NPCMX50 Chip family\")\n> + .atag_offset = 0x100,\n> + .dt_compat = npcm7xx_dt_match,\n> + .l2c_aux_val = NPCM7XX_AUX_VAL,\n> + .l2c_aux_mask = ~NPCM7XX_AUX_VAL,\n> +MACHINE_END\n> diff --git a/arch/arm/mach-npcm/platsmp.c b/arch/arm/mach-npcm/platsmp.c\n> new file mode 100644\n> index 000000000000..144e3e7ec7e6\n> --- /dev/null\n> +++ b/arch/arm/mach-npcm/platsmp.c\n> @@ -0,0 +1,89 @@\n> +/*\n> + * Copyright 2017 Google, Inc.\n> + *\n> + * This program is free software; you can redistribute it and/or modify\n> + * it under the terms of the GNU General Public License version 2 as\n> + * published by the Free Software Foundation.\n> + */\n> +\n> +#define pr_fmt(fmt) \"PLATSMP: \" fmt\n> +\n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +\n> +#define NPCM7XX_SCRPAD_REG 0x13c\n> +\n> +extern void npcm7xx_secondary_startup(void);\n> +\n> +static int npcm7xx_smp_boot_secondary(unsigned int cpu,\n> + struct task_struct *idle)\n> +{\n> + struct device_node *gcr_np;\n> + void __iomem *gcr_base;\n> + int ret = 0;\n> +\n> + gcr_np = of_find_compatible_node(NULL, NULL, \"nuvoton,npcm750-gcr\");\n> + if (!gcr_np) {\n> + pr_err(\"no gcr device node\\n\");\n> + ret = -EFAULT;\n> + goto out;\n> + }\n> + gcr_base = of_iomap(gcr_np, 0);\n> + if (!gcr_base) {\n> + pr_err(\"could not iomap gcr at: 0x%llx\\n\", gcr_base);\n> + ret = -EFAULT;\n> + goto out;\n> + }\n> +\n> + /* give boot ROM kernel start address. */\n> + iowrite32(__pa_symbol(npcm7xx_secondary_startup), gcr_base +\n> + NPCM7XX_SCRPAD_REG);\n> + /* make sure npcm7xx_secondary_startup is seen by all observers. */\n> + smp_wmb();\n> + dsb_sev();\n> + /* make sure write buffer is drained */\n> + mb();\n> +\n> +out:\n> + iounmap(gcr_base);\n> + return ret;\n> +}\n> +\n> +static void __init npcm7xx_smp_prepare_cpus(unsigned int max_cpus)\n> +{\n> + struct device_node *scu_np;\n> + void __iomem *scu_base;\n> +\n> + scu_np = of_find_compatible_node(NULL, NULL, \"arm,cortex-a9-scu\");\n> + if (!scu_np) {\n> + pr_err(\"no scu device node\\n\");\n> + return;\n> + }\n> + scu_base = of_iomap(scu_np, 0);\n> + if (!scu_base) {\n> + pr_err(\"could not iomap scu at: 0x%llx\\n\", scu_base);\n> + return;\n> + }\n> +\n> + scu_enable(scu_base);\n> +\n> +out:\n> + iounmap(scu_base);\n> +}\n> +\n> +static struct smp_operations npcm7xx_smp_ops __initdata = {\n> + .smp_prepare_cpus = npcm7xx_smp_prepare_cpus,\n> + .smp_boot_secondary = npcm7xx_smp_boot_secondary,\n> +};\n> +\n> +CPU_METHOD_OF_DECLARE(npcm7xx_smp, \"nuvoton,npcm7xx-smp\", &npcm7xx_smp_ops);\n> --\n> 2.14.1.581.gf28d330327-goog\n>\n\nReviewed-by: Tomer Maimon \nReviewed-by: Avi Fishman \nTested-by: Tomer Maimon \nTested-by: Avi Fishman ","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","openbmc@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","openbmc@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xnvyn4xcnz9sRV\n\tfor ;\n\tThu, 7 Sep 2017 19:18:57 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org 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(PDT)","MIME-Version":"1.0","In-Reply-To":"<20170906080751.6773-2-brendanhiggins@google.com>","References":"<20170906080751.6773-1-brendanhiggins@google.com>\n\t<20170906080751.6773-2-brendanhiggins@google.com>","From":"Tomer Maimon ","Date":"Thu, 7 Sep 2017 12:18:47 +0300","Message-ID":"","Subject":"Re: [PATCH v4 1/3] arm: npcm: add basic support for Nuvoton BMCs","To":"Brendan Higgins ","Content-Type":"text/plain; charset=\"UTF-8\"","X-BeenThere":"openbmc@lists.ozlabs.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"Development list for OpenBMC ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"mark.rutland@arm.com, devicetree@vger.kernel.org, f.fainelli@gmail.com, \n\tavifishman70@gmail.com, openbmc@lists.ozlabs.org, linux@armlinux.org.uk, \n\tlinux-kernel@vger.kernel.org, robh+dt@kernel.org,\n\tlinux-arm-kernel@lists.infradead.org","Errors-To":"openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org","Sender":"\"openbmc\"\n\t"}},{"id":1764777,"web_url":"http://patchwork.ozlabs.org/comment/1764777/","msgid":"","list_archive_url":null,"date":"2017-09-07T15:09:06","subject":"Re: [PATCH v4 1/3] arm: npcm: add basic support for Nuvoton BMCs","submitter":{"id":72311,"url":"http://patchwork.ozlabs.org/api/people/72311/","name":"Avi Fishman","email":"avifishman70@gmail.com"},"content":"On Thu, Sep 7, 2017 at 8:09 AM, Brendan Higgins\n wrote:\n> On Wed, Sep 6, 2017 at 2:04 PM, Avi Fishman wrote:\n>> Sorry for sending again some mailing list rejected it due to HTML\n>> involved (althoug I tried Plain Text), Trying again.\n>>\n>> 2017-09-06 11:07 GMT+03:00 Brendan Higgins :\n>>> Adds basic support for the Nuvoton NPCM750 BMC.\n>>>\n>>> Signed-off-by: Brendan Higgins \n>>> ---\n>>> arch/arm/Kconfig | 2 +\n>>> arch/arm/Makefile | 1 +\n>>> arch/arm/mach-npcm/Kconfig | 50 +++++++++++++++++++++++++\n>>> arch/arm/mach-npcm/Makefile | 3 ++\n>>> arch/arm/mach-npcm/headsmp.S | 17 +++++++++\n>>> arch/arm/mach-npcm/npcm7xx.c | 34 +++++++++++++++++\n>>> arch/arm/mach-npcm/platsmp.c | 89 ++++++++++++++++++++++++++++++++++++++++++++\n>>> 7 files changed, 196 insertions(+)\n>>> create mode 100644 arch/arm/mach-npcm/Kconfig\n>>> create mode 100644 arch/arm/mach-npcm/Makefile\n>>> create mode 100644 arch/arm/mach-npcm/headsmp.S\n>>> create mode 100644 arch/arm/mach-npcm/npcm7xx.c\n>>> create mode 100644 arch/arm/mach-npcm/platsmp.c\n>>>\n>>> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig\n>>> index 61a0cb15067e..05543f1cfbde 100644\n>>> --- a/arch/arm/Kconfig\n>>> +++ b/arch/arm/Kconfig\n>>> @@ -782,6 +782,8 @@ source \"arch/arm/mach-netx/Kconfig\"\n>>>\n>>> source \"arch/arm/mach-nomadik/Kconfig\"\n>>>\n>>> +source \"arch/arm/mach-npcm/Kconfig\"\n>>> +\n>>> source \"arch/arm/mach-nspire/Kconfig\"\n>>>\n>>> source \"arch/arm/plat-omap/Kconfig\"\n>>> diff --git a/arch/arm/Makefile b/arch/arm/Makefile\n>>> index 47d3a1ab08d2..60ca50c7d762 100644\n>>> --- a/arch/arm/Makefile\n>>> +++ b/arch/arm/Makefile\n>>> @@ -191,6 +191,7 @@ machine-$(CONFIG_ARCH_MEDIATEK) += mediatek\n>>> machine-$(CONFIG_ARCH_MXS) += mxs\n>>> machine-$(CONFIG_ARCH_NETX) += netx\n>>> machine-$(CONFIG_ARCH_NOMADIK) += nomadik\n>>> +machine-$(CONFIG_ARCH_NPCM) += npcm\n>>> machine-$(CONFIG_ARCH_NSPIRE) += nspire\n>>> machine-$(CONFIG_ARCH_OXNAS) += oxnas\n>>> machine-$(CONFIG_ARCH_OMAP1) += omap1\n>>> diff --git a/arch/arm/mach-npcm/Kconfig b/arch/arm/mach-npcm/Kconfig\n>>> new file mode 100644\n>>> index 000000000000..d47061855439\n>>> --- /dev/null\n>>> +++ b/arch/arm/mach-npcm/Kconfig\n>>> @@ -0,0 +1,50 @@\n>>> +menuconfig ARCH_NPCM\n>>> + bool \"Nuvoton NPCM Architecture\"\n>>> + select ARCH_REQUIRE_GPIOLIB\n>>> + select USE_OF\n>>> + select PINCTRL\n>>> + select PINCTRL_NPCM7XX\n>>> +\n>>> +if ARCH_NPCM\n>>> +\n>>> +comment \"NPCMX50 CPU type\"\n>>> +\n>>> +config CPU_NPCM750\n>>> + depends on ARCH_NPCM && ARCH_MULTI_V7\n>>> + bool \"Support for NPCM750 BMC CPU (Poleg)\"\n>>> + select CACHE_L2X0\n>>> + select CPU_V7\n>>> + select ARM_GIC\n>>> + select HAVE_SMP\n>>> + select SMP\n>>> + select SMP_ON_UP\n>>> + select HAVE_ARM_SCU\n>>> + select HAVE_ARM_TWD if SMP\n>>> + select ARM_ERRATA_458693\n>>> + select ARM_ERRATA_720789\n>>> + select ARM_ERRATA_742231\n>>> + select ARM_ERRATA_754322\n>>> + select ARM_ERRATA_764369\n>>> + select ARM_ERRATA_794072\n>>> + select PL310_ERRATA_588369\n>>> + select PL310_ERRATA_727915\n>>> + select USB_EHCI_ROOT_HUB_TT\n>>> + select USB_ARCH_HAS_HCD\n>>> + select USB_ARCH_HAS_EHCI\n>>> + select USB_EHCI_HCD\n>>> + select USB_ARCH_HAS_OHCI\n>>> + select USB_OHCI_HCD\n>>> + select USB\n>>> + select FIQ\n>>> + select CPU_USE_DOMAINS\n>>> + select GENERIC_CLOCKEVENTS\n>>> + select CLKDEV_LOOKUP\n>>> + select COMMON_CLK if OF\n>>> + select NPCM750_TIMER\n>>> + select MFD_SYSCON\n>>> + help\n>>> + Support for NPCM750 BMC CPU (Poleg).\n>>> +\n>>> + Nuvoton NPCM750 BMC based on the Cortex A9.\n>>> +\n>>> +endif\n>>> diff --git a/arch/arm/mach-npcm/Makefile b/arch/arm/mach-npcm/Makefile\n>>> new file mode 100644\n>>> index 000000000000..78416055b854\n>>> --- /dev/null\n>>> +++ b/arch/arm/mach-npcm/Makefile\n>>> @@ -0,0 +1,3 @@\n>>> +AFLAGS_headsmp.o += -march=armv7-a\n>>> +\n>>> +obj-$(CONFIG_CPU_NPCM750) += npcm7xx.o platsmp.o headsmp.o\n>>> diff --git a/arch/arm/mach-npcm/headsmp.S b/arch/arm/mach-npcm/headsmp.S\n>>> new file mode 100644\n>>> index 000000000000..9fccbbd49ed4\n>>> --- /dev/null\n>>> +++ b/arch/arm/mach-npcm/headsmp.S\n>>> @@ -0,0 +1,17 @@\n>>> +/*\n>>> + * Copyright 2017 Google, Inc.\n>>> + *\n>>> + * This program is free software; you can redistribute it and/or modify\n>>> + * it under the terms of the GNU General Public License version 2 as\n>>> + * published by the Free Software Foundation.\n>>> + */\n>>> +\n>>> +#include \n>>> +#include \n>>> +#include \n>>> +\n>>> +ENTRY(npcm7xx_secondary_startup)\n>>> + safe_svcmode_maskall r0\n>>\n>> I saw you answered to Florian Fainelli that the BootRom is not\n>> starting the secondary CPU in SVC mode. Are you sure? In our\n>> engineering npcm7xx revision, Z1, the BootRom indeed started to run it\n>> in IRQ mode but we fixed it in the production version, A1, (quite long\n>> time ago), I hope you didn't get an EB with Z1 you can check that in\n>> BootBlock console print:\n>>> ADC CLK is set to 25000000\n>>>Last reset was CORST\n>>>vgaioen=1 and mux gspi.\n>>>A1 <<====== this is what you should see, if you see Z1 we need to replace your EB\n>>\n>\n> Nope, on boot it prints:\n>\n>>EB\n>>Board manufacturer: Nuvoton\n>\n>> CPU CLK is 800000000\n>> MC CLK is 800000000\n>\n>> ADC CLK is set to 25000000\n>>Last reset was PORST\n>>vgaioen=1 and mux gspi.\n>>A1\n>>Skip PCI config.\n>\n> To reproduce, all you have to do is delete\n>\n>>> + safe_svcmode_maskall r0\n>\n> and the kernel will warn that the core is not starting in SVC mode\n>\n\nOK, Tomer also confirmed it, his kernel printed this:\n CPU: WARNING: CPU(s) started in wrong/inconsistent modes (primary\nCPU mode 0x13)\n CPU: This may indicate a broken bootloader or firmware.\nIt appears that in kernel CPU0 starts at SVC mode (0x13) and CPU1\nstarts at SYS mode (0x1F) and the kernel doesn't like that, so leave\nit as is.\n\n>>> +\n>>> + b secondary_startup\n>>> +ENDPROC(npcm7xx_secondary_startup)\n>>> diff --git a/arch/arm/mach-npcm/npcm7xx.c b/arch/arm/mach-npcm/npcm7xx.c\n>>> new file mode 100644\n>>> index 000000000000..132e9d587857\n>>> --- /dev/null\n>>> +++ b/arch/arm/mach-npcm/npcm7xx.c\n>>> @@ -0,0 +1,34 @@\n>>> +/*\n>>> + * Copyright (c) 2017 Nuvoton Technology corporation.\n>>> + * Copyright 2017 Google, Inc.\n>>> + *\n>>> + * This program is free software; you can redistribute it and/or modify\n>>> + * it under the terms of the GNU General Public License version 2 as\n>>> + * published by the Free Software Foundation.\n>>> + */\n>>> +\n>>> +#include \n>>> +#include \n>>> +#include \n>>> +#include \n>>> +#include \n>>> +#include \n>>> +\n>>> +#define NPCM7XX_AUX_VAL (L310_AUX_CTRL_INSTR_PREFETCH | \\\n>>> + L310_AUX_CTRL_DATA_PREFETCH | \\\n>>> + L310_AUX_CTRL_NS_LOCKDOWN | \\\n>>> + L310_AUX_CTRL_CACHE_REPLACE_RR | \\\n>>> + L2C_AUX_CTRL_SHARED_OVERRIDE | \\\n>>> + L310_AUX_CTRL_FULL_LINE_ZERO)\n>>> +\n>>> +static const char *const npcm7xx_dt_match[] = {\n>>> + \"nuvoton,npcm750\",\n>>> + NULL\n>>> +};\n>>> +\n>>> +DT_MACHINE_START(NPCM7XX_DT, \"NPCMX50 Chip family\")\n>>> + .atag_offset = 0x100,\n>>> + .dt_compat = npcm7xx_dt_match,\n>>> + .l2c_aux_val = NPCM7XX_AUX_VAL,\n>>> + .l2c_aux_mask = ~NPCM7XX_AUX_VAL,\n>>> +MACHINE_END\n>>> diff --git a/arch/arm/mach-npcm/platsmp.c b/arch/arm/mach-npcm/platsmp.c\n>>> new file mode 100644\n>>> index 000000000000..144e3e7ec7e6\n>>> --- /dev/null\n>>> +++ b/arch/arm/mach-npcm/platsmp.c\n>>> @@ -0,0 +1,89 @@\n>>> +/*\n>>> + * Copyright 2017 Google, Inc.\n>>> + *\n>>> + * This program is free software; you can redistribute it and/or modify\n>>> + * it under the terms of the GNU General Public License version 2 as\n>>> + * published by the Free Software Foundation.\n>>> + */\n>>> +\n>>> +#define pr_fmt(fmt) \"PLATSMP: \" fmt\n>>> +\n>>> +#include \n>>> +#include \n>>> +#include \n>>> +#include \n>>> +#include \n>>> +#include \n>>> +#include \n>>> +#include \n>>> +#include \n>>> +#include \n>>> +#include \n>>> +#include \n>>> +\n>>> +#define NPCM7XX_SCRPAD_REG 0x13c\n>>> +\n>>> +extern void npcm7xx_secondary_startup(void);\n>>> +\n>>> +static int npcm7xx_smp_boot_secondary(unsigned int cpu,\n>>> + struct task_struct *idle)\n>>> +{\n>>> + struct device_node *gcr_np;\n>>> + void __iomem *gcr_base;\n>>> + int ret = 0;\n>>> +\n>>> + gcr_np = of_find_compatible_node(NULL, NULL, \"nuvoton,npcm750-gcr\");\n>>> + if (!gcr_np) {\n>>> + pr_err(\"no gcr device node\\n\");\n>>> + ret = -EFAULT;\n>>> + goto out;\n>>> + }\n>>> + gcr_base = of_iomap(gcr_np, 0);\n>>> + if (!gcr_base) {\n>>> + pr_err(\"could not iomap gcr at: 0x%llx\\n\", gcr_base);\n>>> + ret = -EFAULT;\n>>> + goto out;\n>>> + }\n>>> +\n>>> + /* give boot ROM kernel start address. */\n>>> + iowrite32(__pa_symbol(npcm7xx_secondary_startup), gcr_base +\n>>> + NPCM7XX_SCRPAD_REG);\n>>> + /* make sure npcm7xx_secondary_startup is seen by all observers. */\n>>> + smp_wmb();\n>>> + dsb_sev();\n>>> + /* make sure write buffer is drained */\n>>> + mb();\n>>> +\n>>> +out:\n>>> + iounmap(gcr_base);\n>>> + return ret;\n>>> +}\n>>> +\n>>> +static void __init npcm7xx_smp_prepare_cpus(unsigned int max_cpus)\n>>> +{\n>>> + struct device_node *scu_np;\n>>> + void __iomem *scu_base;\n>>> +\n>>> + scu_np = of_find_compatible_node(NULL, NULL, \"arm,cortex-a9-scu\");\n>>> + if (!scu_np) {\n>>> + pr_err(\"no scu device node\\n\");\n>>> + return;\n>>> + }\n>>> + scu_base = of_iomap(scu_np, 0);\n>>> + if (!scu_base) {\n>>> + pr_err(\"could not iomap scu at: 0x%llx\\n\", scu_base);\n>>> + return;\n>>> + }\n>>> +\n>>> + scu_enable(scu_base);\n>>> +\n>>> +out:\n>>> + iounmap(scu_base);\n>>> +}\n>>> +\n>>> +static struct smp_operations npcm7xx_smp_ops __initdata = {\n>>> + .smp_prepare_cpus = npcm7xx_smp_prepare_cpus,\n>>> + .smp_boot_secondary = npcm7xx_smp_boot_secondary,\n>>> +};\n>>> +\n>>> +CPU_METHOD_OF_DECLARE(npcm7xx_smp, \"nuvoton,npcm7xx-smp\", &npcm7xx_smp_ops);\n>>> --\n>>> 2.14.1.581.gf28d330327-goog\n>>>","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","openbmc@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","openbmc@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xp3lM2GVRz9t2v\n\tfor ;\n\tFri, 8 Sep 2017 01:09:35 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xp3lM10ryzDqXy\n\tfor ;\n\tFri, 8 Sep 2017 01:09:35 +1000 (AEST)","from mail-oi0-x242.google.com (mail-oi0-x242.google.com\n\t[IPv6:2607:f8b0:4003:c06::242])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xp3ks6xkyzDrXT\n\tfor ; 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\n\tThu, 07 Sep 2017 08:09:07 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"","References":"<20170906080751.6773-1-brendanhiggins@google.com>\n\t<20170906080751.6773-2-brendanhiggins@google.com>\n\t\n\t","From":"Avi Fishman ","Date":"Thu, 7 Sep 2017 18:09:06 +0300","Message-ID":"","Subject":"Re: [PATCH v4 1/3] arm: npcm: add basic support for Nuvoton BMCs","To":"Brendan Higgins ","Content-Type":"text/plain; charset=\"UTF-8\"","X-BeenThere":"openbmc@lists.ozlabs.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"Development list for OpenBMC ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Mark Rutland ,\n\tdevicetree ,\n\tFlorian Fainelli , tmaimon77@gmail.com,\n\tOpenBMC Maillist ,\n\tRussell King ,\n\tLinux Kernel Mailing List ,\n\tRob Herring , linux-arm-kernel@lists.infradead.org","Errors-To":"openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org","Sender":"\"openbmc\"\n\t"}}]