[{"id":1763843,"web_url":"http://patchwork.ozlabs.org/comment/1763843/","msgid":"","date":"2017-09-06T06:58:31","subject":"Re: [PATCH v2 2/2] powerpc/powernv/npu: Don't explicitly flush nmmu\n\ttlb","submitter":{"id":67555,"url":"http://patchwork.ozlabs.org/api/people/67555/","name":"Frederic Barrat","email":"fbarrat@linux.vnet.ibm.com"},"content":"Le 06/09/2017 à 03:49, Alistair Popple a écrit :\n> The nest mmu required an explicit flush as a tlbi would not flush it in the\n> same way as the core. However an alternate firmware fix exists which should\n> eliminate the need for this flush, so instead add a device-tree property\n> (ibm,nmmu-flush) on the NVLink2 PHB to enable it only if required.\n> \n> Signed-off-by: Alistair Popple \n> ---\n\nFWIW,\nReviewed-by: Frederic Barrat \n\n\n> Changes for v2:\n> - Use mm_context_add_copro()/mm_context_remove_copro() instead\n> of inc_mm_active_cpus()/dec_mm_active_cpus()\n> \n> arch/powerpc/platforms/powernv/npu-dma.c | 28 +++++++++++++++++++++++-----\n> arch/powerpc/platforms/powernv/pci.h | 3 +++\n> 2 files changed, 26 insertions(+), 5 deletions(-)\n> \n> diff --git a/arch/powerpc/platforms/powernv/npu-dma.c b/arch/powerpc/platforms/powernv/npu-dma.c\n> index 2fff9a65..f6cbc1a 100644\n> --- a/arch/powerpc/platforms/powernv/npu-dma.c\n> +++ b/arch/powerpc/platforms/powernv/npu-dma.c\n> @@ -395,6 +395,7 @@ struct npu_context {\n> \tstruct pci_dev *npdev[NV_MAX_NPUS][NV_MAX_LINKS];\n> \tstruct mmu_notifier mn;\n> \tstruct kref kref;\n> +\tbool nmmu_flush;\n> \n> \t/* Callback to stop translation requests on a given GPU */\n> \tstruct npu_context *(*release_cb)(struct npu_context *, void *);\n> @@ -545,11 +546,13 @@ static void mmio_invalidate(struct npu_context *npu_context, int va,\n> \tstruct mmio_atsd_reg mmio_atsd_reg[NV_MAX_NPUS];\n> \tunsigned long pid = npu_context->mm->context.id;\n> \n> -\t/*\n> -\t * Unfortunately the nest mmu does not support flushing specific\n> -\t * addresses so we have to flush the whole mm.\n> -\t */\n> -\tflush_all_mm(npu_context->mm);\n> +\tif (npu_context->nmmu_flush)\n> +\t\t/*\n> +\t\t * Unfortunately the nest mmu does not support flushing specific\n> +\t\t * addresses so we have to flush the whole mm once before\n> +\t\t * shooting down the GPU translation.\n> +\t\t */\n> +\t\tflush_all_mm(npu_context->mm);\n> \n> \t/*\n> \t * Loop over all the NPUs this process is active on and launch\n> @@ -722,6 +725,16 @@ struct npu_context *pnv_npu2_init_context(struct pci_dev *gpdev,\n> \t\treturn ERR_PTR(-ENODEV);\n> \tnpu_context->npdev[npu->index][nvlink_index] = npdev;\n> \n> +\tif (!nphb->npu.nmmu_flush) {\n> +\t\t/*\n> +\t\t * If we're not explicitly flushing ourselves we need to mark\n> +\t\t * the thread for global flushes\n> +\t\t */\n> +\t\tnpu_context->nmmu_flush = false;\n> +\t\tmm_context_add_copro(mm);\n> +\t} else\n> +\t\tnpu_context->nmmu_flush = true;\n> +\n> \treturn npu_context;\n> }\n> EXPORT_SYMBOL(pnv_npu2_init_context);\n> @@ -731,6 +744,9 @@ static void pnv_npu2_release_context(struct kref *kref)\n> \tstruct npu_context *npu_context =\n> \t\tcontainer_of(kref, struct npu_context, kref);\n> \n> +\tif (!npu_context->nmmu_flush)\n> +\t\tmm_context_remove_copro(npu_context->mm);\n> +\n> \tnpu_context->mm->context.npu_context = NULL;\n> \tmmu_notifier_unregister(&npu_context->mn,\n> \t\t\t\tnpu_context->mm);\n> @@ -819,6 +835,8 @@ int pnv_npu2_init(struct pnv_phb *phb)\n> \tstatic int npu_index;\n> \tuint64_t rc = 0;\n> \n> +\tphb->npu.nmmu_flush =\n> +\t\tof_property_read_bool(phb->hose->dn, \"ibm,nmmu-flush\");\n> \tfor_each_child_of_node(phb->hose->dn, dn) {\n> \t\tgpdev = pnv_pci_get_gpu_dev(get_pci_dev(dn));\n> \t\tif (gpdev) {\n> diff --git a/arch/powerpc/platforms/powernv/pci.h b/arch/powerpc/platforms/powernv/pci.h\n> index a95273c..22025c6 100644\n> --- a/arch/powerpc/platforms/powernv/pci.h\n> +++ b/arch/powerpc/platforms/powernv/pci.h\n> @@ -187,6 +187,9 @@ struct pnv_phb {\n> \n> \t\t/* Bitmask for MMIO register usage */\n> \t\tunsigned long mmio_atsd_usage;\n> +\n> +\t\t/* Do we need to explicitly flush the nest mmu? */\n> +\t\tbool nmmu_flush;\n> \t} npu;\n> \n> #ifdef CONFIG_CXL_BASE\n>","headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xnDwm4PSbz9sNd\n\tfor ;\n\tWed, 6 Sep 2017 16:59:52 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xnDwm3S1FzDrVk\n\tfor ;\n\tWed, 6 Sep 2017 16:59:52 +1000 (AEST)","from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com\n\t[148.163.158.5])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xnDvM6HV2zDqZ7\n\tfor ;\n\tWed, 6 Sep 2017 16:58:39 +1000 (AEST)","from pps.filterd (m0098419.ppops.net [127.0.0.1])\n\tby mx0b-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv866trUI056095\n\tfor ; Wed, 6 Sep 2017 02:58:37 -0400","from e06smtp10.uk.ibm.com (e06smtp10.uk.ibm.com [195.75.94.106])\n\tby mx0b-001b2d01.pphosted.com with ESMTP id 2ctc018r7w-1\n\t(version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT)\n\tfor ; Wed, 06 Sep 2017 02:58:37 -0400","from localhost\n\tby e06smtp10.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! 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Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"<1504662540-27527-2-git-send-email-alistair@popple.id.au>","Content-Type":"text/plain; charset=utf-8; format=flowed","Content-Language":"fr","Content-Transfer-Encoding":"8bit","X-TM-AS-GCONF":"00","x-cbid":"17090606-0040-0000-0000-000003D5EC2F","X-IBM-AV-DETECTION":"SAVI=unused REMOTE=unused XFE=unused","x-cbparentid":"17090606-0041-0000-0000-000025D6727F","Message-Id":"","X-Proofpoint-Virus-Version":"vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-09-06_02:, , signatures=0","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n\tspamscore=0 suspectscore=0\n\tmalwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam\n\tadjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000\n\tdefinitions=main-1709060093","X-BeenThere":"linuxppc-dev@lists.ozlabs.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"Linux on PowerPC Developers Mail List\n\t","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"andrew.donnellan@au1.ibm.com, arbab@linux.vnet.ibm.com","Errors-To":"linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org","Sender":"\"Linuxppc-dev\"\n\t"}},{"id":1765226,"web_url":"http://patchwork.ozlabs.org/comment/1765226/","msgid":"<201709081856.2Nn5liQZ%fengguang.wu@intel.com>","date":"2017-09-08T10:23:13","subject":"Re: [PATCH v2 2/2] powerpc/powernv/npu: Don't explicitly flush nmmu\n\ttlb","submitter":{"id":67315,"url":"http://patchwork.ozlabs.org/api/people/67315/","name":"kernel test robot","email":"lkp@intel.com"},"content":"Hi Alistair,\n\n[auto build test ERROR on powerpc/next]\n[also build test ERROR on next-20170907]\n[cannot apply to v4.13]\n[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]\n\nurl: https://github.com/0day-ci/linux/commits/Alistair-Popple/powerpc-npu-Use-flush_all_mm-instead-of-flush_tlb_mm/20170908-080828\nbase: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next\nconfig: powerpc-allmodconfig (attached as .config)\ncompiler: powerpc64-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705\nreproduce:\n wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross\n chmod +x ~/bin/make.cross\n # save the attached .config to linux build tree\n make.cross ARCH=powerpc \n\nAll errors (new ones prefixed by >>):\n\n arch/powerpc/platforms/powernv/npu-dma.c: In function 'mmio_invalidate':\n arch/powerpc/platforms/powernv/npu-dma.c:555:3: error: implicit declaration of function 'flush_all_mm' [-Werror=implicit-function-declaration]\n flush_all_mm(npu_context->mm);\n ^~~~~~~~~~~~\n arch/powerpc/platforms/powernv/npu-dma.c: In function 'pnv_npu2_init_context':\n>> arch/powerpc/platforms/powernv/npu-dma.c:744:3: error: implicit declaration of function 'mm_context_add_copro' [-Werror=implicit-function-declaration]\n mm_context_add_copro(mm);\n ^~~~~~~~~~~~~~~~~~~~\n arch/powerpc/platforms/powernv/npu-dma.c: In function 'pnv_npu2_release_context':\n>> arch/powerpc/platforms/powernv/npu-dma.c:758:3: error: implicit declaration of function 'mm_context_remove_copro' [-Werror=implicit-function-declaration]\n mm_context_remove_copro(npu_context->mm);\n ^~~~~~~~~~~~~~~~~~~~~~~\n cc1: some warnings being treated as errors\n\nvim +/mm_context_add_copro +744 arch/powerpc/platforms/powernv/npu-dma.c\n\n 534\t\n 535\t/*\n 536\t * Invalidate either a single address or an entire PID depending on\n 537\t * the value of va.\n 538\t */\n 539\tstatic void mmio_invalidate(struct npu_context *npu_context, int va,\n 540\t\t\t\tunsigned long address, bool flush)\n 541\t{\n 542\t\tint i, j;\n 543\t\tstruct npu *npu;\n 544\t\tstruct pnv_phb *nphb;\n 545\t\tstruct pci_dev *npdev;\n 546\t\tstruct mmio_atsd_reg mmio_atsd_reg[NV_MAX_NPUS];\n 547\t\tunsigned long pid = npu_context->mm->context.id;\n 548\t\n 549\t\tif (npu_context->nmmu_flush)\n 550\t\t\t/*\n 551\t\t\t * Unfortunately the nest mmu does not support flushing specific\n 552\t\t\t * addresses so we have to flush the whole mm once before\n 553\t\t\t * shooting down the GPU translation.\n 554\t\t\t */\n > 555\t\t\tflush_all_mm(npu_context->mm);\n 556\t\n 557\t\t/*\n 558\t\t * Loop over all the NPUs this process is active on and launch\n 559\t\t * an invalidate.\n 560\t\t */\n 561\t\tfor (i = 0; i <= max_npu2_index; i++) {\n 562\t\t\tmmio_atsd_reg[i].reg = -1;\n 563\t\t\tfor (j = 0; j < NV_MAX_LINKS; j++) {\n 564\t\t\t\tnpdev = npu_context->npdev[i][j];\n 565\t\t\t\tif (!npdev)\n 566\t\t\t\t\tcontinue;\n 567\t\n 568\t\t\t\tnphb = pci_bus_to_host(npdev->bus)->private_data;\n 569\t\t\t\tnpu = &nphb->npu;\n 570\t\t\t\tmmio_atsd_reg[i].npu = npu;\n 571\t\n 572\t\t\t\tif (va)\n 573\t\t\t\t\tmmio_atsd_reg[i].reg =\n 574\t\t\t\t\t\tmmio_invalidate_va(npu, address, pid,\n 575\t\t\t\t\t\t\t\tflush);\n 576\t\t\t\telse\n 577\t\t\t\t\tmmio_atsd_reg[i].reg =\n 578\t\t\t\t\t\tmmio_invalidate_pid(npu, pid, flush);\n 579\t\n 580\t\t\t\t/*\n 581\t\t\t\t * The NPU hardware forwards the shootdown to all GPUs\n 582\t\t\t\t * so we only have to launch one shootdown per NPU.\n 583\t\t\t\t */\n 584\t\t\t\tbreak;\n 585\t\t\t}\n 586\t\t}\n 587\t\n 588\t\tmmio_invalidate_wait(mmio_atsd_reg, flush);\n 589\t\tif (flush)\n 590\t\t\t/* Wait for the flush to complete */\n 591\t\t\tmmio_invalidate_wait(mmio_atsd_reg, false);\n 592\t}\n 593\t\n 594\tstatic void pnv_npu2_mn_release(struct mmu_notifier *mn,\n 595\t\t\t\t\tstruct mm_struct *mm)\n 596\t{\n 597\t\tstruct npu_context *npu_context = mn_to_npu_context(mn);\n 598\t\n 599\t\t/* Call into device driver to stop requests to the NMMU */\n 600\t\tif (npu_context->release_cb)\n 601\t\t\tnpu_context->release_cb(npu_context, npu_context->priv);\n 602\t\n 603\t\t/*\n 604\t\t * There should be no more translation requests for this PID, but we\n 605\t\t * need to ensure any entries for it are removed from the TLB.\n 606\t\t */\n 607\t\tmmio_invalidate(npu_context, 0, 0, true);\n 608\t}\n 609\t\n 610\tstatic void pnv_npu2_mn_change_pte(struct mmu_notifier *mn,\n 611\t\t\t\t\tstruct mm_struct *mm,\n 612\t\t\t\t\tunsigned long address,\n 613\t\t\t\t\tpte_t pte)\n 614\t{\n 615\t\tstruct npu_context *npu_context = mn_to_npu_context(mn);\n 616\t\n 617\t\tmmio_invalidate(npu_context, 1, address, true);\n 618\t}\n 619\t\n 620\tstatic void pnv_npu2_mn_invalidate_page(struct mmu_notifier *mn,\n 621\t\t\t\t\t\tstruct mm_struct *mm,\n 622\t\t\t\t\t\tunsigned long address)\n 623\t{\n 624\t\tstruct npu_context *npu_context = mn_to_npu_context(mn);\n 625\t\n 626\t\tmmio_invalidate(npu_context, 1, address, true);\n 627\t}\n 628\t\n 629\tstatic void pnv_npu2_mn_invalidate_range(struct mmu_notifier *mn,\n 630\t\t\t\t\t\tstruct mm_struct *mm,\n 631\t\t\t\t\t\tunsigned long start, unsigned long end)\n 632\t{\n 633\t\tstruct npu_context *npu_context = mn_to_npu_context(mn);\n 634\t\tunsigned long address;\n 635\t\n 636\t\tfor (address = start; address < end; address += PAGE_SIZE)\n 637\t\t\tmmio_invalidate(npu_context, 1, address, false);\n 638\t\n 639\t\t/* Do the flush only on the final addess == end */\n 640\t\tmmio_invalidate(npu_context, 1, address, true);\n 641\t}\n 642\t\n 643\tstatic const struct mmu_notifier_ops nv_nmmu_notifier_ops = {\n 644\t\t.release = pnv_npu2_mn_release,\n 645\t\t.change_pte = pnv_npu2_mn_change_pte,\n 646\t\t.invalidate_page = pnv_npu2_mn_invalidate_page,\n 647\t\t.invalidate_range = pnv_npu2_mn_invalidate_range,\n 648\t};\n 649\t\n 650\t/*\n 651\t * Call into OPAL to setup the nmmu context for the current task in\n 652\t * the NPU. This must be called to setup the context tables before the\n 653\t * GPU issues ATRs. pdev should be a pointed to PCIe GPU device.\n 654\t *\n 655\t * A release callback should be registered to allow a device driver to\n 656\t * be notified that it should not launch any new translation requests\n 657\t * as the final TLB invalidate is about to occur.\n 658\t *\n 659\t * Returns an error if there no contexts are currently available or a\n 660\t * npu_context which should be passed to pnv_npu2_handle_fault().\n 661\t *\n 662\t * mmap_sem must be held in write mode.\n 663\t */\n 664\tstruct npu_context *pnv_npu2_init_context(struct pci_dev *gpdev,\n 665\t\t\t\tunsigned long flags,\n 666\t\t\t\tstruct npu_context *(*cb)(struct npu_context *, void *),\n 667\t\t\t\tvoid *priv)\n 668\t{\n 669\t\tint rc;\n 670\t\tu32 nvlink_index;\n 671\t\tstruct device_node *nvlink_dn;\n 672\t\tstruct mm_struct *mm = current->mm;\n 673\t\tstruct pnv_phb *nphb;\n 674\t\tstruct npu *npu;\n 675\t\tstruct npu_context *npu_context;\n 676\t\n 677\t\t/*\n 678\t\t * At present we don't support GPUs connected to multiple NPUs and I'm\n 679\t\t * not sure the hardware does either.\n 680\t\t */\n 681\t\tstruct pci_dev *npdev = pnv_pci_get_npu_dev(gpdev, 0);\n 682\t\n 683\t\tif (!firmware_has_feature(FW_FEATURE_OPAL))\n 684\t\t\treturn ERR_PTR(-ENODEV);\n 685\t\n 686\t\tif (!npdev)\n 687\t\t\t/* No nvlink associated with this GPU device */\n 688\t\t\treturn ERR_PTR(-ENODEV);\n 689\t\n 690\t\tif (!mm || mm->context.id == 0) {\n 691\t\t\t/*\n 692\t\t\t * Kernel thread contexts are not supported and context id 0 is\n 693\t\t\t * reserved on the GPU.\n 694\t\t\t */\n 695\t\t\treturn ERR_PTR(-EINVAL);\n 696\t\t}\n 697\t\n 698\t\tnphb = pci_bus_to_host(npdev->bus)->private_data;\n 699\t\tnpu = &nphb->npu;\n 700\t\n 701\t\t/*\n 702\t\t * Setup the NPU context table for a particular GPU. These need to be\n 703\t\t * per-GPU as we need the tables to filter ATSDs when there are no\n 704\t\t * active contexts on a particular GPU.\n 705\t\t */\n 706\t\trc = opal_npu_init_context(nphb->opal_id, mm->context.id, flags,\n 707\t\t\t\t\tPCI_DEVID(gpdev->bus->number, gpdev->devfn));\n 708\t\tif (rc < 0)\n 709\t\t\treturn ERR_PTR(-ENOSPC);\n 710\t\n 711\t\t/*\n 712\t\t * We store the npu pci device so we can more easily get at the\n 713\t\t * associated npus.\n 714\t\t */\n 715\t\tnpu_context = mm->context.npu_context;\n 716\t\tif (!npu_context) {\n 717\t\t\tnpu_context = kzalloc(sizeof(struct npu_context), GFP_KERNEL);\n 718\t\t\tif (!npu_context)\n 719\t\t\t\treturn ERR_PTR(-ENOMEM);\n 720\t\n 721\t\t\tmm->context.npu_context = npu_context;\n 722\t\t\tnpu_context->mm = mm;\n 723\t\t\tnpu_context->mn.ops = &nv_nmmu_notifier_ops;\n 724\t\t\t__mmu_notifier_register(&npu_context->mn, mm);\n 725\t\t\tkref_init(&npu_context->kref);\n 726\t\t} else {\n 727\t\t\tkref_get(&npu_context->kref);\n 728\t\t}\n 729\t\n 730\t\tnpu_context->release_cb = cb;\n 731\t\tnpu_context->priv = priv;\n 732\t\tnvlink_dn = of_parse_phandle(npdev->dev.of_node, \"ibm,nvlink\", 0);\n 733\t\tif (WARN_ON(of_property_read_u32(nvlink_dn, \"ibm,npu-link-index\",\n 734\t\t\t\t\t\t\t\t&nvlink_index)))\n 735\t\t\treturn ERR_PTR(-ENODEV);\n 736\t\tnpu_context->npdev[npu->index][nvlink_index] = npdev;\n 737\t\n 738\t\tif (!nphb->npu.nmmu_flush) {\n 739\t\t\t/*\n 740\t\t\t * If we're not explicitly flushing ourselves we need to mark\n 741\t\t\t * the thread for global flushes\n 742\t\t\t */\n 743\t\t\tnpu_context->nmmu_flush = false;\n > 744\t\t\tmm_context_add_copro(mm);\n 745\t\t} else\n 746\t\t\tnpu_context->nmmu_flush = true;\n 747\t\n 748\t\treturn npu_context;\n 749\t}\n 750\tEXPORT_SYMBOL(pnv_npu2_init_context);\n 751\t\n 752\tstatic void pnv_npu2_release_context(struct kref *kref)\n 753\t{\n 754\t\tstruct npu_context *npu_context =\n 755\t\t\tcontainer_of(kref, struct npu_context, kref);\n 756\t\n 757\t\tif (!npu_context->nmmu_flush)\n > 758\t\t\tmm_context_remove_copro(npu_context->mm);\n 759\t\n 760\t\tnpu_context->mm->context.npu_context = NULL;\n 761\t\tmmu_notifier_unregister(&npu_context->mn,\n 762\t\t\t\t\tnpu_context->mm);\n 763\t\n 764\t\tkfree(npu_context);\n 765\t}\n 766\t\n\n---\n0-DAY kernel test infrastructure Open Source Technology Center\nhttps://lists.01.org/pipermail/kbuild-all Intel Corporation","headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xpYNz6BW1z9s75\n\tfor ;\n\tFri, 8 Sep 2017 20:25:23 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xpYNz59cNzDrnP\n\tfor ;\n\tFri, 8 Sep 2017 20:25:23 +1000 (AEST)","from mga06.intel.com (mga06.intel.com [134.134.136.31])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xpYML3BngzDrYn\n\tfor ;\n\tFri, 8 Sep 2017 20:23:54 +1000 (AEST)","from fmsmga005.fm.intel.com ([10.253.24.32])\n\tby orsmga104.jf.intel.com with ESMTP; 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