[{"id":1763713,"web_url":"http://patchwork.ozlabs.org/comment/1763713/","msgid":"<000d01d32698$1cd4a9e0$567dfda0$@ovn.org>","list_archive_url":null,"date":"2017-09-05T22:41:27","subject":"Re: [ovs-dev] [PATCH] ovs-atomic-msvc: Add atomics x64 builds","submitter":{"id":72181,"url":"http://patchwork.ozlabs.org/api/people/72181/","name":"Alin-Gabriel Serdean","email":"aserdean@ovn.org"},"content":"I sent out a new version changing the commit message.\n\nPlease disregard this patch.\n\nAlin.\n\n> -----Original Message-----\n> From: ovs-dev-bounces@openvswitch.org [mailto:ovs-dev-\n> bounces@openvswitch.org] On Behalf Of Alin Gabriel Serdean\n> Sent: Wednesday, September 6, 2017 1:30 AM\n> To: dev@openvswitch.org\n> Cc: Alin Gabriel Serdean \n> Subject: [ovs-dev] [PATCH] ovs-atomic-msvc: Add atomics x64 builds\n> \n> This patch enables atomics on x64 builds.\n> \n> Reuse the atomics defined for x86 and add atomics for 64 bit reads/writes.\n> \n> Before this patch the cmap test gives us:\n> $ ./tests/ovstest.exe test-cmap benchmark 10000000 3 1 Benchmarking with\n> n=10000000, 3 threads, 1.00% mutations, batch size 1:\n> cmap insert: 20100 ms\n> cmap iterate: 2967 ms\n> batch search: 10929 ms\n> cmap destroy: 13489 ms\n> \n> cmap insert: 20079 ms\n> cmap iterate: 2953 ms\n> cmap search: 10559 ms\n> cmap destroy: 13486 ms\n> \n> hmap insert: 2021 ms\n> hmap iterate: 1162 ms\n> hmap search: 5152 ms\n> hmap destroy: 1158 ms\n> \n> After this change we have:\n> $ ./tests/ovstest.exe test-cmap benchmark 10000000 3 1 Benchmarking with\n> n=10000000, 3 threads, 1.00% mutations, batch size 1:\n> cmap insert: 20100 ms\n> cmap iterate: 2967 ms\n> batch search: 10929 ms\n> cmap destroy: 13489 ms\n> \n> cmap insert: 20079 ms\n> cmap iterate: 2953 ms\n> cmap search: 10559 ms\n> cmap destroy: 13486 ms\n> \n> hmap insert: 2021 ms\n> hmap iterate: 1162 ms\n> hmap search: 5152 ms\n> hmap destroy: 1158 ms\n> \n> $ ./tests/ovstest.exe test-cmap benchmark 10000000 3 1 Benchmarking with\n> n=10000000, 3 threads, 1.00% mutations, batch size 1:\n> cmap insert: 2953 ms\n> cmap iterate: 267 ms\n> batch search: 2193 ms\n> cmap destroy: 2037 ms\n> \n> cmap insert: 2909 ms\n> cmap iterate: 267 ms\n> cmap search: 2167 ms\n> cmap destroy: 2087 ms\n> \n> hmap insert: 1853 ms\n> hmap iterate: 1086 ms\n> hmap search: 4395 ms\n> hmap destroy: 1140 ms\n> \n> We should probably revisit this file and investigate it further to see if\nwe can\n> squeeze more performance.\n> \n> As a side effect fix tests on x64 because usage of `ovs-atomic-pthreads.h`\nis\n> currently broken.\n> \n> Signed-off-by: Alin Gabriel Serdean \n> Suggested-by: Ben Pfaff \n> ---\n> lib/ovs-atomic-msvc.h | 12 ++++++++++++\n> lib/ovs-atomic.h | 2 +-\n> 2 files changed, 13 insertions(+), 1 deletion(-)\n> \n> diff --git a/lib/ovs-atomic-msvc.h b/lib/ovs-atomic-msvc.h index\n> c6a7db3..0b041c6 100644\n> --- a/lib/ovs-atomic-msvc.h\n> +++ b/lib/ovs-atomic-msvc.h\n> @@ -107,6 +107,7 @@ atomic_signal_fence(memory_order order)\n> * InterlockedExchange64Acquire() available. So we are forced to use\n> * InterlockedExchange64() which uses full memory barrier for everything\n> * greater than 'memory_order_relaxed'. */\n> +#ifdef _M_IX86\n> #define atomic_store64(DST, SRC, ORDER)\n\\\n> if (ORDER == memory_order_relaxed) {\n\\\n> InterlockedExchangeNoFence64((int64_t volatile *) (DST),\n\\\n> @@ -114,6 +115,11 @@ atomic_signal_fence(memory_order order)\n> } else {\n\\\n> InterlockedExchange64((int64_t volatile *) (DST), (int64_t)\n(SRC));\\\n> }\n> +#elif _M_X64\n> +/* 64 bit writes are atomic on amd64 if 64 bit aligned. */\n> +#define atomic_store64(DST, SRC, ORDER) \\\n> + atomic_storeX(64, DST, SRC, ORDER)\n> +#endif\n> \n> /* Used for 8 and 16 bit variations. */\n> #define atomic_storeX(X, DST, SRC, ORDER) \\\n> @@ -160,11 +166,17 @@ atomic_signal_fence(memory_order order)\n> /* MSVC converts 64 bit reads into two instructions. So there is\n> * a possibility that an interrupt can make a 64 bit read non-atomic even\n> * when 8 byte aligned. So use fully memory barrier InterlockedOr64(). */\n> +#ifdef _M_IX86\n> #define atomic_read64(SRC, DST, ORDER)\n\\\n> __pragma (warning(push))\n\\\n> __pragma (warning(disable:4047))\n\\\n> *(DST) = InterlockedOr64((int64_t volatile *) (SRC), 0);\n\\\n> __pragma (warning(pop))\n> +#elif _M_X64\n> +/* 64 bit reads are atomic on amd64 if 64 bit aligned. */\n> +#define atomic_read64(SRC, DST, ORDER)\n\\\n> + *(DST) = *(SRC);\n> +#endif\n> \n> #define atomic_read(SRC, DST) \\\n> atomic_read_explicit(SRC, DST, memory_order_seq_cst) diff --git\n> a/lib/ovs-atomic.h b/lib/ovs-atomic.h index f1f2c38..c835eb7 100644\n> --- a/lib/ovs-atomic.h\n> +++ b/lib/ovs-atomic.h\n> @@ -335,7 +335,7 @@\n> #include \"ovs-atomic-i586.h\"\n> #elif HAVE_GCC4_ATOMICS\n> #include \"ovs-atomic-gcc4+.h\"\n> - #elif _MSC_VER && _M_IX86 >= 500\n> + #elif _MSC_VER\n> #include \"ovs-atomic-msvc.h\"\n> #else\n> /* ovs-atomic-pthreads implementation is provided for\nportability.\n> --\n> 2.10.2.windows.1\n> \n> _______________________________________________\n> dev mailing list\n> dev@openvswitch.org\n> https://mail.openvswitch.org/mailman/listinfo/ovs-dev","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","dev@openvswitch.org"],"Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","ovs-dev@mail.linuxfoundation.org"],"Authentication-Results":"ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=openvswitch.org\n\t(client-ip=140.211.169.12; helo=mail.linuxfoundation.org;\n\tenvelope-from=ovs-dev-bounces@openvswitch.org;\n\treceiver=)","Received":["from mail.linuxfoundation.org (mail.linuxfoundation.org\n\t[140.211.169.12])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xn1sn2gPpz9sR9\n\tfor ;\n\tWed, 6 Sep 2017 08:41:33 +1000 (AEST)","from mail.linux-foundation.org (localhost [127.0.0.1])\n\tby mail.linuxfoundation.org (Postfix) with ESMTP id 8BADAB13;\n\tTue, 5 Sep 2017 22:41:31 +0000 (UTC)","from smtp1.linuxfoundation.org (smtp1.linux-foundation.org\n\t[172.17.192.35])\n\tby mail.linuxfoundation.org (Postfix) with ESMTPS id 0C9A0AF4\n\tfor ; Tue, 5 Sep 2017 22:41:31 +0000 (UTC)","from relay6-d.mail.gandi.net (relay6-d.mail.gandi.net\n\t[217.70.183.198])\n\tby smtp1.linuxfoundation.org (Postfix) with ESMTPS id 02C3F8A\n\tfor ; Tue, 5 Sep 2017 22:41:28 +0000 (UTC)","from cloudbasealin (unknown [79.114.121.216])\n\t(Authenticated sender: aserdean@ovn.org)\n\tby relay6-d.mail.gandi.net (Postfix) with ESMTPSA id 7EFE0FB886;\n\tWed, 6 Sep 2017 00:41:27 +0200 (CEST)"],"X-Greylist":"domain auto-whitelisted by SQLgrey-1.7.6","X-Originating-IP":"79.114.121.216","From":"","To":"\"'Alin Gabriel Serdean'\" ,\n\t","References":"<20170905222950.8100-1-aserdean@ovn.org>","In-Reply-To":"<20170905222950.8100-1-aserdean@ovn.org>","Date":"Wed, 6 Sep 2017 01:41:27 +0300","Message-ID":"<000d01d32698$1cd4a9e0$567dfda0$@ovn.org>","MIME-Version":"1.0","X-Mailer":"Microsoft Outlook 16.0","Thread-Index":"AQHTJpaUrPi20BzHIU2w1Jdgm1MnJaKm4tOA","Content-Language":"ro","X-Spam-Status":"No, score=-0.7 required=5.0 tests=RCVD_IN_DNSWL_LOW\n\tautolearn=disabled version=3.3.1","X-Spam-Checker-Version":"SpamAssassin 3.3.1 (2010-03-16) on\n\tsmtp1.linux-foundation.org","Subject":"Re: [ovs-dev] [PATCH] ovs-atomic-msvc: Add atomics x64 builds","X-BeenThere":"ovs-dev@openvswitch.org","X-Mailman-Version":"2.1.12","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"ovs-dev-bounces@openvswitch.org","Errors-To":"ovs-dev-bounces@openvswitch.org"}}]