[{"id":1763338,"web_url":"http://patchwork.ozlabs.org/comment/1763338/","msgid":"<47d93f9f-008c-503d-b475-fba65fe69dc0@gmail.com>","list_archive_url":null,"date":"2017-09-05T13:02:18","subject":"Re: [PATCH v2 4/6] gpu: host1x: Disassemble more instructions","submitter":{"id":18124,"url":"http://patchwork.ozlabs.org/api/people/18124/","name":"Dmitry Osipenko","email":"digetx@gmail.com"},"content":"On 05.09.2017 11:10, Mikko Perttunen wrote:\n> The disassembler for debug dumps was missing some newer host1x opcodes.\n> Add disassembly support for these.\n> \n> Signed-off-by: Mikko Perttunen \n> ---\n> drivers/gpu/host1x/hw/debug_hw.c | 57 ++++++++++++++++++++++++++++++++---\n> drivers/gpu/host1x/hw/debug_hw_1x01.c | 3 +-\n> drivers/gpu/host1x/hw/debug_hw_1x06.c | 3 +-\n> 3 files changed, 57 insertions(+), 6 deletions(-)\n> \n> diff --git a/drivers/gpu/host1x/hw/debug_hw.c b/drivers/gpu/host1x/hw/debug_hw.c\n> index 1e67667e308c..de2a0ba7a32d 100644\n> --- a/drivers/gpu/host1x/hw/debug_hw.c\n> +++ b/drivers/gpu/host1x/hw/debug_hw.c\n> @@ -30,6 +30,13 @@ enum {\n> \tHOST1X_OPCODE_IMM\t= 0x04,\n> \tHOST1X_OPCODE_RESTART\t= 0x05,\n> \tHOST1X_OPCODE_GATHER\t= 0x06,\n> +\tHOST1X_OPCODE_SETSTRMID = 0x07,\n> +\tHOST1X_OPCODE_SETAPPID = 0x08,\n> +\tHOST1X_OPCODE_SETPYLD = 0x09,\n> +\tHOST1X_OPCODE_INCR_W = 0x0a,\n> +\tHOST1X_OPCODE_NONINCR_W = 0x0b,\n> +\tHOST1X_OPCODE_GATHER_W = 0x0c,\n> +\tHOST1X_OPCODE_RESTART_W = 0x0d,\n> \tHOST1X_OPCODE_EXTEND\t= 0x0e,\n> };\n> \n> @@ -38,11 +45,16 @@ enum {\n> \tHOST1X_OPCODE_EXTEND_RELEASE_MLOCK\t= 0x01,\n> };\n> \n> -static unsigned int show_channel_command(struct output *o, u32 val)\n> +#define INVALID_PAYLOAD\t\t\t\t0xffffffff\n> +\n> +static unsigned int show_channel_command(struct output *o, u32 val,\n> +\t\t\t\t\t u32 *payload)\n> {\n> -\tunsigned int mask, subop, num;\n> +\tunsigned int mask, subop, num, opcode;\n> +\n> +\topcode = val >> 28;\n> \n> -\tswitch (val >> 28) {\n> +\tswitch (opcode) {\n> \tcase HOST1X_OPCODE_SETCLASS:\n> \t\tmask = val & 0x3f;\n> \t\tif (mask) {\n> @@ -97,6 +109,42 @@ static unsigned int show_channel_command(struct output *o, u32 val)\n> \t\t\t\t val >> 14 & 0x1, val & 0x3fff);\n> \t\treturn 1;\n> \n\nOpcodes below aren't relevant to older Tegra's, seems \"#if HOST1X_HW >= 6\"\nshould be added here.\n\n> +\tcase HOST1X_OPCODE_SETSTRMID:\n> +\t\thost1x_debug_cont(o, \"SETSTRMID(offset=%06x)\\n\",\n> +\t\t\t\t val & 0x3fffff);\n> +\t\treturn 0;\n> +\n> +\tcase HOST1X_OPCODE_SETAPPID:\n> +\t\thost1x_debug_cont(o, \"SETAPPID(appid=%02x)\\n\", val & 0xff);\n> +\t\treturn 0;\n> +\n> +\tcase HOST1X_OPCODE_SETPYLD:\n> +\t\t*payload = val & 0xffff;\n> +\t\thost1x_debug_cont(o, \"SETPYLD(data=%04x)\\n\", *payload);\n> +\t\treturn 0;\n> +\n> +\tcase HOST1X_OPCODE_INCR_W:\n> +\tcase HOST1X_OPCODE_NONINCR_W:\n> +\t\thost1x_debug_cont(o, \"%s(offset=%06x, \",\n> +\t\t\t\t opcode == HOST1X_OPCODE_INCR_W ?\n> +\t\t\t\t\t\"INCR_W\" : \"NONINCR_W\",\n> +\t\t\t\t val & 0x3fffff);\n> +\t\tif (*payload == 0) {\n> +\t\t\thost1x_debug_cont(o, \"[])\\n\");\n> +\t\t\treturn 0;\n> +\t\t} else if (*payload == INVALID_PAYLOAD) {\n> +\t\t\thost1x_debug_cont(o, \"unknown)\\n\");\n> +\t\t\treturn 0;\n> +\t\t} else {\n> +\t\t\thost1x_debug_cont(o, \"[\");\n> +\t\t\treturn *payload;\n> +\t\t}\n> +\n> +\tcase HOST1X_OPCODE_GATHER_W:\n> +\t\thost1x_debug_cont(o, \"GATHER_W(count=%04x, addr=[\",\n> +\t\t\t\t val & 0x3fff);\n> +\t\treturn 2;\n> +\n> \tcase HOST1X_OPCODE_EXTEND:\n> \t\tsubop = val >> 24 & 0xf;\n> \t\tif (subop == HOST1X_OPCODE_EXTEND_ACQUIRE_MLOCK)\n> @@ -122,6 +170,7 @@ static void show_gather(struct output *o, phys_addr_t phys_addr,\n> \t/* Map dmaget cursor to corresponding mem handle */\n> \tu32 offset = phys_addr - pin_addr;\n> \tunsigned int data_count = 0, i;\n> +\tu32 payload = INVALID_PAYLOAD;\n> \n> \t/*\n> \t * Sometimes we're given different hardware address to the same\n> @@ -139,7 +188,7 @@ static void show_gather(struct output *o, phys_addr_t phys_addr,\n> \n> \t\tif (!data_count) {\n> \t\t\thost1x_debug_output(o, \"%08x: %08x: \", addr, val);\n> -\t\t\tdata_count = show_channel_command(o, val);\n> +\t\t\tdata_count = show_channel_command(o, val, &payload);\n> \t\t} else {\n> \t\t\thost1x_debug_cont(o, \"%08x%s\", val,\n> \t\t\t\t\t data_count > 1 ? \", \" : \"])\\n\");\n> diff --git a/drivers/gpu/host1x/hw/debug_hw_1x01.c b/drivers/gpu/host1x/hw/debug_hw_1x01.c\n> index 09e1aa7bb5dd..7d1401c6c193 100644\n> --- a/drivers/gpu/host1x/hw/debug_hw_1x01.c\n> +++ b/drivers/gpu/host1x/hw/debug_hw_1x01.c\n> @@ -78,6 +78,7 @@ static void host1x_debug_show_channel_fifo(struct host1x *host,\n> \t\t\t\t\t struct output *o)\n> {\n> \tu32 val, rd_ptr, wr_ptr, start, end;\n> +\tu32 payload = INVALID_PAYLOAD;\n> \tunsigned int data_count = 0;\n> \n> \thost1x_debug_output(o, \"%u: fifo:\\n\", ch->id);\n> @@ -112,7 +113,7 @@ static void host1x_debug_show_channel_fifo(struct host1x *host,\n> \n> \t\tif (!data_count) {\n> \t\t\thost1x_debug_output(o, \"%08x: \", val);\n> -\t\t\tdata_count = show_channel_command(o, val);\n> +\t\t\tdata_count = show_channel_command(o, val, &payload);\n> \t\t} else {\n> \t\t\thost1x_debug_cont(o, \"%08x%s\", val,\n> \t\t\t\t\t data_count > 1 ? \", \" : \"])\\n\");\n> diff --git a/drivers/gpu/host1x/hw/debug_hw_1x06.c b/drivers/gpu/host1x/hw/debug_hw_1x06.c\n> index bd89da5dc64c..b503c740c022 100644\n> --- a/drivers/gpu/host1x/hw/debug_hw_1x06.c\n> +++ b/drivers/gpu/host1x/hw/debug_hw_1x06.c\n> @@ -63,6 +63,7 @@ static void host1x_debug_show_channel_fifo(struct host1x *host,\n> \t\t\t\t\t struct output *o)\n> {\n> \tu32 val, rd_ptr, wr_ptr, start, end;\n> +\tu32 payload = INVALID_PAYLOAD;\n> \tunsigned int data_count = 0;\n> \n> \thost1x_debug_output(o, \"%u: fifo:\\n\", ch->id);\n> @@ -107,7 +108,7 @@ static void host1x_debug_show_channel_fifo(struct host1x *host,\n> \t\tif (!data_count) {\n> \t\t\thost1x_debug_output(o, \"%03x 0x%08x: \",\n> \t\t\t\t\t rd_ptr - start, val);\n> -\t\t\tdata_count = show_channel_command(o, val);\n> +\t\t\tdata_count = show_channel_command(o, val, &payload);\n> \t\t} else {\n> \t\t\thost1x_debug_cont(o, \"%08x%s\", val,\n> \t\t\t\t\t data_count > 1 ? \", \" : \"])\\n\");\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-tegra-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"XfAjFy4E\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xmn1X3KnHz9t16\n\tfor ;\n\tTue, 5 Sep 2017 23:02:24 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751236AbdIENCX (ORCPT );\n\tTue, 5 Sep 2017 09:02:23 -0400","from mail-lf0-f68.google.com ([209.85.215.68]:38465 \"EHLO\n\tmail-lf0-f68.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1750955AbdIENCW (ORCPT\n\t); Tue, 5 Sep 2017 09:02:22 -0400","by mail-lf0-f68.google.com with SMTP id m199so1700952lfe.5;\n\tTue, 05 Sep 2017 06:02:21 -0700 (PDT)","from [192.168.1.145] (ppp109-252-91-9.pppoe.spdop.ru.\n\t[109.252.91.9]) by smtp.googlemail.com with ESMTPSA id\n\ty1sm96612lfg.67.2017.09.05.06.02.19\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tTue, 05 Sep 2017 06:02:19 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=gmail.com; s=20161025;\n\th=subject:to:cc:references:from:message-id:date:user-agent\n\t:mime-version:in-reply-to:content-language:content-transfer-encoding; \n\tbh=Lqcasj5zWjvoKgm50qjjOtfOi90kiTyynpirBU9gAO4=;\n\tb=XfAjFy4EYrdr0a+egMgrbm1fLYsfdrHzxoPS6rSDlMnU8ruLnhyLfJSq88xJAn+2Vo\n\t/z/6wVQ0RzwoL0l5mukOoyBZiXtlbTjZtykv7/FI6LILuGxF3MlfxxY3mxyDQd4ZMmOp\n\tpfGfFOcfrFL13KDToLT/rjiQCpSuy8PHGhbTT9TS6Xfd9yCVCbCb1HYj3y5hRVLd2+ko\n\txqxxFUcl7X124zxGhKq532L5pvoWfensjmNDyqSmmY1XTC9MINi7+Ms7aCuRA5jAiRQa\n\t7x/e4pVihBqN5O6sVzSUlfgqZOrGUjeHzSJ1tb6EO2ZOxioaIY4/jl9jmv6P8P+wGRZ7\n\tVDyw==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:subject:to:cc:references:from:message-id:date\n\t:user-agent:mime-version:in-reply-to:content-language\n\t:content-transfer-encoding;\n\tbh=Lqcasj5zWjvoKgm50qjjOtfOi90kiTyynpirBU9gAO4=;\n\tb=dj2qd69w9py5bCSLkhZSymI3jGDaMHBplo02r6+sFQhEMxzpSGLqER2Ltcf68oTDwb\n\t24f1twVslC/8vP/Zwsd35iUEZ/pq0W1rgToF+FX9dPMALHk9jN3CmmnOx0VL6uEDxw3f\n\ttKx2CuB2rX8LeN93vYQzqgMPQxr5SbyIVEiJm+jXelMJsHCdDeG1VlJqNwx+rZw87rNI\n\tRumdGoHXGbXxrrJ3IuTgAOY3qFKsZgYgye8PTPcTv7r+YIzKoJnYAa6x7LEMEK47TscE\n\tHxoay5az36M7iuj+oXVd0inFqD+eEZuFVIPm9J/mROep8KypZcpeSiKjib2KnE3OKR3z\n\t/Gtg==","X-Gm-Message-State":"AHPjjUhQ8KBggwEF5RxYILoWEKSjxODUjS43oX9VZYLjurC/ral7gEv3\n\tU4YZjIU/gHIgostvJW4=","X-Google-Smtp-Source":"ADKCNb5wbsKpOv5csTVFsINoOGymRGIVwoBQjeMMdu4Csmw9JLaE/XeWhvvjzVtKExPLM6mO4CVimA==","X-Received":"by 10.46.85.156 with SMTP id g28mr1460967lje.116.1504616540668; \n\tTue, 05 Sep 2017 06:02:20 -0700 (PDT)","Subject":"Re: [PATCH v2 4/6] gpu: host1x: Disassemble more instructions","To":"Mikko Perttunen , thierry.reding@gmail.com,\n\tjonathanh@nvidia.com","Cc":"dri-devel@lists.freedesktop.org, linux-tegra@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org","References":"<20170905081029.19769-1-mperttunen@nvidia.com>\n\t<20170905081029.19769-5-mperttunen@nvidia.com>","From":"Dmitry Osipenko ","Message-ID":"<47d93f9f-008c-503d-b475-fba65fe69dc0@gmail.com>","Date":"Tue, 5 Sep 2017 16:02:18 +0300","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<20170905081029.19769-5-mperttunen@nvidia.com>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","Sender":"linux-tegra-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-tegra@vger.kernel.org"}}]