[{"id":1778019,"web_url":"http://patchwork.ozlabs.org/comment/1778019/","msgid":"","list_archive_url":null,"date":"2017-10-01T14:48:47","subject":"Re: [RFC v3 3/7] platform/x86: intel_pmc_ipc: Use regmap calls for\n\tGCR updates","submitter":{"id":4675,"url":"http://patchwork.ozlabs.org/api/people/4675/","name":"Andy Shevchenko","email":"andy.shevchenko@gmail.com"},"content":"On Tue, Sep 5, 2017 at 8:37 AM,\n wrote:\n> From: Kuppuswamy Sathyanarayanan \n>\n> Currently, update_no_reboot_bit() function implemented in this driver\n> uses mutex_lock to protect its register updates. But this function is\n> called with in atomic context in iTCO_wdt_start() and iTCO_wdt_stop()\n> functions in iTCO_wdt.c driver, which in turn causes \"sleeping into\n> atomic context\" issue. This patch fixes this issue by refactoring the\n> current GCR read/write/update functions with regmap APIs.\n\nSince it sounds as candidate for stable, can we have split it to just\nas less as possible intrusive fix + moving to regmap as a separate\nchange?\nIt should include Fixes: tag as well I suppose.\n\n>\n> Signed-off-by: Kuppuswamy Sathyanarayanan \n> ---\n> drivers/platform/x86/Kconfig | 1 +\n> drivers/platform/x86/intel_pmc_ipc.c | 115 ++++++++++++-----------------------\n> 2 files changed, 40 insertions(+), 76 deletions(-)\n>\n> diff --git a/drivers/platform/x86/Kconfig b/drivers/platform/x86/Kconfig\n> index 80b8795..45f4e79 100644\n> --- a/drivers/platform/x86/Kconfig\n> +++ b/drivers/platform/x86/Kconfig\n> @@ -1054,6 +1054,7 @@ config PVPANIC\n> config INTEL_PMC_IPC\n> tristate \"Intel PMC IPC Driver\"\n> depends on ACPI\n> + select REGMAP_MMIO\n> ---help---\n> This driver provides support for PMC control on some Intel platforms.\n> The PMC is an ARC processor which defines IPC commands for communication\n> diff --git a/drivers/platform/x86/intel_pmc_ipc.c b/drivers/platform/x86/intel_pmc_ipc.c\n> index 021dcf6..40a25f8 100644\n> --- a/drivers/platform/x86/intel_pmc_ipc.c\n> +++ b/drivers/platform/x86/intel_pmc_ipc.c\n> @@ -31,9 +31,11 @@\n> #include \n> #include \n> #include \n> +#include \n> #include \n> #include \n> #include \n> +#include \n>\n> #include \n>\n> @@ -125,7 +127,7 @@ static struct intel_pmc_ipc_dev {\n>\n> /* gcr */\n> void __iomem *gcr_mem_base;\n> - bool has_gcr_regs;\n> + struct regmap *gcr_regs;\n>\n> /* Telemetry */\n> u8 telem_res_inval;\n> @@ -150,6 +152,14 @@ static char *ipc_err_sources[] = {\n> \"Unsigned kernel\",\n> };\n>\n> +static struct regmap_config gcr_regmap_config = {\n> + .reg_bits = 32,\n> + .reg_stride = 4,\n> + .val_bits = 32,\n> + .fast_io = true,\n> + .max_register = PLAT_RESOURCE_GCR_SIZE,\n> +};\n> +\n> /* Prevent concurrent calls to the PMC */\n> static DEFINE_MUTEX(ipclock);\n>\n> @@ -183,21 +193,6 @@ static inline u32 ipc_data_readl(u32 offset)\n> return readl(ipcdev.ipc_base + IPC_READ_BUFFER + offset);\n> }\n>\n> -static inline u64 gcr_data_readq(u32 offset)\n> -{\n> - return readq(ipcdev.gcr_mem_base + offset);\n> -}\n> -\n> -static inline int is_gcr_valid(u32 offset)\n> -{\n> - if (!ipcdev.has_gcr_regs)\n> - return -EACCES;\n> -\n> - if (offset > PLAT_RESOURCE_GCR_SIZE)\n> - return -EINVAL;\n> -\n> - return 0;\n> -}\n>\n> /**\n> * intel_pmc_gcr_read() - Read PMC GCR register\n> @@ -210,21 +205,10 @@ static inline int is_gcr_valid(u32 offset)\n> */\n> int intel_pmc_gcr_read(u32 offset, u32 *data)\n> {\n> - int ret;\n> -\n> - mutex_lock(&ipclock);\n> -\n> - ret = is_gcr_valid(offset);\n> - if (ret < 0) {\n> - mutex_unlock(&ipclock);\n> - return ret;\n> - }\n> -\n> - *data = readl(ipcdev.gcr_mem_base + offset);\n> -\n> - mutex_unlock(&ipclock);\n> + if (!ipcdev.gcr_regs)\n> + return -EACCES;\n>\n> - return 0;\n> + return regmap_read(ipcdev.gcr_regs, offset, data);\n> }\n> EXPORT_SYMBOL_GPL(intel_pmc_gcr_read);\n>\n> @@ -240,21 +224,10 @@ EXPORT_SYMBOL_GPL(intel_pmc_gcr_read);\n> */\n> int intel_pmc_gcr_write(u32 offset, u32 data)\n> {\n> - int ret;\n> -\n> - mutex_lock(&ipclock);\n> -\n> - ret = is_gcr_valid(offset);\n> - if (ret < 0) {\n> - mutex_unlock(&ipclock);\n> - return ret;\n> - }\n> -\n> - writel(data, ipcdev.gcr_mem_base + offset);\n> -\n> - mutex_unlock(&ipclock);\n> + if (!ipcdev.gcr_regs)\n> + return -EACCES;\n>\n> - return 0;\n> + return regmap_write(ipcdev.gcr_regs, offset, data);\n> }\n> EXPORT_SYMBOL_GPL(intel_pmc_gcr_write);\n>\n> @@ -271,33 +244,10 @@ EXPORT_SYMBOL_GPL(intel_pmc_gcr_write);\n> */\n> int intel_pmc_gcr_update(u32 offset, u32 mask, u32 val)\n> {\n> - u32 new_val;\n> - int ret = 0;\n> -\n> - mutex_lock(&ipclock);\n> -\n> - ret = is_gcr_valid(offset);\n> - if (ret < 0)\n> - goto gcr_ipc_unlock;\n> -\n> - new_val = readl(ipcdev.gcr_mem_base + offset);\n> -\n> - new_val &= ~mask;\n> - new_val |= val & mask;\n> -\n> - writel(new_val, ipcdev.gcr_mem_base + offset);\n> -\n> - new_val = readl(ipcdev.gcr_mem_base + offset);\n> -\n> - /* check whether the bit update is successful */\n> - if ((new_val & mask) != (val & mask)) {\n> - ret = -EIO;\n> - goto gcr_ipc_unlock;\n> - }\n> + if (!ipcdev.gcr_regs)\n> + return -EACCES;\n>\n> -gcr_ipc_unlock:\n> - mutex_unlock(&ipclock);\n> - return ret;\n> + return regmap_update_bits(ipcdev.gcr_regs, offset, mask, val);\n> }\n> EXPORT_SYMBOL_GPL(intel_pmc_gcr_update);\n>\n> @@ -776,16 +726,24 @@ static int ipc_plat_get_res(struct platform_device *pdev)\n> int intel_pmc_s0ix_counter_read(u64 *data)\n> {\n> u64 deep, shlw;\n> + int ret;\n>\n> - if (!ipcdev.has_gcr_regs)\n> + if (!ipcdev.gcr_regs)\n> return -EACCES;\n>\n> - deep = gcr_data_readq(PMC_GCR_TELEM_DEEP_S0IX_REG);\n> - shlw = gcr_data_readq(PMC_GCR_TELEM_SHLW_S0IX_REG);\n> + ret = regmap_bulk_read(ipcdev.gcr_regs, PMC_GCR_TELEM_DEEP_S0IX_REG,\n> + &deep, 2);\n> + if (ret)\n> + return ret;\n> +\n> + ret = regmap_bulk_read(ipcdev.gcr_regs, PMC_GCR_TELEM_SHLW_S0IX_REG,\n> + &shlw, 2);\n> + if (ret)\n> + return ret;\n>\n> *data = S0IX_RESIDENCY_IN_USECS(deep, shlw);\n>\n> - return 0;\n> + return ret;\n> }\n> EXPORT_SYMBOL_GPL(intel_pmc_s0ix_counter_read);\n>\n> @@ -817,6 +775,13 @@ static int ipc_plat_probe(struct platform_device *pdev)\n> return ret;\n> }\n>\n> + ipcdev.gcr_regs = devm_regmap_init_mmio_clk(ipcdev.dev, NULL,\n> + ipcdev.gcr_mem_base, &gcr_regmap_config);\n> + if (IS_ERR(ipcdev.gcr_regs)) {\n> + dev_err(ipcdev.dev, \"gcr_regs regmap init failed\\n\");\n> + return PTR_ERR(ipcdev.gcr_regs);;\n> + }\n> +\n> ret = ipc_create_pmc_devices(pdev);\n> if (ret) {\n> dev_err(&pdev->dev, \"Failed to create pmc devices\\n\");\n> @@ -836,8 +801,6 @@ static int ipc_plat_probe(struct platform_device *pdev)\n> return ret;\n> }\n>\n> - ipcdev.has_gcr_regs = true;\n> -\n> return 0;\n> }\n>\n> --\n> 2.7.4\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-rtc-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"hseQfd7A\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y4p8c5zb6z9t42\n\tfor ;\n\tMon, 2 Oct 2017 01:49:04 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751042AbdJAOsv (ORCPT );\n\tSun, 1 Oct 2017 10:48:51 -0400","from mail-qk0-f193.google.com ([209.85.220.193]:36760 \"EHLO\n\tmail-qk0-f193.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1750981AbdJAOst (ORCPT\n\t); Sun, 1 Oct 2017 10:48:49 -0400","by mail-qk0-f193.google.com with SMTP id z14so2477120qkg.3;\n\tSun, 01 Oct 2017 07:48:48 -0700 (PDT)","by 10.12.190.196 with HTTP; Sun, 1 Oct 2017 07:48:47 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=gmail.com; s=20161025;\n\th=mime-version:in-reply-to:references:from:date:message-id:subject:to\n\t:cc; bh=8T8peLZLnEvw7acqiODt70mjnZkrui8kGk+ISeeBlQU=;\n\tb=hseQfd7ACJJDD1hLrPwZRpM8sXuTyR+NWUaG86jiA3TyKu++poDb/wR5mwyDfGuGTl\n\tlbN2/m2oXoCh4hU5HaD362uPFqqC0a7EvbakkKi8sCCaDgu8huf7wTmVNZgf5Yopj5Q0\n\t7Yroi5TZr8bJmgH9tjRHNK8GtXB906PqNtwbmmiLpbVaItjZvb0LbXRcB6WpcZL70/VG\n\th+9TxxLWQCIo7YyG9Q/z30pBnxiUQRa8x3W6L//mfxsI9kAxwk9H/R5qpHmyKUR0qhj7\n\tMGCd5jJVMPvHpyhEWTZ9w/cxD1RfrcZoS9BTWGf77XV+k4f08KAxPMm4QYRMPV4DgaBb\n\txlBw==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:mime-version:in-reply-to:references:from:date\n\t:message-id:subject:to:cc;\n\tbh=8T8peLZLnEvw7acqiODt70mjnZkrui8kGk+ISeeBlQU=;\n\tb=UDkC/gX6hxkoZv4JEQNdffgLOEKdDBZQ8O8QiIk7nPMWtT5S1bDC1Bqeq0G8HEKe/1\n\tM8mcApPx2f/bsxoGs1egFxefgvnAPlGsRo9lb3fliTWJQ9XG4USp1PUOgm62N9m4xlP/\n\tLGsoY1uPNP/M5UBeUY9Exz02FBwjKEbqNKT8J8RTyWFwJuIKsrN0PyEhTHfn4u7a57zh\n\tIlFF3m7o7WqcJjbdgds5BpOx4A9HQu+0bJOEaI5liLd2wz7A5JNTYrH5NwmDe+Dp7IeK\n\tDwvcvA2mU7R+6pZ69xW5wFWmPfRFI86HzhfmAv55AyWt6UnrDjl9YErV4SudJeiitM1D\n\t2tmw==","X-Gm-Message-State":"AMCzsaVWpOZNWPCMY07UaW4JDDu1qZYJN+vOxayUc8euOpbRT5WUrbSo\n\tYoxzBYp+DYICEy8xjzMIu9ZwhbrI/Psuo3MhgBk=","X-Google-Smtp-Source":"AOwi7QA9R96U5BuWZ6dmPoptIK4hbowsiIg6EIyb8YQ1Bz9Ggl3MWpMZL3X0PBVocOGTX2PJvetHxBvAXt3v5n5m+s8=","X-Received":"by 10.55.96.67 with SMTP id u64mr4340859qkb.323.1506869328256;\n\tSun, 01 Oct 2017 07:48:48 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"<5286489131571f149c6b75a8367ceb93cfe6e6be.1504588701.git.sathyanarayanan.kuppuswamy@linux.intel.com>","References":"\n\t<5286489131571f149c6b75a8367ceb93cfe6e6be.1504588701.git.sathyanarayanan.kuppuswamy@linux.intel.com>","From":"Andy Shevchenko ","Date":"Sun, 1 Oct 2017 17:48:47 +0300","Message-ID":"","Subject":"Re: [RFC v3 3/7] platform/x86: intel_pmc_ipc: Use regmap calls for\n\tGCR updates","To":"Kuppuswamy Sathyanarayanan ","Cc":"Alessandro Zummo ,\n\t\"x86@kernel.org\" , Wim Van Sebroeck ,\n\tIngo Molnar ,\n\tAlexandre Belloni ,\n\tZha Qipeng , \"H. Peter Anvin\" ,\n\t\"dvhart@infradead.org\" ,\n\tThomas Gleixner , Lee Jones ,\n\tAndy Shevchenko ,\n\tSouvik Kumar Chakravarty ,\n\tlinux-rtc@vger.kernel.org, linux-watchdog@vger.kernel.org,\n\t\"linux-kernel@vger.kernel.org\" ,\n\tPlatform Driver ,\n\tSathyanarayanan Kuppuswamy Natarajan ","Content-Type":"text/plain; charset=\"UTF-8\"","Sender":"linux-rtc-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-rtc@vger.kernel.org"}},{"id":1779346,"web_url":"http://patchwork.ozlabs.org/comment/1779346/","msgid":"<5ba5b3d9-b55a-5834-04e5-b4b9a356dca7@linux.intel.com>","list_archive_url":null,"date":"2017-10-04T01:16:32","subject":"Re: [RFC v3 3/7] platform/x86: intel_pmc_ipc: Use regmap calls for\n\tGCR updates","submitter":{"id":66129,"url":"http://patchwork.ozlabs.org/api/people/66129/","name":"Kuppuswamy Sathyanarayanan","email":"sathyanarayanan.kuppuswamy@linux.intel.com"},"content":"Hi Andy,\n\n\nOn 10/01/2017 07:48 AM, Andy Shevchenko wrote:\n> On Tue, Sep 5, 2017 at 8:37 AM,\n> wrote:\n>> From: Kuppuswamy Sathyanarayanan \n>>\n>> Currently, update_no_reboot_bit() function implemented in this driver\n>> uses mutex_lock to protect its register updates. But this function is\n>> called with in atomic context in iTCO_wdt_start() and iTCO_wdt_stop()\n>> functions in iTCO_wdt.c driver, which in turn causes \"sleeping into\n>> atomic context\" issue. This patch fixes this issue by refactoring the\n>> current GCR read/write/update functions with regmap APIs.\n> Since it sounds as candidate for stable,\nYes.\n> can we have split it to just\n> as less as possible intrusive fix + moving to regmap as a separate\n> change?\nIf we have to split it into two patches then,\n\nPatch #1 will fix the \"sleep in atomic context issue\" by replacing \nmutex_lock() with spin_lock()\nin GCR read/write APIs to protect the GCR memory updates.\nPatch #2 will remove GCR read/write/update APIs and replace it with \nregmap APIs. But along with this\nchange we will also remove the spin_lock() added in previous patch \nbecause regmap calls are already\nprotected by its own locking mechanism.\n\nSince Patch #2 will clean up what we do in Patch #1, Do we need to split \nit into two patches?\n\n> It should include Fixes: tag as well I suppose.\nAgree. I will add Fixes tag in next version.\n>\n>> Signed-off-by: Kuppuswamy Sathyanarayanan \n>> ---\n>> drivers/platform/x86/Kconfig | 1 +\n>> drivers/platform/x86/intel_pmc_ipc.c | 115 ++++++++++++-----------------------\n>> 2 files changed, 40 insertions(+), 76 deletions(-)\n>>\n>> diff --git a/drivers/platform/x86/Kconfig b/drivers/platform/x86/Kconfig\n>> index 80b8795..45f4e79 100644\n>> --- a/drivers/platform/x86/Kconfig\n>> +++ b/drivers/platform/x86/Kconfig\n>> @@ -1054,6 +1054,7 @@ config PVPANIC\n>> config INTEL_PMC_IPC\n>> tristate \"Intel PMC IPC Driver\"\n>> depends on ACPI\n>> + select REGMAP_MMIO\n>> ---help---\n>> This driver provides support for PMC control on some Intel platforms.\n>> The PMC is an ARC processor which defines IPC commands for communication\n>> diff --git a/drivers/platform/x86/intel_pmc_ipc.c b/drivers/platform/x86/intel_pmc_ipc.c\n>> index 021dcf6..40a25f8 100644\n>> --- a/drivers/platform/x86/intel_pmc_ipc.c\n>> +++ b/drivers/platform/x86/intel_pmc_ipc.c\n>> @@ -31,9 +31,11 @@\n>> #include \n>> #include \n>> #include \n>> +#include \n>> #include \n>> #include \n>> #include \n>> +#include \n>>\n>> #include \n>>\n>> @@ -125,7 +127,7 @@ static struct intel_pmc_ipc_dev {\n>>\n>> /* gcr */\n>> void __iomem *gcr_mem_base;\n>> - bool has_gcr_regs;\n>> + struct regmap *gcr_regs;\n>>\n>> /* Telemetry */\n>> u8 telem_res_inval;\n>> @@ -150,6 +152,14 @@ static char *ipc_err_sources[] = {\n>> \"Unsigned kernel\",\n>> };\n>>\n>> +static struct regmap_config gcr_regmap_config = {\n>> + .reg_bits = 32,\n>> + .reg_stride = 4,\n>> + .val_bits = 32,\n>> + .fast_io = true,\n>> + .max_register = PLAT_RESOURCE_GCR_SIZE,\n>> +};\n>> +\n>> /* Prevent concurrent calls to the PMC */\n>> static DEFINE_MUTEX(ipclock);\n>>\n>> @@ -183,21 +193,6 @@ static inline u32 ipc_data_readl(u32 offset)\n>> return readl(ipcdev.ipc_base + IPC_READ_BUFFER + offset);\n>> }\n>>\n>> -static inline u64 gcr_data_readq(u32 offset)\n>> -{\n>> - return readq(ipcdev.gcr_mem_base + offset);\n>> -}\n>> -\n>> -static inline int is_gcr_valid(u32 offset)\n>> -{\n>> - if (!ipcdev.has_gcr_regs)\n>> - return -EACCES;\n>> -\n>> - if (offset > PLAT_RESOURCE_GCR_SIZE)\n>> - return -EINVAL;\n>> -\n>> - return 0;\n>> -}\n>>\n>> /**\n>> * intel_pmc_gcr_read() - Read PMC GCR register\n>> @@ -210,21 +205,10 @@ static inline int is_gcr_valid(u32 offset)\n>> */\n>> int intel_pmc_gcr_read(u32 offset, u32 *data)\n>> {\n>> - int ret;\n>> -\n>> - mutex_lock(&ipclock);\n>> -\n>> - ret = is_gcr_valid(offset);\n>> - if (ret < 0) {\n>> - mutex_unlock(&ipclock);\n>> - return ret;\n>> - }\n>> -\n>> - *data = readl(ipcdev.gcr_mem_base + offset);\n>> -\n>> - mutex_unlock(&ipclock);\n>> + if (!ipcdev.gcr_regs)\n>> + return -EACCES;\n>>\n>> - return 0;\n>> + return regmap_read(ipcdev.gcr_regs, offset, data);\n>> }\n>> EXPORT_SYMBOL_GPL(intel_pmc_gcr_read);\n>>\n>> @@ -240,21 +224,10 @@ EXPORT_SYMBOL_GPL(intel_pmc_gcr_read);\n>> */\n>> int intel_pmc_gcr_write(u32 offset, u32 data)\n>> {\n>> - int ret;\n>> -\n>> - mutex_lock(&ipclock);\n>> -\n>> - ret = is_gcr_valid(offset);\n>> - if (ret < 0) {\n>> - mutex_unlock(&ipclock);\n>> - return ret;\n>> - }\n>> -\n>> - writel(data, ipcdev.gcr_mem_base + offset);\n>> -\n>> - mutex_unlock(&ipclock);\n>> + if (!ipcdev.gcr_regs)\n>> + return -EACCES;\n>>\n>> - return 0;\n>> + return regmap_write(ipcdev.gcr_regs, offset, data);\n>> }\n>> EXPORT_SYMBOL_GPL(intel_pmc_gcr_write);\n>>\n>> @@ -271,33 +244,10 @@ EXPORT_SYMBOL_GPL(intel_pmc_gcr_write);\n>> */\n>> int intel_pmc_gcr_update(u32 offset, u32 mask, u32 val)\n>> {\n>> - u32 new_val;\n>> - int ret = 0;\n>> -\n>> - mutex_lock(&ipclock);\n>> -\n>> - ret = is_gcr_valid(offset);\n>> - if (ret < 0)\n>> - goto gcr_ipc_unlock;\n>> -\n>> - new_val = readl(ipcdev.gcr_mem_base + offset);\n>> -\n>> - new_val &= ~mask;\n>> - new_val |= val & mask;\n>> -\n>> - writel(new_val, ipcdev.gcr_mem_base + offset);\n>> -\n>> - new_val = readl(ipcdev.gcr_mem_base + offset);\n>> -\n>> - /* check whether the bit update is successful */\n>> - if ((new_val & mask) != (val & mask)) {\n>> - ret = -EIO;\n>> - goto gcr_ipc_unlock;\n>> - }\n>> + if (!ipcdev.gcr_regs)\n>> + return -EACCES;\n>>\n>> -gcr_ipc_unlock:\n>> - mutex_unlock(&ipclock);\n>> - return ret;\n>> + return regmap_update_bits(ipcdev.gcr_regs, offset, mask, val);\n>> }\n>> EXPORT_SYMBOL_GPL(intel_pmc_gcr_update);\n>>\n>> @@ -776,16 +726,24 @@ static int ipc_plat_get_res(struct platform_device *pdev)\n>> int intel_pmc_s0ix_counter_read(u64 *data)\n>> {\n>> u64 deep, shlw;\n>> + int ret;\n>>\n>> - if (!ipcdev.has_gcr_regs)\n>> + if (!ipcdev.gcr_regs)\n>> return -EACCES;\n>>\n>> - deep = gcr_data_readq(PMC_GCR_TELEM_DEEP_S0IX_REG);\n>> - shlw = gcr_data_readq(PMC_GCR_TELEM_SHLW_S0IX_REG);\n>> + ret = regmap_bulk_read(ipcdev.gcr_regs, PMC_GCR_TELEM_DEEP_S0IX_REG,\n>> + &deep, 2);\n>> + if (ret)\n>> + return ret;\n>> +\n>> + ret = regmap_bulk_read(ipcdev.gcr_regs, PMC_GCR_TELEM_SHLW_S0IX_REG,\n>> + &shlw, 2);\n>> + if (ret)\n>> + return ret;\n>>\n>> *data = S0IX_RESIDENCY_IN_USECS(deep, shlw);\n>>\n>> - return 0;\n>> + return ret;\n>> }\n>> EXPORT_SYMBOL_GPL(intel_pmc_s0ix_counter_read);\n>>\n>> @@ -817,6 +775,13 @@ static int ipc_plat_probe(struct platform_device *pdev)\n>> return ret;\n>> }\n>>\n>> + ipcdev.gcr_regs = devm_regmap_init_mmio_clk(ipcdev.dev, NULL,\n>> + ipcdev.gcr_mem_base, &gcr_regmap_config);\n>> + if (IS_ERR(ipcdev.gcr_regs)) {\n>> + dev_err(ipcdev.dev, \"gcr_regs regmap init failed\\n\");\n>> + return PTR_ERR(ipcdev.gcr_regs);;\n>> + }\n>> +\n>> ret = ipc_create_pmc_devices(pdev);\n>> if (ret) {\n>> dev_err(&pdev->dev, \"Failed to create pmc devices\\n\");\n>> @@ -836,8 +801,6 @@ static int ipc_plat_probe(struct platform_device *pdev)\n>> return ret;\n>> }\n>>\n>> - ipcdev.has_gcr_regs = true;\n>> -\n>> return 0;\n>> }\n>>\n>> --\n>> 2.7.4\n>>\n>\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-rtc-owner@vger.kernel.org;\n\treceiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y6J0D1ZwDz9t2V\n\tfor ;\n\tWed, 4 Oct 2017 12:17:00 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751315AbdJDBQr (ORCPT );\n\tTue, 3 Oct 2017 21:16:47 -0400","from mga14.intel.com ([192.55.52.115]:37378 \"EHLO mga14.intel.com\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1751115AbdJDBQq (ORCPT );\n\tTue, 3 Oct 2017 21:16:46 -0400","from fmsmga003.fm.intel.com ([10.253.24.29])\n\tby fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t03 Oct 2017 18:16:45 -0700","from linux.intel.com ([10.54.29.200])\n\tby FMSMGA003.fm.intel.com with ESMTP; 03 Oct 2017 18:16:44 -0700","from [10.7.198.92] (skuppusw-desk.jf.intel.com [10.7.198.92])\n\tby linux.intel.com (Postfix) with ESMTP id 54A645802D8;\n\tTue, 3 Oct 2017 18:16:44 -0700 (PDT)"],"X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos;i=\"5.42,475,1500966000\"; d=\"scan'208\";a=\"906442687\"","Reply-To":"sathyanarayanan.kuppuswamy@linux.intel.com","Subject":"Re: [RFC v3 3/7] platform/x86: intel_pmc_ipc: Use regmap calls for\n\tGCR updates","To":"Andy Shevchenko ","Cc":"Alessandro Zummo ,\n\t\"x86@kernel.org\" , Wim Van Sebroeck ,\n\tIngo Molnar ,\n\tAlexandre Belloni ,\n\tZha Qipeng , \"H. Peter Anvin\" ,\n\t\"dvhart@infradead.org\" ,\n\tThomas Gleixner , Lee Jones ,\n\tAndy Shevchenko ,\n\tSouvik Kumar Chakravarty ,\n\tlinux-rtc@vger.kernel.org, linux-watchdog@vger.kernel.org,\n\t\"linux-kernel@vger.kernel.org\" ,\n\tPlatform Driver ,\n\tSathyanarayanan Kuppuswamy Natarajan ","References":"\n\t<5286489131571f149c6b75a8367ceb93cfe6e6be.1504588701.git.sathyanarayanan.kuppuswamy@linux.intel.com>\n\t","From":"sathyanarayanan kuppuswamy \n\t","Organization":"Intel","Message-ID":"<5ba5b3d9-b55a-5834-04e5-b4b9a356dca7@linux.intel.com>","Date":"Tue, 3 Oct 2017 18:16:32 -0700","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"","Content-Type":"text/plain; charset=utf-8; format=flowed","Content-Transfer-Encoding":"7bit","Content-Language":"en-US","Sender":"linux-rtc-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-rtc@vger.kernel.org"}},{"id":1779765,"web_url":"http://patchwork.ozlabs.org/comment/1779765/","msgid":"","list_archive_url":null,"date":"2017-10-04T12:37:20","subject":"Re: [RFC v3 3/7] platform/x86: intel_pmc_ipc: Use regmap calls for\n\tGCR updates","submitter":{"id":4675,"url":"http://patchwork.ozlabs.org/api/people/4675/","name":"Andy Shevchenko","email":"andy.shevchenko@gmail.com"},"content":"On Wed, Oct 4, 2017 at 4:16 AM, sathyanarayanan kuppuswamy\n wrote:\n> On 10/01/2017 07:48 AM, Andy Shevchenko wrote:\n>> On Tue, Sep 5, 2017 at 8:37 AM,\n>> wrote:\n\n>> Since it sounds as candidate for stable,\n>\n> Yes.\n>>\n>> can we have split it to just\n>> as less as possible intrusive fix + moving to regmap as a separate\n>> change?\n>\n> If we have to split it into two patches then,\n>\n> Patch #1 will fix the \"sleep in atomic context issue\" by replacing\n> mutex_lock() with spin_lock()\n> in GCR read/write APIs to protect the GCR memory updates.\n> Patch #2 will remove GCR read/write/update APIs and replace it with regmap\n> APIs. But along with this\n> change we will also remove the spin_lock() added in previous patch because\n> regmap calls are already\n> protected by its own locking mechanism.\n>\n> Since Patch #2 will clean up what we do in Patch #1, Do we need to split it\n> into two patches?\n\nYes, please do...\n\n>> It should include Fixes: tag as well I suppose.\n>\n> Agree. I will add Fixes tag in next version.\n\n...because this one will go alone to stable releases.\n\nBe also sure patch #1 will be applied on current vanilla (w/o PDx86\nqueue involvement).","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-rtc-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"Q03wB4Uh\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y6b5H56wlz9t16\n\tfor ;\n\tWed, 4 Oct 2017 23:37:23 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752011AbdJDMhX (ORCPT );\n\tWed, 4 Oct 2017 08:37:23 -0400","from mail-qk0-f194.google.com ([209.85.220.194]:38379 \"EHLO\n\tmail-qk0-f194.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751962AbdJDMhV (ORCPT\n\t); Wed, 4 Oct 2017 08:37:21 -0400","by mail-qk0-f194.google.com with SMTP id 17so959740qkq.5;\n\tWed, 04 Oct 2017 05:37:21 -0700 (PDT)","by 10.12.190.196 with HTTP; Wed, 4 Oct 2017 05:37:20 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=gmail.com; s=20161025;\n\th=mime-version:in-reply-to:references:from:date:message-id:subject:to\n\t:cc; bh=afCW/OiG44kaXjmjmRcAZzxQZhOi0AnWf0c0AFNj78Q=;\n\tb=Q03wB4UhklG7pWfpwCvdJKYQUcUOKXolbIuFhqlvBsb7xBKD1VFa1kKFgQ8CItS93g\n\tj2GFnyrxNvcXNnGiM1rbmTpaQ81Jaisw7HYL+gyFxBxxkCVr06OoDqVmxENedpboLrZF\n\tHiUGG8TTy1gCHovUtgNhLbBC2ByTgup28aEZzE/KO1XVnL/KJ8H9wo/c7KJMAl9cwHEN\n\t5034iumxsh49fG1MqyJVTv8LrvURYplcFoWfWvFcRN7Qz6rKrF7j3mCdz3KG0kA8TB6A\n\tAyGYVbtgD9Ba5J7qgvNXvvlpsvN0TXY4ex/tFVVelqfllzAMANkrd/BSgNHdoWqBPoed\n\tCa3A==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:mime-version:in-reply-to:references:from:date\n\t:message-id:subject:to:cc;\n\tbh=afCW/OiG44kaXjmjmRcAZzxQZhOi0AnWf0c0AFNj78Q=;\n\tb=M2v98K85nlkpNSJQmGZeOnL7TaqcwyooBp0ozZNX9qFyiQYHsmhH3cM2gUqYv2NSwg\n\togwQjgScC1JvA6j9jVPQpe2eBfiAy0i+kEkK+YEYWVjvoAspdLBE71iQpIENZ7NlR4I6\n\t6pTJkWQRWIg1bXhwtQc9iHRCpPr1YQo+79g6Wo7arRyz5TVLtGaCAhs5KvtsuZ/TwFtL\n\tf2KrPEyJC4VJ0xow50svl9WJDs4HLLabYgIZ4Gs87NlUDLOLXTgN1QzL723AG3rmk5U+\n\thKc1Fj3O9R+UACuk2Ni2jickdIEIT0c4kxCfnlOh3iPygTjagBNzkZyf7WcT0sKnv7oG\n\tbMdQ==","X-Gm-Message-State":"AMCzsaWO3GRKhnRkwX3FQEtvt8gVo/F1cTcQ9EchcqX8rPJzuFFOgcRg\n\tOOwE2GmhnwTLs2ZmNNZFWmzp5FQ5K5BUjzj8He8=","X-Google-Smtp-Source":"AOwi7QCV3klMoPk8jdsx9o/TCdSuSS86+QCLHnuehjn8cehcPtvQTCzxStKIiK5xGTsFBhHNaX9/DuwjpeYWZlVPvHk=","X-Received":"by 10.55.114.195 with SMTP id\n\tn186mr10783263qkc.319.1507120640602; \n\tWed, 04 Oct 2017 05:37:20 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"<5ba5b3d9-b55a-5834-04e5-b4b9a356dca7@linux.intel.com>","References":"\n\t<5286489131571f149c6b75a8367ceb93cfe6e6be.1504588701.git.sathyanarayanan.kuppuswamy@linux.intel.com>\n\t\n\t<5ba5b3d9-b55a-5834-04e5-b4b9a356dca7@linux.intel.com>","From":"Andy Shevchenko ","Date":"Wed, 4 Oct 2017 15:37:20 +0300","Message-ID":"","Subject":"Re: [RFC v3 3/7] platform/x86: intel_pmc_ipc: Use regmap calls for\n\tGCR updates","To":"Kuppuswamy Sathyanarayanan ","Cc":"Alessandro Zummo ,\n\t\"x86@kernel.org\" , Wim Van Sebroeck ,\n\tIngo Molnar ,\n\tAlexandre Belloni ,\n\tZha Qipeng , \"H. Peter Anvin\" ,\n\t\"dvhart@infradead.org\" ,\n\tThomas Gleixner , Lee Jones ,\n\tAndy Shevchenko ,\n\tSouvik Kumar Chakravarty ,\n\tlinux-rtc@vger.kernel.org, linux-watchdog@vger.kernel.org,\n\t\"linux-kernel@vger.kernel.org\" ,\n\tPlatform Driver ,\n\tSathyanarayanan Kuppuswamy Natarajan ","Content-Type":"text/plain; charset=\"UTF-8\"","Sender":"linux-rtc-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-rtc@vger.kernel.org"}}]