[{"id":1777009,"web_url":"http://patchwork.ozlabs.org/comment/1777009/","msgid":"<20170928125519.ol5suebaoqsiixm5@piout.net>","list_archive_url":null,"date":"2017-09-28T12:55:19","subject":"Re: [RFC v3 7/7] platform/x86: intel_scu_ipc: Use generic Intel IPC\n\tdevice calls","submitter":{"id":26276,"url":"http://patchwork.ozlabs.org/api/people/26276/","name":"Alexandre Belloni","email":"alexandre.belloni@free-electrons.com"},"content":"On 04/09/2017 at 22:37:27 -0700, sathyanarayanan.kuppuswamy@linux.intel.com wrote:\n> From: Kuppuswamy Sathyanarayanan \n> \n> Removed redundant IPC helper functions and refactored the driver to use\n> generic IPC device driver APIs.\n> \n> This patch also cleans-up SCU IPC user drivers to use APIs provided\n> by generic IPC driver.\n> \n> Signed-off-by: Kuppuswamy Sathyanarayanan \n\nFor the RTC part:\nAcked-by: Alexandre Belloni \n\n\n> ---\n> arch/x86/include/asm/intel_scu_ipc.h | 23 +-\n> arch/x86/platform/intel-mid/intel-mid.c | 12 +-\n> drivers/platform/x86/Kconfig | 1 +\n> drivers/platform/x86/intel_scu_ipc.c | 483 +++++++++++++-------------------\n> drivers/rtc/rtc-mrst.c | 15 +-\n> drivers/watchdog/intel-mid_wdt.c | 12 +-\n> drivers/watchdog/intel_scu_watchdog.c | 17 +-\n> 7 files changed, 251 insertions(+), 312 deletions(-)\n> \n> diff --git a/arch/x86/include/asm/intel_scu_ipc.h b/arch/x86/include/asm/intel_scu_ipc.h\n> index 81d3d87..5842534 100644\n> --- a/arch/x86/include/asm/intel_scu_ipc.h\n> +++ b/arch/x86/include/asm/intel_scu_ipc.h\n> @@ -14,9 +14,19 @@\n> #define IPCMSG_COLD_BOOT\t0xF3\n> \n> #define IPCMSG_VRTC\t\t0xFA\t /* Set vRTC device */\n> -\t/* Command id associated with message IPCMSG_VRTC */\n> -\t#define IPC_CMD_VRTC_SETTIME 1 /* Set time */\n> -\t#define IPC_CMD_VRTC_SETALARM 2 /* Set alarm */\n> +\n> +/* Command id associated with message IPCMSG_VRTC */\n> +#define IPC_CMD_VRTC_SETTIME 1 /* Set time */\n> +#define IPC_CMD_VRTC_SETALARM 2 /* Set alarm */\n> +\n> +#define INTEL_SCU_IPC_DEV\t\"intel_scu_ipc\"\n> +#define SCU_PARAM_LEN\t\t2\n> +\n> +static inline void scu_cmd_init(u32 *cmd, u32 param1, u32 param2)\n> +{\n> +\tcmd[0] = param1;\n> +\tcmd[1] = param2;\n> +}\n> \n> /* Read single register */\n> int intel_scu_ipc_ioread8(u16 addr, u8 *data);\n> @@ -45,13 +55,6 @@ int intel_scu_ipc_writev(u16 *addr, u8 *data, int len);\n> /* Update single register based on the mask */\n> int intel_scu_ipc_update_register(u16 addr, u8 data, u8 mask);\n> \n> -/* Issue commands to the SCU with or without data */\n> -int intel_scu_ipc_simple_command(int cmd, int sub);\n> -int intel_scu_ipc_command(int cmd, int sub, u32 *in, int inlen,\n> -\t\t\t u32 *out, int outlen);\n> -int intel_scu_ipc_raw_command(int cmd, int sub, u8 *in, int inlen,\n> -\t\t\t u32 *out, int outlen, u32 dptr, u32 sptr);\n> -\n> /* I2C control api */\n> int intel_scu_ipc_i2c_cntrl(u32 addr, u32 *data);\n> \n> diff --git a/arch/x86/platform/intel-mid/intel-mid.c b/arch/x86/platform/intel-mid/intel-mid.c\n> index 12a2725..27541e9 100644\n> --- a/arch/x86/platform/intel-mid/intel-mid.c\n> +++ b/arch/x86/platform/intel-mid/intel-mid.c\n> @@ -22,6 +22,7 @@\n> #include \n> #include \n> #include \n> +#include \n> \n> #include \n> #include \n> @@ -68,18 +69,23 @@ static void *(*get_intel_mid_ops[])(void) = INTEL_MID_OPS_INIT;\n> enum intel_mid_cpu_type __intel_mid_cpu_chip;\n> EXPORT_SYMBOL_GPL(__intel_mid_cpu_chip);\n> \n> +static struct intel_ipc_dev *ipc_dev;\n> +\n> static void intel_mid_power_off(void)\n> {\n> +\tu32 cmds[SCU_PARAM_LEN] = {IPCMSG_COLD_OFF, 1};\n> \t/* Shut down South Complex via PWRMU */\n> \tintel_mid_pwr_power_off();\n> \n> \t/* Only for Tangier, the rest will ignore this command */\n> -\tintel_scu_ipc_simple_command(IPCMSG_COLD_OFF, 1);\n> +\tipc_dev_simple_cmd(ipc_dev, cmds, SCU_PARAM_LEN);\n> };\n> \n> static void intel_mid_reboot(void)\n> {\n> -\tintel_scu_ipc_simple_command(IPCMSG_COLD_BOOT, 0);\n> +\tu32 cmds[SCU_PARAM_LEN] = {IPCMSG_COLD_BOOT, 0};\n> +\n> +\tipc_dev_simple_cmd(ipc_dev, cmds, SCU_PARAM_LEN);\n> }\n> \n> static unsigned long __init intel_mid_calibrate_tsc(void)\n> @@ -206,6 +212,8 @@ void __init x86_intel_mid_early_setup(void)\n> \tx86_init.mpparse.find_smp_config = x86_init_noop;\n> \tx86_init.mpparse.get_smp_config = x86_init_uint_noop;\n> \tset_bit(MP_BUS_ISA, mp_bus_not_pci);\n> +\n> +\tipc_dev = intel_ipc_dev_get(INTEL_SCU_IPC_DEV);\n> }\n> \n> /*\n> diff --git a/drivers/platform/x86/Kconfig b/drivers/platform/x86/Kconfig\n> index 82479ca..e4e5822 100644\n> --- a/drivers/platform/x86/Kconfig\n> +++ b/drivers/platform/x86/Kconfig\n> @@ -850,6 +850,7 @@ config INTEL_VBTN\n> config INTEL_SCU_IPC\n> \tbool \"Intel SCU IPC Support\"\n> \tdepends on X86_INTEL_MID\n> +\tselect REGMAP_MMIO\n> \tdefault y\n> \t---help---\n> \t IPC is used to bridge the communications between kernel and SCU on\n> diff --git a/drivers/platform/x86/intel_scu_ipc.c b/drivers/platform/x86/intel_scu_ipc.c\n> index f7cf981..78013e4 100644\n> --- a/drivers/platform/x86/intel_scu_ipc.c\n> +++ b/drivers/platform/x86/intel_scu_ipc.c\n> @@ -24,6 +24,8 @@\n> #include \n> #include \n> #include \n> +#include \n> +#include \n> #include \n> #include \n> \n> @@ -39,6 +41,25 @@\n> #define IPC_CMD_PCNTRL_R 1 /* Register read */\n> #define IPC_CMD_PCNTRL_M 2 /* Register read-modify-write */\n> \n> +/* IPC dev register offsets */\n> +/*\n> + * IPC Read Buffer (Read Only):\n> + * 16 byte buffer for receiving data from SCU, if IPC command\n> + * processing results in response data\n> + */\n> +#define IPC_DEV_SCU_RBUF_OFFSET\t\t\t0x90\n> +#define IPC_DEV_SCU_WRBUF_OFFSET\t\t0x80\n> +#define IPC_DEV_SCU_SPTR_OFFSET\t\t\t0x08\n> +#define IPC_DEV_SCU_DPTR_OFFSET\t\t\t0x0C\n> +#define IPC_DEV_SCU_STATUS_OFFSET\t\t0x04\n> +\n> +/* IPC dev commands */\n> +/* IPC command register IOC bit */\n> +#define\tIPC_DEV_SCU_CMD_MSI\t\t\tBIT(8)\n> +#define\tIPC_DEV_SCU_CMD_STATUS_ERR\t\tBIT(1)\n> +#define\tIPC_DEV_SCU_CMD_STATUS_ERR_MASK\t\tGENMASK(7, 0)\n> +#define\tIPC_DEV_SCU_CMD_STATUS_BUSY\t\tBIT(0)\n> +\n> /*\n> * IPC register summary\n> *\n> @@ -59,6 +80,11 @@\n> #define IPC_WWBUF_SIZE 20\t\t/* IPC Write buffer Size */\n> #define IPC_RWBUF_SIZE 20\t\t/* IPC Read buffer Size */\n> #define IPC_IOC\t 0x100\t\t/* IPC command register IOC bit */\n> +#define\tIPC_CMD_SIZE 16\n> +#define\tIPC_CMD_SUBCMD 12\n> +#define\tIPC_RWBUF_SIZE_DWORD 5\n> +#define\tIPC_WWBUF_SIZE_DWORD 5\n> +\n> \n> #define PCI_DEVICE_ID_LINCROFT\t\t0x082a\n> #define PCI_DEVICE_ID_PENWELL\t\t0x080e\n> @@ -93,140 +119,49 @@ static struct intel_scu_ipc_pdata_t intel_scu_ipc_tangier_pdata = {\n> \n> struct intel_scu_ipc_dev {\n> \tstruct device *dev;\n> +\tstruct intel_ipc_dev *ipc_dev;\n> \tvoid __iomem *ipc_base;\n> \tvoid __iomem *i2c_base;\n> -\tstruct completion cmd_complete;\n> +\tstruct regmap *ipc_regs;\n> +\tstruct regmap *i2c_regs;\n> \tu8 irq_mode;\n> };\n> \n> -static struct intel_scu_ipc_dev ipcdev; /* Only one for now */\n> +static struct regmap_config ipc_regmap_config = {\n> + .reg_bits = 32,\n> + .reg_stride = 4,\n> + .val_bits = 32,\n> +};\n> \n> -/*\n> - * IPC Read Buffer (Read Only):\n> - * 16 byte buffer for receiving data from SCU, if IPC command\n> - * processing results in response data\n> - */\n> -#define IPC_READ_BUFFER\t\t0x90\n> +static struct regmap_config i2c_regmap_config = {\n> + .reg_bits = 32,\n> + .reg_stride = 4,\n> + .val_bits = 32,\n> +\t.fast_io = true,\n> +};\n> +\n> +static struct intel_scu_ipc_dev ipcdev; /* Only one for now */\n> \n> #define IPC_I2C_CNTRL_ADDR\t0\n> #define I2C_DATA_ADDR\t\t0x04\n> \n> -static DEFINE_MUTEX(ipclock); /* lock used to prevent multiple call to SCU */\n> -\n> -/*\n> - * Send ipc command\n> - * Command Register (Write Only):\n> - * A write to this register results in an interrupt to the SCU core processor\n> - * Format:\n> - * |rfu2(8) | size(8) | command id(4) | rfu1(3) | ioc(1) | command(8)|\n> - */\n> -static inline void ipc_command(struct intel_scu_ipc_dev *scu, u32 cmd)\n> -{\n> -\tif (scu->irq_mode) {\n> -\t\treinit_completion(&scu->cmd_complete);\n> -\t\twritel(cmd | IPC_IOC, scu->ipc_base);\n> -\t}\n> -\twritel(cmd, scu->ipc_base);\n> -}\n> -\n> -/*\n> - * Write ipc data\n> - * IPC Write Buffer (Write Only):\n> - * 16-byte buffer for sending data associated with IPC command to\n> - * SCU. Size of the data is specified in the IPC_COMMAND_REG register\n> - */\n> -static inline void ipc_data_writel(struct intel_scu_ipc_dev *scu, u32 data, u32 offset)\n> -{\n> -\twritel(data, scu->ipc_base + 0x80 + offset);\n> -}\n> -\n> -/*\n> - * Status Register (Read Only):\n> - * Driver will read this register to get the ready/busy status of the IPC\n> - * block and error status of the IPC command that was just processed by SCU\n> - * Format:\n> - * |rfu3(8)|error code(8)|initiator id(8)|cmd id(4)|rfu1(2)|error(1)|busy(1)|\n> - */\n> -static inline u8 ipc_read_status(struct intel_scu_ipc_dev *scu)\n> -{\n> -\treturn __raw_readl(scu->ipc_base + 0x04);\n> -}\n> -\n> -/* Read ipc byte data */\n> -static inline u8 ipc_data_readb(struct intel_scu_ipc_dev *scu, u32 offset)\n> -{\n> -\treturn readb(scu->ipc_base + IPC_READ_BUFFER + offset);\n> -}\n> -\n> -/* Read ipc u32 data */\n> -static inline u32 ipc_data_readl(struct intel_scu_ipc_dev *scu, u32 offset)\n> -{\n> -\treturn readl(scu->ipc_base + IPC_READ_BUFFER + offset);\n> -}\n> -\n> -/* Wait till scu status is busy */\n> -static inline int busy_loop(struct intel_scu_ipc_dev *scu)\n> -{\n> -\tu32 status = ipc_read_status(scu);\n> -\tu32 loop_count = 100000;\n> -\n> -\t/* break if scu doesn't reset busy bit after huge retry */\n> -\twhile ((status & BIT(0)) && --loop_count) {\n> -\t\tudelay(1); /* scu processing time is in few u secods */\n> -\t\tstatus = ipc_read_status(scu);\n> -\t}\n> -\n> -\tif (status & BIT(0)) {\n> -\t\tdev_err(scu->dev, \"IPC timed out\");\n> -\t\treturn -ETIMEDOUT;\n> -\t}\n> -\n> -\tif (status & BIT(1))\n> -\t\treturn -EIO;\n> -\n> -\treturn 0;\n> -}\n> -\n> -/* Wait till ipc ioc interrupt is received or timeout in 3 HZ */\n> -static inline int ipc_wait_for_interrupt(struct intel_scu_ipc_dev *scu)\n> -{\n> -\tint status;\n> -\n> -\tif (!wait_for_completion_timeout(&scu->cmd_complete, 3 * HZ)) {\n> -\t\tdev_err(scu->dev, \"IPC timed out\\n\");\n> -\t\treturn -ETIMEDOUT;\n> -\t}\n> -\n> -\tstatus = ipc_read_status(scu);\n> -\tif (status & BIT(1))\n> -\t\treturn -EIO;\n> -\n> -\treturn 0;\n> -}\n> -\n> -static int intel_scu_ipc_check_status(struct intel_scu_ipc_dev *scu)\n> -{\n> -\treturn scu->irq_mode ? ipc_wait_for_interrupt(scu) : busy_loop(scu);\n> -}\n> -\n> /* Read/Write power control(PMIC in Langwell, MSIC in PenWell) registers */\n> static int pwr_reg_rdwr(u16 *addr, u8 *data, u32 count, u32 op, u32 id)\n> {\n> \tstruct intel_scu_ipc_dev *scu = &ipcdev;\n> \tint nc;\n> \tu32 offset = 0;\n> -\tint err;\n> +\tint err = -EIO;\n> \tu8 cbuf[IPC_WWBUF_SIZE];\n> \tu32 *wbuf = (u32 *)&cbuf;\n> +\tu32 cmd[SCU_PARAM_LEN] = {0};\n> +\t/* max rbuf size is 20 bytes */\n> +\tu8 rbuf[IPC_RWBUF_SIZE] = {0};\n> +\tu32 rbuflen = DIV_ROUND_UP(count, 4);\n> \n> \tmemset(cbuf, 0, sizeof(cbuf));\n> \n> -\tmutex_lock(&ipclock);\n> -\n> -\tif (scu->dev == NULL) {\n> -\t\tmutex_unlock(&ipclock);\n> -\t\treturn -ENODEV;\n> -\t}\n> +\tscu_cmd_init(cmd, op, id);\n> \n> \tfor (nc = 0; nc < count; nc++, offset += 2) {\n> \t\tcbuf[offset] = addr[nc];\n> @@ -234,30 +169,30 @@ static int pwr_reg_rdwr(u16 *addr, u8 *data, u32 count, u32 op, u32 id)\n> \t}\n> \n> \tif (id == IPC_CMD_PCNTRL_R) {\n> -\t\tfor (nc = 0, offset = 0; nc < count; nc++, offset += 4)\n> -\t\t\tipc_data_writel(scu, wbuf[nc], offset);\n> -\t\tipc_command(scu, (count * 2) << 16 | id << 12 | 0 << 8 | op);\n> +\t\terr = ipc_dev_raw_cmd(scu->ipc_dev, cmd, SCU_PARAM_LEN,\n> +\t\t\t\t(u8 *)wbuf, count * 2, (u32 *)rbuf,\n> +\t\t\t\tIPC_RWBUF_SIZE_DWORD, 0, 0);\n> \t} else if (id == IPC_CMD_PCNTRL_W) {\n> \t\tfor (nc = 0; nc < count; nc++, offset += 1)\n> \t\t\tcbuf[offset] = data[nc];\n> -\t\tfor (nc = 0, offset = 0; nc < count; nc++, offset += 4)\n> -\t\t\tipc_data_writel(scu, wbuf[nc], offset);\n> -\t\tipc_command(scu, (count * 3) << 16 | id << 12 | 0 << 8 | op);\n> +\t\terr = ipc_dev_raw_cmd(scu->ipc_dev, cmd, SCU_PARAM_LEN,\n> +\t\t\t\t(u8 *)wbuf, count * 3, NULL, 0, 0, 0);\n> +\n> \t} else if (id == IPC_CMD_PCNTRL_M) {\n> \t\tcbuf[offset] = data[0];\n> \t\tcbuf[offset + 1] = data[1];\n> -\t\tipc_data_writel(scu, wbuf[0], 0); /* Write wbuff */\n> -\t\tipc_command(scu, 4 << 16 | id << 12 | 0 << 8 | op);\n> +\t\terr = ipc_dev_raw_cmd(scu->ipc_dev, cmd, SCU_PARAM_LEN,\n> +\t\t\t\t(u8 *)wbuf, 4, NULL, 0, 0, 0);\n> \t}\n> \n> -\terr = intel_scu_ipc_check_status(scu);\n> \tif (!err && id == IPC_CMD_PCNTRL_R) { /* Read rbuf */\n> \t\t/* Workaround: values are read as 0 without memcpy_fromio */\n> \t\tmemcpy_fromio(cbuf, scu->ipc_base + 0x90, 16);\n> -\t\tfor (nc = 0; nc < count; nc++)\n> -\t\t\tdata[nc] = ipc_data_readb(scu, nc);\n> +\t\tregmap_bulk_read(scu->ipc_regs, IPC_DEV_SCU_RBUF_OFFSET,\n> +\t\t\t\t\trbuf, rbuflen);\n> +\t\tmemcpy(data, rbuf, count);\n> \t}\n> -\tmutex_unlock(&ipclock);\n> +\n> \treturn err;\n> }\n> \n> @@ -422,138 +357,6 @@ int intel_scu_ipc_update_register(u16 addr, u8 bits, u8 mask)\n> }\n> EXPORT_SYMBOL(intel_scu_ipc_update_register);\n> \n> -/**\n> - *\tintel_scu_ipc_simple_command\t-\tsend a simple command\n> - *\t@cmd: command\n> - *\t@sub: sub type\n> - *\n> - *\tIssue a simple command to the SCU. Do not use this interface if\n> - *\tyou must then access data as any data values may be overwritten\n> - *\tby another SCU access by the time this function returns.\n> - *\n> - *\tThis function may sleep. Locking for SCU accesses is handled for\n> - *\tthe caller.\n> - */\n> -int intel_scu_ipc_simple_command(int cmd, int sub)\n> -{\n> -\tstruct intel_scu_ipc_dev *scu = &ipcdev;\n> -\tint err;\n> -\n> -\tmutex_lock(&ipclock);\n> -\tif (scu->dev == NULL) {\n> -\t\tmutex_unlock(&ipclock);\n> -\t\treturn -ENODEV;\n> -\t}\n> -\tipc_command(scu, sub << 12 | cmd);\n> -\terr = intel_scu_ipc_check_status(scu);\n> -\tmutex_unlock(&ipclock);\n> -\treturn err;\n> -}\n> -EXPORT_SYMBOL(intel_scu_ipc_simple_command);\n> -\n> -/**\n> - *\tintel_scu_ipc_command\t-\tcommand with data\n> - *\t@cmd: command\n> - *\t@sub: sub type\n> - *\t@in: input data\n> - *\t@inlen: input length in dwords\n> - *\t@out: output data\n> - *\t@outlein: output length in dwords\n> - *\n> - *\tIssue a command to the SCU which involves data transfers. Do the\n> - *\tdata copies under the lock but leave it for the caller to interpret\n> - */\n> -int intel_scu_ipc_command(int cmd, int sub, u32 *in, int inlen,\n> -\t\t\t u32 *out, int outlen)\n> -{\n> -\tstruct intel_scu_ipc_dev *scu = &ipcdev;\n> -\tint i, err;\n> -\n> -\tmutex_lock(&ipclock);\n> -\tif (scu->dev == NULL) {\n> -\t\tmutex_unlock(&ipclock);\n> -\t\treturn -ENODEV;\n> -\t}\n> -\n> -\tfor (i = 0; i < inlen; i++)\n> -\t\tipc_data_writel(scu, *in++, 4 * i);\n> -\n> -\tipc_command(scu, (inlen << 16) | (sub << 12) | cmd);\n> -\terr = intel_scu_ipc_check_status(scu);\n> -\n> -\tif (!err) {\n> -\t\tfor (i = 0; i < outlen; i++)\n> -\t\t\t*out++ = ipc_data_readl(scu, 4 * i);\n> -\t}\n> -\n> -\tmutex_unlock(&ipclock);\n> -\treturn err;\n> -}\n> -EXPORT_SYMBOL(intel_scu_ipc_command);\n> -\n> -#define IPC_SPTR\t\t0x08\n> -#define IPC_DPTR\t\t0x0C\n> -\n> -/**\n> - * intel_scu_ipc_raw_command() - IPC command with data and pointers\n> - * @cmd:\tIPC command code.\n> - * @sub:\tIPC command sub type.\n> - * @in:\t\tinput data of this IPC command.\n> - * @inlen:\tinput data length in dwords.\n> - * @out:\toutput data of this IPC command.\n> - * @outlen:\toutput data length in dwords.\n> - * @sptr:\tdata writing to SPTR register.\n> - * @dptr:\tdata writing to DPTR register.\n> - *\n> - * Send an IPC command to SCU with input/output data and source/dest pointers.\n> - *\n> - * Return:\tan IPC error code or 0 on success.\n> - */\n> -int intel_scu_ipc_raw_command(int cmd, int sub, u8 *in, int inlen,\n> -\t\t\t u32 *out, int outlen, u32 dptr, u32 sptr)\n> -{\n> -\tstruct intel_scu_ipc_dev *scu = &ipcdev;\n> -\tint inbuflen = DIV_ROUND_UP(inlen, 4);\n> -\tu32 inbuf[4];\n> -\tint i, err;\n> -\n> -\t/* Up to 16 bytes */\n> -\tif (inbuflen > 4)\n> -\t\treturn -EINVAL;\n> -\n> -\tmutex_lock(&ipclock);\n> -\tif (scu->dev == NULL) {\n> -\t\tmutex_unlock(&ipclock);\n> -\t\treturn -ENODEV;\n> -\t}\n> -\n> -\twritel(dptr, scu->ipc_base + IPC_DPTR);\n> -\twritel(sptr, scu->ipc_base + IPC_SPTR);\n> -\n> -\t/*\n> -\t * SRAM controller doesn't support 8-bit writes, it only\n> -\t * supports 32-bit writes, so we have to copy input data into\n> -\t * the temporary buffer, and SCU FW will use the inlen to\n> -\t * determine the actual input data length in the temporary\n> -\t * buffer.\n> -\t */\n> -\tmemcpy(inbuf, in, inlen);\n> -\n> -\tfor (i = 0; i < inbuflen; i++)\n> -\t\tipc_data_writel(scu, inbuf[i], 4 * i);\n> -\n> -\tipc_command(scu, (inlen << 16) | (sub << 12) | cmd);\n> -\terr = intel_scu_ipc_check_status(scu);\n> -\tif (!err) {\n> -\t\tfor (i = 0; i < outlen; i++)\n> -\t\t\t*out++ = ipc_data_readl(scu, 4 * i);\n> -\t}\n> -\n> -\tmutex_unlock(&ipclock);\n> -\treturn err;\n> -}\n> -EXPORT_SYMBOL_GPL(intel_scu_ipc_raw_command);\n> -\n> /* I2C commands */\n> #define IPC_I2C_WRITE 1 /* I2C Write command */\n> #define IPC_I2C_READ 2 /* I2C Read command */\n> @@ -575,48 +378,143 @@ int intel_scu_ipc_i2c_cntrl(u32 addr, u32 *data)\n> \tstruct intel_scu_ipc_dev *scu = &ipcdev;\n> \tu32 cmd = 0;\n> \n> -\tmutex_lock(&ipclock);\n> -\tif (scu->dev == NULL) {\n> -\t\tmutex_unlock(&ipclock);\n> -\t\treturn -ENODEV;\n> -\t}\n> \tcmd = (addr >> 24) & 0xFF;\n> \tif (cmd == IPC_I2C_READ) {\n> -\t\twritel(addr, scu->i2c_base + IPC_I2C_CNTRL_ADDR);\n> +\t\tregmap_write(scu->i2c_regs, IPC_I2C_CNTRL_ADDR, addr);\n> \t\t/* Write not getting updated without delay */\n> \t\tmdelay(1);\n> -\t\t*data = readl(scu->i2c_base + I2C_DATA_ADDR);\n> +\t\tregmap_read(scu->i2c_regs, I2C_DATA_ADDR, data);\n> \t} else if (cmd == IPC_I2C_WRITE) {\n> -\t\twritel(*data, scu->i2c_base + I2C_DATA_ADDR);\n> +\t\tregmap_write(scu->i2c_regs, I2C_DATA_ADDR, *data);\n> \t\tmdelay(1);\n> -\t\twritel(addr, scu->i2c_base + IPC_I2C_CNTRL_ADDR);\n> +\t\tregmap_write(scu->i2c_regs, IPC_I2C_CNTRL_ADDR, addr);\n> \t} else {\n> \t\tdev_err(scu->dev,\n> \t\t\t\"intel_scu_ipc: I2C INVALID_CMD = 0x%x\\n\", cmd);\n> \n> -\t\tmutex_unlock(&ipclock);\n> \t\treturn -EIO;\n> \t}\n> -\tmutex_unlock(&ipclock);\n> \treturn 0;\n> }\n> EXPORT_SYMBOL(intel_scu_ipc_i2c_cntrl);\n> \n> -/*\n> - * Interrupt handler gets called when ioc bit of IPC_COMMAND_REG set to 1\n> - * When ioc bit is set to 1, caller api must wait for interrupt handler called\n> - * which in turn unlocks the caller api. Currently this is not used\n> - *\n> - * This is edge triggered so we need take no action to clear anything\n> - */\n> -static irqreturn_t ioc(int irq, void *dev_id)\n> +static int pre_simple_cmd_fn(u32 *cmd_list, u32 cmdlen)\n> {\n> -\tstruct intel_scu_ipc_dev *scu = dev_id;\n> +\tif (!cmd_list || cmdlen != SCU_PARAM_LEN)\n> +\t\treturn -EINVAL;\n> \n> -\tif (scu->irq_mode)\n> -\t\tcomplete(&scu->cmd_complete);\n> +\tcmd_list[0] |= (cmd_list[1] << IPC_CMD_SUBCMD);\n> \n> -\treturn IRQ_HANDLED;\n> +\treturn 0;\n> +}\n> +\n> +static int pre_cmd_fn(u32 *cmd_list, u32 cmdlen, u32 *in, u32 inlen,\n> +\t\tu32 *out, u32 outlen)\n> +{\n> +\tint ret;\n> +\n> +\tif (inlen > IPC_WWBUF_SIZE_DWORD || outlen > IPC_RWBUF_SIZE_DWORD)\n> +\t\treturn -EINVAL;\n> +\n> +\tret = pre_simple_cmd_fn(cmd_list, cmdlen);\n> +\tif (ret < 0)\n> +\t\treturn ret;\n> +\n> +\tcmd_list[0] |= (inlen << IPC_CMD_SIZE);\n> +\n> +\treturn 0;\n> +}\n> +\n> +static int pre_raw_cmd_fn(u32 *cmd_list, u32 cmdlen, u8 *in, u32 inlen,\n> +\t\tu32 *out, u32 outlen, u32 dptr, u32 sptr)\n> +{\n> +\tint ret;\n> +\n> +\tif (inlen > IPC_WWBUF_SIZE || outlen > IPC_RWBUF_SIZE_DWORD)\n> +\t\treturn -EINVAL;\n> +\n> +\tret = pre_simple_cmd_fn(cmd_list, cmdlen);\n> +\tif (ret < 0)\n> +\t\treturn ret;\n> +\n> +\tcmd_list[0] |= (inlen << IPC_CMD_SIZE);\n> +\n> +\treturn 0;\n> +}\n> +\n> +static int scu_ipc_err_code(int status)\n> +{\n> +\tif (status & IPC_DEV_SCU_CMD_STATUS_ERR)\n> +\t\treturn (status & IPC_DEV_SCU_CMD_STATUS_ERR_MASK);\n> +\telse\n> +\t\treturn 0;\n> +}\n> +\n> +static int scu_ipc_busy_check(int status)\n> +{\n> +\treturn status | IPC_DEV_SCU_CMD_STATUS_BUSY;\n> +}\n> +\n> +static u32 scu_ipc_enable_msi(u32 cmd)\n> +{\n> +\treturn cmd | IPC_DEV_SCU_CMD_MSI;\n> +}\n> +\n> +static struct intel_ipc_dev *intel_scu_ipc_dev_create(\n> +\t\tstruct device *dev,\n> +\t\tvoid __iomem *base,\n> +\t\tint irq)\n> +{\n> +\tstruct intel_ipc_dev_ops *ops;\n> +\tstruct intel_ipc_dev_cfg *cfg;\n> +\tstruct regmap *ipc_regs;\n> +\tstruct intel_scu_ipc_dev *scu = dev_get_drvdata(dev);\n> +\n> +\tcfg = devm_kzalloc(dev, sizeof(*cfg), GFP_KERNEL);\n> +\tif (!cfg)\n> +\t\treturn ERR_PTR(-ENOMEM);\n> +\n> +\tops = devm_kzalloc(dev, sizeof(*ops), GFP_KERNEL);\n> +\tif (!ops)\n> +\t\treturn ERR_PTR(-ENOMEM);\n> +\n> + ipc_regs = devm_regmap_init_mmio_clk(dev, NULL, base,\n> +\t\t\t&ipc_regmap_config);\n> + if (IS_ERR(ipc_regs)) {\n> + dev_err(dev, \"ipc_regs regmap init failed\\n\");\n> + return ERR_CAST(ipc_regs);;\n> + }\n> +\n> +\tscu->ipc_regs = ipc_regs;\n> +\n> +\t/* set IPC dev ops */\n> +\tops->to_err_code = scu_ipc_err_code;\n> +\tops->busy_check = scu_ipc_busy_check;\n> +\tops->enable_msi = scu_ipc_enable_msi;\n> +\tops->pre_cmd_fn = pre_cmd_fn;\n> +\tops->pre_raw_cmd_fn = pre_raw_cmd_fn;\n> +\tops->pre_simple_cmd_fn = pre_simple_cmd_fn;\n> +\n> +\t/* set cfg options */\n> +\tif (scu->irq_mode)\n> +\t\tcfg->mode = IPC_DEV_MODE_IRQ;\n> +\telse\n> +\t\tcfg->mode = IPC_DEV_MODE_POLLING;\n> +\n> +\tcfg->chan_type = IPC_CHANNEL_IA_SCU;\n> +\tcfg->irq = irq;\n> +\tcfg->use_msi = true;\n> +\tcfg->support_sptr = true;\n> +\tcfg->support_dptr = true;\n> +\tcfg->cmd_regs = ipc_regs;\n> +\tcfg->data_regs = ipc_regs;\n> +\tcfg->wrbuf_reg = IPC_DEV_SCU_WRBUF_OFFSET;\n> +\tcfg->rbuf_reg = IPC_DEV_SCU_RBUF_OFFSET;\n> +\tcfg->sptr_reg = IPC_DEV_SCU_SPTR_OFFSET;\n> +\tcfg->dptr_reg = IPC_DEV_SCU_DPTR_OFFSET;\n> +\tcfg->status_reg = IPC_DEV_SCU_STATUS_OFFSET;\n> +\n> +\treturn devm_intel_ipc_dev_create(dev, INTEL_SCU_IPC_DEV, cfg, ops);\n> }\n> \n> /**\n> @@ -650,25 +548,34 @@ static int ipc_probe(struct pci_dev *pdev, const struct pci_device_id *id)\n> \tif (err)\n> \t\treturn err;\n> \n> -\tinit_completion(&scu->cmd_complete);\n> -\n> \tscu->ipc_base = pcim_iomap_table(pdev)[0];\n> \n> -\tscu->i2c_base = ioremap_nocache(pdata->i2c_base, pdata->i2c_len);\n> +\tscu->i2c_base = devm_ioremap_nocache(&pdev->dev, pdata->i2c_base,\n> +\t\t\tpdata->i2c_len);\n> \tif (!scu->i2c_base)\n> \t\treturn -ENOMEM;\n> \n> -\terr = devm_request_irq(&pdev->dev, pdev->irq, ioc, 0, \"intel_scu_ipc\",\n> -\t\t\t scu);\n> -\tif (err)\n> -\t\treturn err;\n> +\tpci_set_drvdata(pdev, scu);\n> +\n> + scu->i2c_regs = devm_regmap_init_mmio_clk(&pdev->dev, NULL,\n> +\t\t\tscu->i2c_base, &i2c_regmap_config);\n> + if (IS_ERR(scu->i2c_regs)) {\n> + dev_err(&pdev->dev, \"i2c_regs regmap init failed\\n\");\n> + return PTR_ERR(scu->i2c_regs);;\n> + }\n> +\n> +\tscu->ipc_dev = intel_scu_ipc_dev_create(&pdev->dev, scu->ipc_base,\n> +\t\t\tpdev->irq);\n> +\tif (IS_ERR(scu->ipc_dev)) {\n> +\t\tdev_err(&pdev->dev, \"Failed to create SCU IPC device\\n\");\n> +\t\treturn PTR_ERR(scu->ipc_dev);\n> +\t}\n> \n> \t/* Assign device at last */\n> \tscu->dev = &pdev->dev;\n> \n> \tintel_scu_devices_create();\n> \n> -\tpci_set_drvdata(pdev, scu);\n> \treturn 0;\n> }\n> \n> diff --git a/drivers/rtc/rtc-mrst.c b/drivers/rtc/rtc-mrst.c\n> index 7334c44..a2d87e8 100644\n> --- a/drivers/rtc/rtc-mrst.c\n> +++ b/drivers/rtc/rtc-mrst.c\n> @@ -36,6 +36,7 @@\n> #include \n> #include \n> #include \n> +#include \n> \n> #include \n> #include \n> @@ -46,6 +47,7 @@ struct mrst_rtc {\n> \tstruct device\t\t*dev;\n> \tint\t\t\tirq;\n> \tstruct resource\t\t*iomem;\n> +\tstruct intel_ipc_dev\t*ipc_dev;\n> \n> \tu8\t\t\tenabled_wake;\n> \tu8\t\t\tsuspend_ctrl;\n> @@ -110,10 +112,11 @@ static int mrst_read_time(struct device *dev, struct rtc_time *time)\n> \n> static int mrst_set_time(struct device *dev, struct rtc_time *time)\n> {\n> -\tint ret;\n> \tunsigned long flags;\n> \tunsigned char mon, day, hrs, min, sec;\n> \tunsigned int yrs;\n> +\tstruct mrst_rtc\t*mrst = dev_get_drvdata(dev);\n> +\tu32 cmds[SCU_PARAM_LEN] = {IPCMSG_VRTC, IPC_CMD_VRTC_SETTIME};\n> \n> \tyrs = time->tm_year;\n> \tmon = time->tm_mon + 1; /* tm_mon starts at zero */\n> @@ -137,8 +140,7 @@ static int mrst_set_time(struct device *dev, struct rtc_time *time)\n> \n> \tspin_unlock_irqrestore(&rtc_lock, flags);\n> \n> -\tret = intel_scu_ipc_simple_command(IPCMSG_VRTC, IPC_CMD_VRTC_SETTIME);\n> -\treturn ret;\n> +\treturn ipc_dev_simple_cmd(mrst->ipc_dev, cmds, SCU_PARAM_LEN);\n> }\n> \n> static int mrst_read_alarm(struct device *dev, struct rtc_wkalrm *t)\n> @@ -210,6 +212,7 @@ static int mrst_set_alarm(struct device *dev, struct rtc_wkalrm *t)\n> \tstruct mrst_rtc\t*mrst = dev_get_drvdata(dev);\n> \tunsigned char hrs, min, sec;\n> \tint ret = 0;\n> +\tu32 cmds[SCU_PARAM_LEN] = {IPCMSG_VRTC, IPC_CMD_VRTC_SETALARM};\n> \n> \tif (!mrst->irq)\n> \t\treturn -EIO;\n> @@ -229,7 +232,7 @@ static int mrst_set_alarm(struct device *dev, struct rtc_wkalrm *t)\n> \n> \tspin_unlock_irq(&rtc_lock);\n> \n> -\tret = intel_scu_ipc_simple_command(IPCMSG_VRTC, IPC_CMD_VRTC_SETALARM);\n> +\tret = ipc_dev_simple_cmd(mrst->ipc_dev, cmds, SCU_PARAM_LEN);\n> \tif (ret)\n> \t\treturn ret;\n> \n> @@ -329,6 +332,10 @@ static int vrtc_mrst_do_probe(struct device *dev, struct resource *iomem,\n> \tif (!iomem)\n> \t\treturn -ENODEV;\n> \n> +\tmrst_rtc.ipc_dev = intel_ipc_dev_get(INTEL_SCU_IPC_DEV);\n> +\tif (IS_ERR_OR_NULL(mrst_rtc.ipc_dev))\n> +\t\treturn PTR_ERR(mrst_rtc.ipc_dev);\n> +\n> \tiomem = request_mem_region(iomem->start, resource_size(iomem),\n> \t\t\t\t driver_name);\n> \tif (!iomem) {\n> diff --git a/drivers/watchdog/intel-mid_wdt.c b/drivers/watchdog/intel-mid_wdt.c\n> index 72c108a..a73559b 100644\n> --- a/drivers/watchdog/intel-mid_wdt.c\n> +++ b/drivers/watchdog/intel-mid_wdt.c\n> @@ -18,6 +18,7 @@\n> #include \n> #include \n> #include \n> +#include \n> \n> #include \n> #include \n> @@ -29,6 +30,8 @@\n> #define MID_WDT_TIMEOUT_MAX\t\t170\n> #define MID_WDT_DEFAULT_TIMEOUT\t\t90\n> \n> +static struct intel_ipc_dev *scu_ipc_dev;\n> +\n> /* SCU watchdog messages */\n> enum {\n> \tSCU_WATCHDOG_START = 0,\n> @@ -38,7 +41,10 @@ enum {\n> \n> static inline int wdt_command(int sub, u32 *in, int inlen)\n> {\n> -\treturn intel_scu_ipc_command(IPC_WATCHDOG, sub, in, inlen, NULL, 0);\n> +\tu32 cmds[SCU_PARAM_LEN] = {IPC_WATCHDOG, sub};\n> +\n> +\treturn ipc_dev_cmd(scu_ipc_dev, cmds, SCU_PARAM_LEN, in,\n> +\t\t\tinlen, NULL, 0);\n> }\n> \n> static int wdt_start(struct watchdog_device *wd)\n> @@ -129,6 +135,10 @@ static int mid_wdt_probe(struct platform_device *pdev)\n> \tif (!wdt_dev)\n> \t\treturn -ENOMEM;\n> \n> +\tscu_ipc_dev = intel_ipc_dev_get(INTEL_SCU_IPC_DEV);\n> +\tif (IS_ERR_OR_NULL(scu_ipc_dev))\n> +\t\treturn PTR_ERR(scu_ipc_dev);\n> +\n> \twdt_dev->info = &mid_wdt_info;\n> \twdt_dev->ops = &mid_wdt_ops;\n> \twdt_dev->min_timeout = MID_WDT_TIMEOUT_MIN;\n> diff --git a/drivers/watchdog/intel_scu_watchdog.c b/drivers/watchdog/intel_scu_watchdog.c\n> index 0caab62..9457c7a 100644\n> --- a/drivers/watchdog/intel_scu_watchdog.c\n> +++ b/drivers/watchdog/intel_scu_watchdog.c\n> @@ -49,6 +49,7 @@\n> #include \n> #include \n> #include \n> +#include \n> \n> #include \"intel_scu_watchdog.h\"\n> \n> @@ -94,6 +95,8 @@ MODULE_PARM_DESC(force_boot,\n> \n> static struct intel_scu_watchdog_dev watchdog_device;\n> \n> +static struct intel_ipc_dev *scu_ipc_dev;\n> +\n> /* Forces restart, if force_reboot is set */\n> static void watchdog_fire(void)\n> {\n> @@ -128,18 +131,14 @@ static int watchdog_set_ipc(int soft_threshold, int threshold)\n> \tu32\t*ipc_wbuf;\n> \tu8\t cbuf[16] = { '\\0' };\n> \tint\t ipc_ret = 0;\n> +\tu32 cmds[SCU_PARAM_LEN] = {IPC_SET_WATCHDOG_TIMER, 0};\n> \n> \tipc_wbuf = (u32 *)&cbuf;\n> \tipc_wbuf[0] = soft_threshold;\n> \tipc_wbuf[1] = threshold;\n> \n> -\tipc_ret = intel_scu_ipc_command(\n> -\t\t\tIPC_SET_WATCHDOG_TIMER,\n> -\t\t\t0,\n> -\t\t\tipc_wbuf,\n> -\t\t\t2,\n> -\t\t\tNULL,\n> -\t\t\t0);\n> +\tipc_ret = ipc_dev_cmd(scu_ipc_dev, cmds, SCU_PARAM_LEN, ipc_wbuf,\n> +\t\t\t2, NULL, 0);\n> \n> \tif (ipc_ret != 0)\n> \t\tpr_err(\"Error setting SCU watchdog timer: %x\\n\", ipc_ret);\n> @@ -460,6 +459,10 @@ static int __init intel_scu_watchdog_init(void)\n> \tif (check_timer_margin(timer_margin))\n> \t\treturn -EINVAL;\n> \n> +\tscu_ipc_dev = intel_ipc_dev_get(INTEL_SCU_IPC_DEV);\n> +\tif (IS_ERR_OR_NULL(scu_ipc_dev))\n> +\t\treturn PTR_ERR(scu_ipc_dev);\n> +\n> \twatchdog_device.timer_tbl_ptr = sfi_get_mtmr(sfi_mtimer_num-1);\n> \n> \tif (watchdog_device.timer_tbl_ptr == NULL) {\n> -- \n> 2.7.4\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-rtc-owner@vger.kernel.org;\n\treceiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2vnF56BRz9tXt\n\tfor ;\n\tThu, 28 Sep 2017 22:55:45 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1753127AbdI1Mzd (ORCPT );\n\tThu, 28 Sep 2017 08:55:33 -0400","from mail.free-electrons.com ([62.4.15.54]:43935 \"EHLO\n\tmail.free-electrons.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1752900AbdI1Mzb (ORCPT\n\t); Thu, 28 Sep 2017 08:55:31 -0400","by mail.free-electrons.com (Postfix, from userid 110)\n\tid D71C820790; Thu, 28 Sep 2017 14:55:28 +0200 (CEST)","from localhost (unknown [37.71.171.242])\n\tby mail.free-electrons.com (Postfix) with ESMTPSA id 9EC92207F7;\n\tThu, 28 Sep 2017 14:55:18 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tmail.free-electrons.com","X-Spam-Level":"","X-Spam-Status":"No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT,\n\tURIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0","Date":"Thu, 28 Sep 2017 14:55:19 +0200","From":"Alexandre Belloni ","To":"sathyanarayanan.kuppuswamy@linux.intel.com","Cc":"a.zummo@towertech.it, x86@kernel.org, wim@iguana.be,\n\tmingo@redhat.com, qipeng.zha@intel.com, hpa@zytor.com,\n\tdvhart@infradead.org, tglx@linutronix.de, lee.jones@linaro.org,\n\tandy@infradead.org, souvik.k.chakravarty@intel.com,\n\tlinux-rtc@vger.kernel.org, linux-watchdog@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org,\n\tsathyaosid@gmail.com","Subject":"Re: [RFC v3 7/7] platform/x86: intel_scu_ipc: Use generic Intel IPC\n\tdevice calls","Message-ID":"<20170928125519.ol5suebaoqsiixm5@piout.net>","References":"\n\t<90f4d15c9ca0430f6ac4cfafe0eaf6ece6c8761c.1504588701.git.sathyanarayanan.kuppuswamy@linux.intel.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<90f4d15c9ca0430f6ac4cfafe0eaf6ece6c8761c.1504588701.git.sathyanarayanan.kuppuswamy@linux.intel.com>","User-Agent":"NeoMutt/20170609 (1.8.3)","Sender":"linux-rtc-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-rtc@vger.kernel.org"}},{"id":1777030,"web_url":"http://patchwork.ozlabs.org/comment/1777030/","msgid":"","list_archive_url":null,"date":"2017-09-28T13:35:18","subject":"Re: [RFC v3 7/7] platform/x86: intel_scu_ipc: Use generic Intel IPC\n\tdevice calls","submitter":{"id":21889,"url":"http://patchwork.ozlabs.org/api/people/21889/","name":"Guenter Roeck","email":"linux@roeck-us.net"},"content":"On 09/28/2017 05:55 AM, Alexandre Belloni wrote:\n> On 04/09/2017 at 22:37:27 -0700, sathyanarayanan.kuppuswamy@linux.intel.com wrote:\n>> From: Kuppuswamy Sathyanarayanan \n>>\n>> Removed redundant IPC helper functions and refactored the driver to use\n>> generic IPC device driver APIs.\n>>\n>> This patch also cleans-up SCU IPC user drivers to use APIs provided\n>> by generic IPC driver.\n>>\n>> Signed-off-by: Kuppuswamy Sathyanarayanan \n> \n> For the RTC part:\n> Acked-by: Alexandre Belloni \n> >\n>> ---\n>> arch/x86/include/asm/intel_scu_ipc.h | 23 +-\n>> arch/x86/platform/intel-mid/intel-mid.c | 12 +-\n>> drivers/platform/x86/Kconfig | 1 +\n>> drivers/platform/x86/intel_scu_ipc.c | 483 +++++++++++++-------------------\n>> drivers/rtc/rtc-mrst.c | 15 +-\n>> drivers/watchdog/intel-mid_wdt.c | 12 +-\n>> drivers/watchdog/intel_scu_watchdog.c | 17 +-\n>> 7 files changed, 251 insertions(+), 312 deletions(-)\n\nI think it would help in general to mention at least in the description which drivers are touched.\n\nI see calls to intel_ipc_dev_get() but not associated put calls. Missing the context, it may\nwell be that those are not necessary, but then how does the ipc code know that the device\nreference is no longer needed ?\n\nGuenter\n\n>>\n>> diff --git a/arch/x86/include/asm/intel_scu_ipc.h b/arch/x86/include/asm/intel_scu_ipc.h\n>> index 81d3d87..5842534 100644\n>> --- a/arch/x86/include/asm/intel_scu_ipc.h\n>> +++ b/arch/x86/include/asm/intel_scu_ipc.h\n>> @@ -14,9 +14,19 @@\n>> #define IPCMSG_COLD_BOOT\t0xF3\n>> \n>> #define IPCMSG_VRTC\t\t0xFA\t /* Set vRTC device */\n>> -\t/* Command id associated with message IPCMSG_VRTC */\n>> -\t#define IPC_CMD_VRTC_SETTIME 1 /* Set time */\n>> -\t#define IPC_CMD_VRTC_SETALARM 2 /* Set alarm */\n>> +\n>> +/* Command id associated with message IPCMSG_VRTC */\n>> +#define IPC_CMD_VRTC_SETTIME 1 /* Set time */\n>> +#define IPC_CMD_VRTC_SETALARM 2 /* Set alarm */\n>> +\n>> +#define INTEL_SCU_IPC_DEV\t\"intel_scu_ipc\"\n>> +#define SCU_PARAM_LEN\t\t2\n>> +\n>> +static inline void scu_cmd_init(u32 *cmd, u32 param1, u32 param2)\n>> +{\n>> +\tcmd[0] = param1;\n>> +\tcmd[1] = param2;\n>> +}\n>> \n>> /* Read single register */\n>> int intel_scu_ipc_ioread8(u16 addr, u8 *data);\n>> @@ -45,13 +55,6 @@ int intel_scu_ipc_writev(u16 *addr, u8 *data, int len);\n>> /* Update single register based on the mask */\n>> int intel_scu_ipc_update_register(u16 addr, u8 data, u8 mask);\n>> \n>> -/* Issue commands to the SCU with or without data */\n>> -int intel_scu_ipc_simple_command(int cmd, int sub);\n>> -int intel_scu_ipc_command(int cmd, int sub, u32 *in, int inlen,\n>> -\t\t\t u32 *out, int outlen);\n>> -int intel_scu_ipc_raw_command(int cmd, int sub, u8 *in, int inlen,\n>> -\t\t\t u32 *out, int outlen, u32 dptr, u32 sptr);\n>> -\n>> /* I2C control api */\n>> int intel_scu_ipc_i2c_cntrl(u32 addr, u32 *data);\n>> \n>> diff --git a/arch/x86/platform/intel-mid/intel-mid.c b/arch/x86/platform/intel-mid/intel-mid.c\n>> index 12a2725..27541e9 100644\n>> --- a/arch/x86/platform/intel-mid/intel-mid.c\n>> +++ b/arch/x86/platform/intel-mid/intel-mid.c\n>> @@ -22,6 +22,7 @@\n>> #include \n>> #include \n>> #include \n>> +#include \n>> \n>> #include \n>> #include \n>> @@ -68,18 +69,23 @@ static void *(*get_intel_mid_ops[])(void) = INTEL_MID_OPS_INIT;\n>> enum intel_mid_cpu_type __intel_mid_cpu_chip;\n>> EXPORT_SYMBOL_GPL(__intel_mid_cpu_chip);\n>> \n>> +static struct intel_ipc_dev *ipc_dev;\n>> +\n>> static void intel_mid_power_off(void)\n>> {\n>> +\tu32 cmds[SCU_PARAM_LEN] = {IPCMSG_COLD_OFF, 1};\n>> \t/* Shut down South Complex via PWRMU */\n>> \tintel_mid_pwr_power_off();\n>> \n>> \t/* Only for Tangier, the rest will ignore this command */\n>> -\tintel_scu_ipc_simple_command(IPCMSG_COLD_OFF, 1);\n>> +\tipc_dev_simple_cmd(ipc_dev, cmds, SCU_PARAM_LEN);\n>> };\n>> \n>> static void intel_mid_reboot(void)\n>> {\n>> -\tintel_scu_ipc_simple_command(IPCMSG_COLD_BOOT, 0);\n>> +\tu32 cmds[SCU_PARAM_LEN] = {IPCMSG_COLD_BOOT, 0};\n>> +\n>> +\tipc_dev_simple_cmd(ipc_dev, cmds, SCU_PARAM_LEN);\n>> }\n>> \n>> static unsigned long __init intel_mid_calibrate_tsc(void)\n>> @@ -206,6 +212,8 @@ void __init x86_intel_mid_early_setup(void)\n>> \tx86_init.mpparse.find_smp_config = x86_init_noop;\n>> \tx86_init.mpparse.get_smp_config = x86_init_uint_noop;\n>> \tset_bit(MP_BUS_ISA, mp_bus_not_pci);\n>> +\n>> +\tipc_dev = intel_ipc_dev_get(INTEL_SCU_IPC_DEV);\n>> }\n>> \n>> /*\n>> diff --git a/drivers/platform/x86/Kconfig b/drivers/platform/x86/Kconfig\n>> index 82479ca..e4e5822 100644\n>> --- a/drivers/platform/x86/Kconfig\n>> +++ b/drivers/platform/x86/Kconfig\n>> @@ -850,6 +850,7 @@ config INTEL_VBTN\n>> config INTEL_SCU_IPC\n>> \tbool \"Intel SCU IPC Support\"\n>> \tdepends on X86_INTEL_MID\n>> +\tselect REGMAP_MMIO\n>> \tdefault y\n>> \t---help---\n>> \t IPC is used to bridge the communications between kernel and SCU on\n>> diff --git a/drivers/platform/x86/intel_scu_ipc.c b/drivers/platform/x86/intel_scu_ipc.c\n>> index f7cf981..78013e4 100644\n>> --- a/drivers/platform/x86/intel_scu_ipc.c\n>> +++ b/drivers/platform/x86/intel_scu_ipc.c\n>> @@ -24,6 +24,8 @@\n>> #include \n>> #include \n>> #include \n>> +#include \n>> +#include \n>> #include \n>> #include \n>> \n>> @@ -39,6 +41,25 @@\n>> #define IPC_CMD_PCNTRL_R 1 /* Register read */\n>> #define IPC_CMD_PCNTRL_M 2 /* Register read-modify-write */\n>> \n>> +/* IPC dev register offsets */\n>> +/*\n>> + * IPC Read Buffer (Read Only):\n>> + * 16 byte buffer for receiving data from SCU, if IPC command\n>> + * processing results in response data\n>> + */\n>> +#define IPC_DEV_SCU_RBUF_OFFSET\t\t\t0x90\n>> +#define IPC_DEV_SCU_WRBUF_OFFSET\t\t0x80\n>> +#define IPC_DEV_SCU_SPTR_OFFSET\t\t\t0x08\n>> +#define IPC_DEV_SCU_DPTR_OFFSET\t\t\t0x0C\n>> +#define IPC_DEV_SCU_STATUS_OFFSET\t\t0x04\n>> +\n>> +/* IPC dev commands */\n>> +/* IPC command register IOC bit */\n>> +#define\tIPC_DEV_SCU_CMD_MSI\t\t\tBIT(8)\n>> +#define\tIPC_DEV_SCU_CMD_STATUS_ERR\t\tBIT(1)\n>> +#define\tIPC_DEV_SCU_CMD_STATUS_ERR_MASK\t\tGENMASK(7, 0)\n>> +#define\tIPC_DEV_SCU_CMD_STATUS_BUSY\t\tBIT(0)\n>> +\n>> /*\n>> * IPC register summary\n>> *\n>> @@ -59,6 +80,11 @@\n>> #define IPC_WWBUF_SIZE 20\t\t/* IPC Write buffer Size */\n>> #define IPC_RWBUF_SIZE 20\t\t/* IPC Read buffer Size */\n>> #define IPC_IOC\t 0x100\t\t/* IPC command register IOC bit */\n>> +#define\tIPC_CMD_SIZE 16\n>> +#define\tIPC_CMD_SUBCMD 12\n>> +#define\tIPC_RWBUF_SIZE_DWORD 5\n>> +#define\tIPC_WWBUF_SIZE_DWORD 5\n>> +\n>> \n>> #define PCI_DEVICE_ID_LINCROFT\t\t0x082a\n>> #define PCI_DEVICE_ID_PENWELL\t\t0x080e\n>> @@ -93,140 +119,49 @@ static struct intel_scu_ipc_pdata_t intel_scu_ipc_tangier_pdata = {\n>> \n>> struct intel_scu_ipc_dev {\n>> \tstruct device *dev;\n>> +\tstruct intel_ipc_dev *ipc_dev;\n>> \tvoid __iomem *ipc_base;\n>> \tvoid __iomem *i2c_base;\n>> -\tstruct completion cmd_complete;\n>> +\tstruct regmap *ipc_regs;\n>> +\tstruct regmap *i2c_regs;\n>> \tu8 irq_mode;\n>> };\n>> \n>> -static struct intel_scu_ipc_dev ipcdev; /* Only one for now */\n>> +static struct regmap_config ipc_regmap_config = {\n>> + .reg_bits = 32,\n>> + .reg_stride = 4,\n>> + .val_bits = 32,\n>> +};\n>> \n>> -/*\n>> - * IPC Read Buffer (Read Only):\n>> - * 16 byte buffer for receiving data from SCU, if IPC command\n>> - * processing results in response data\n>> - */\n>> -#define IPC_READ_BUFFER\t\t0x90\n>> +static struct regmap_config i2c_regmap_config = {\n>> + .reg_bits = 32,\n>> + .reg_stride = 4,\n>> + .val_bits = 32,\n>> +\t.fast_io = true,\n>> +};\n>> +\n>> +static struct intel_scu_ipc_dev ipcdev; /* Only one for now */\n>> \n>> #define IPC_I2C_CNTRL_ADDR\t0\n>> #define I2C_DATA_ADDR\t\t0x04\n>> \n>> -static DEFINE_MUTEX(ipclock); /* lock used to prevent multiple call to SCU */\n>> -\n>> -/*\n>> - * Send ipc command\n>> - * Command Register (Write Only):\n>> - * A write to this register results in an interrupt to the SCU core processor\n>> - * Format:\n>> - * |rfu2(8) | size(8) | command id(4) | rfu1(3) | ioc(1) | command(8)|\n>> - */\n>> -static inline void ipc_command(struct intel_scu_ipc_dev *scu, u32 cmd)\n>> -{\n>> -\tif (scu->irq_mode) {\n>> -\t\treinit_completion(&scu->cmd_complete);\n>> -\t\twritel(cmd | IPC_IOC, scu->ipc_base);\n>> -\t}\n>> -\twritel(cmd, scu->ipc_base);\n>> -}\n>> -\n>> -/*\n>> - * Write ipc data\n>> - * IPC Write Buffer (Write Only):\n>> - * 16-byte buffer for sending data associated with IPC command to\n>> - * SCU. Size of the data is specified in the IPC_COMMAND_REG register\n>> - */\n>> -static inline void ipc_data_writel(struct intel_scu_ipc_dev *scu, u32 data, u32 offset)\n>> -{\n>> -\twritel(data, scu->ipc_base + 0x80 + offset);\n>> -}\n>> -\n>> -/*\n>> - * Status Register (Read Only):\n>> - * Driver will read this register to get the ready/busy status of the IPC\n>> - * block and error status of the IPC command that was just processed by SCU\n>> - * Format:\n>> - * |rfu3(8)|error code(8)|initiator id(8)|cmd id(4)|rfu1(2)|error(1)|busy(1)|\n>> - */\n>> -static inline u8 ipc_read_status(struct intel_scu_ipc_dev *scu)\n>> -{\n>> -\treturn __raw_readl(scu->ipc_base + 0x04);\n>> -}\n>> -\n>> -/* Read ipc byte data */\n>> -static inline u8 ipc_data_readb(struct intel_scu_ipc_dev *scu, u32 offset)\n>> -{\n>> -\treturn readb(scu->ipc_base + IPC_READ_BUFFER + offset);\n>> -}\n>> -\n>> -/* Read ipc u32 data */\n>> -static inline u32 ipc_data_readl(struct intel_scu_ipc_dev *scu, u32 offset)\n>> -{\n>> -\treturn readl(scu->ipc_base + IPC_READ_BUFFER + offset);\n>> -}\n>> -\n>> -/* Wait till scu status is busy */\n>> -static inline int busy_loop(struct intel_scu_ipc_dev *scu)\n>> -{\n>> -\tu32 status = ipc_read_status(scu);\n>> -\tu32 loop_count = 100000;\n>> -\n>> -\t/* break if scu doesn't reset busy bit after huge retry */\n>> -\twhile ((status & BIT(0)) && --loop_count) {\n>> -\t\tudelay(1); /* scu processing time is in few u secods */\n>> -\t\tstatus = ipc_read_status(scu);\n>> -\t}\n>> -\n>> -\tif (status & BIT(0)) {\n>> -\t\tdev_err(scu->dev, \"IPC timed out\");\n>> -\t\treturn -ETIMEDOUT;\n>> -\t}\n>> -\n>> -\tif (status & BIT(1))\n>> -\t\treturn -EIO;\n>> -\n>> -\treturn 0;\n>> -}\n>> -\n>> -/* Wait till ipc ioc interrupt is received or timeout in 3 HZ */\n>> -static inline int ipc_wait_for_interrupt(struct intel_scu_ipc_dev *scu)\n>> -{\n>> -\tint status;\n>> -\n>> -\tif (!wait_for_completion_timeout(&scu->cmd_complete, 3 * HZ)) {\n>> -\t\tdev_err(scu->dev, \"IPC timed out\\n\");\n>> -\t\treturn -ETIMEDOUT;\n>> -\t}\n>> -\n>> -\tstatus = ipc_read_status(scu);\n>> -\tif (status & BIT(1))\n>> -\t\treturn -EIO;\n>> -\n>> -\treturn 0;\n>> -}\n>> -\n>> -static int intel_scu_ipc_check_status(struct intel_scu_ipc_dev *scu)\n>> -{\n>> -\treturn scu->irq_mode ? ipc_wait_for_interrupt(scu) : busy_loop(scu);\n>> -}\n>> -\n>> /* Read/Write power control(PMIC in Langwell, MSIC in PenWell) registers */\n>> static int pwr_reg_rdwr(u16 *addr, u8 *data, u32 count, u32 op, u32 id)\n>> {\n>> \tstruct intel_scu_ipc_dev *scu = &ipcdev;\n>> \tint nc;\n>> \tu32 offset = 0;\n>> -\tint err;\n>> +\tint err = -EIO;\n>> \tu8 cbuf[IPC_WWBUF_SIZE];\n>> \tu32 *wbuf = (u32 *)&cbuf;\n>> +\tu32 cmd[SCU_PARAM_LEN] = {0};\n>> +\t/* max rbuf size is 20 bytes */\n>> +\tu8 rbuf[IPC_RWBUF_SIZE] = {0};\n>> +\tu32 rbuflen = DIV_ROUND_UP(count, 4);\n>> \n>> \tmemset(cbuf, 0, sizeof(cbuf));\n>> \n>> -\tmutex_lock(&ipclock);\n>> -\n>> -\tif (scu->dev == NULL) {\n>> -\t\tmutex_unlock(&ipclock);\n>> -\t\treturn -ENODEV;\n>> -\t}\n>> +\tscu_cmd_init(cmd, op, id);\n>> \n>> \tfor (nc = 0; nc < count; nc++, offset += 2) {\n>> \t\tcbuf[offset] = addr[nc];\n>> @@ -234,30 +169,30 @@ static int pwr_reg_rdwr(u16 *addr, u8 *data, u32 count, u32 op, u32 id)\n>> \t}\n>> \n>> \tif (id == IPC_CMD_PCNTRL_R) {\n>> -\t\tfor (nc = 0, offset = 0; nc < count; nc++, offset += 4)\n>> -\t\t\tipc_data_writel(scu, wbuf[nc], offset);\n>> -\t\tipc_command(scu, (count * 2) << 16 | id << 12 | 0 << 8 | op);\n>> +\t\terr = ipc_dev_raw_cmd(scu->ipc_dev, cmd, SCU_PARAM_LEN,\n>> +\t\t\t\t(u8 *)wbuf, count * 2, (u32 *)rbuf,\n>> +\t\t\t\tIPC_RWBUF_SIZE_DWORD, 0, 0);\n>> \t} else if (id == IPC_CMD_PCNTRL_W) {\n>> \t\tfor (nc = 0; nc < count; nc++, offset += 1)\n>> \t\t\tcbuf[offset] = data[nc];\n>> -\t\tfor (nc = 0, offset = 0; nc < count; nc++, offset += 4)\n>> -\t\t\tipc_data_writel(scu, wbuf[nc], offset);\n>> -\t\tipc_command(scu, (count * 3) << 16 | id << 12 | 0 << 8 | op);\n>> +\t\terr = ipc_dev_raw_cmd(scu->ipc_dev, cmd, SCU_PARAM_LEN,\n>> +\t\t\t\t(u8 *)wbuf, count * 3, NULL, 0, 0, 0);\n>> +\n>> \t} else if (id == IPC_CMD_PCNTRL_M) {\n>> \t\tcbuf[offset] = data[0];\n>> \t\tcbuf[offset + 1] = data[1];\n>> -\t\tipc_data_writel(scu, wbuf[0], 0); /* Write wbuff */\n>> -\t\tipc_command(scu, 4 << 16 | id << 12 | 0 << 8 | op);\n>> +\t\terr = ipc_dev_raw_cmd(scu->ipc_dev, cmd, SCU_PARAM_LEN,\n>> +\t\t\t\t(u8 *)wbuf, 4, NULL, 0, 0, 0);\n>> \t}\n>> \n>> -\terr = intel_scu_ipc_check_status(scu);\n>> \tif (!err && id == IPC_CMD_PCNTRL_R) { /* Read rbuf */\n>> \t\t/* Workaround: values are read as 0 without memcpy_fromio */\n>> \t\tmemcpy_fromio(cbuf, scu->ipc_base + 0x90, 16);\n>> -\t\tfor (nc = 0; nc < count; nc++)\n>> -\t\t\tdata[nc] = ipc_data_readb(scu, nc);\n>> +\t\tregmap_bulk_read(scu->ipc_regs, IPC_DEV_SCU_RBUF_OFFSET,\n>> +\t\t\t\t\trbuf, rbuflen);\n>> +\t\tmemcpy(data, rbuf, count);\n>> \t}\n>> -\tmutex_unlock(&ipclock);\n>> +\n>> \treturn err;\n>> }\n>> \n>> @@ -422,138 +357,6 @@ int intel_scu_ipc_update_register(u16 addr, u8 bits, u8 mask)\n>> }\n>> EXPORT_SYMBOL(intel_scu_ipc_update_register);\n>> \n>> -/**\n>> - *\tintel_scu_ipc_simple_command\t-\tsend a simple command\n>> - *\t@cmd: command\n>> - *\t@sub: sub type\n>> - *\n>> - *\tIssue a simple command to the SCU. Do not use this interface if\n>> - *\tyou must then access data as any data values may be overwritten\n>> - *\tby another SCU access by the time this function returns.\n>> - *\n>> - *\tThis function may sleep. Locking for SCU accesses is handled for\n>> - *\tthe caller.\n>> - */\n>> -int intel_scu_ipc_simple_command(int cmd, int sub)\n>> -{\n>> -\tstruct intel_scu_ipc_dev *scu = &ipcdev;\n>> -\tint err;\n>> -\n>> -\tmutex_lock(&ipclock);\n>> -\tif (scu->dev == NULL) {\n>> -\t\tmutex_unlock(&ipclock);\n>> -\t\treturn -ENODEV;\n>> -\t}\n>> -\tipc_command(scu, sub << 12 | cmd);\n>> -\terr = intel_scu_ipc_check_status(scu);\n>> -\tmutex_unlock(&ipclock);\n>> -\treturn err;\n>> -}\n>> -EXPORT_SYMBOL(intel_scu_ipc_simple_command);\n>> -\n>> -/**\n>> - *\tintel_scu_ipc_command\t-\tcommand with data\n>> - *\t@cmd: command\n>> - *\t@sub: sub type\n>> - *\t@in: input data\n>> - *\t@inlen: input length in dwords\n>> - *\t@out: output data\n>> - *\t@outlein: output length in dwords\n>> - *\n>> - *\tIssue a command to the SCU which involves data transfers. Do the\n>> - *\tdata copies under the lock but leave it for the caller to interpret\n>> - */\n>> -int intel_scu_ipc_command(int cmd, int sub, u32 *in, int inlen,\n>> -\t\t\t u32 *out, int outlen)\n>> -{\n>> -\tstruct intel_scu_ipc_dev *scu = &ipcdev;\n>> -\tint i, err;\n>> -\n>> -\tmutex_lock(&ipclock);\n>> -\tif (scu->dev == NULL) {\n>> -\t\tmutex_unlock(&ipclock);\n>> -\t\treturn -ENODEV;\n>> -\t}\n>> -\n>> -\tfor (i = 0; i < inlen; i++)\n>> -\t\tipc_data_writel(scu, *in++, 4 * i);\n>> -\n>> -\tipc_command(scu, (inlen << 16) | (sub << 12) | cmd);\n>> -\terr = intel_scu_ipc_check_status(scu);\n>> -\n>> -\tif (!err) {\n>> -\t\tfor (i = 0; i < outlen; i++)\n>> -\t\t\t*out++ = ipc_data_readl(scu, 4 * i);\n>> -\t}\n>> -\n>> -\tmutex_unlock(&ipclock);\n>> -\treturn err;\n>> -}\n>> -EXPORT_SYMBOL(intel_scu_ipc_command);\n>> -\n>> -#define IPC_SPTR\t\t0x08\n>> -#define IPC_DPTR\t\t0x0C\n>> -\n>> -/**\n>> - * intel_scu_ipc_raw_command() - IPC command with data and pointers\n>> - * @cmd:\tIPC command code.\n>> - * @sub:\tIPC command sub type.\n>> - * @in:\t\tinput data of this IPC command.\n>> - * @inlen:\tinput data length in dwords.\n>> - * @out:\toutput data of this IPC command.\n>> - * @outlen:\toutput data length in dwords.\n>> - * @sptr:\tdata writing to SPTR register.\n>> - * @dptr:\tdata writing to DPTR register.\n>> - *\n>> - * Send an IPC command to SCU with input/output data and source/dest pointers.\n>> - *\n>> - * Return:\tan IPC error code or 0 on success.\n>> - */\n>> -int intel_scu_ipc_raw_command(int cmd, int sub, u8 *in, int inlen,\n>> -\t\t\t u32 *out, int outlen, u32 dptr, u32 sptr)\n>> -{\n>> -\tstruct intel_scu_ipc_dev *scu = &ipcdev;\n>> -\tint inbuflen = DIV_ROUND_UP(inlen, 4);\n>> -\tu32 inbuf[4];\n>> -\tint i, err;\n>> -\n>> -\t/* Up to 16 bytes */\n>> -\tif (inbuflen > 4)\n>> -\t\treturn -EINVAL;\n>> -\n>> -\tmutex_lock(&ipclock);\n>> -\tif (scu->dev == NULL) {\n>> -\t\tmutex_unlock(&ipclock);\n>> -\t\treturn -ENODEV;\n>> -\t}\n>> -\n>> -\twritel(dptr, scu->ipc_base + IPC_DPTR);\n>> -\twritel(sptr, scu->ipc_base + IPC_SPTR);\n>> -\n>> -\t/*\n>> -\t * SRAM controller doesn't support 8-bit writes, it only\n>> -\t * supports 32-bit writes, so we have to copy input data into\n>> -\t * the temporary buffer, and SCU FW will use the inlen to\n>> -\t * determine the actual input data length in the temporary\n>> -\t * buffer.\n>> -\t */\n>> -\tmemcpy(inbuf, in, inlen);\n>> -\n>> -\tfor (i = 0; i < inbuflen; i++)\n>> -\t\tipc_data_writel(scu, inbuf[i], 4 * i);\n>> -\n>> -\tipc_command(scu, (inlen << 16) | (sub << 12) | cmd);\n>> -\terr = intel_scu_ipc_check_status(scu);\n>> -\tif (!err) {\n>> -\t\tfor (i = 0; i < outlen; i++)\n>> -\t\t\t*out++ = ipc_data_readl(scu, 4 * i);\n>> -\t}\n>> -\n>> -\tmutex_unlock(&ipclock);\n>> -\treturn err;\n>> -}\n>> -EXPORT_SYMBOL_GPL(intel_scu_ipc_raw_command);\n>> -\n>> /* I2C commands */\n>> #define IPC_I2C_WRITE 1 /* I2C Write command */\n>> #define IPC_I2C_READ 2 /* I2C Read command */\n>> @@ -575,48 +378,143 @@ int intel_scu_ipc_i2c_cntrl(u32 addr, u32 *data)\n>> \tstruct intel_scu_ipc_dev *scu = &ipcdev;\n>> \tu32 cmd = 0;\n>> \n>> -\tmutex_lock(&ipclock);\n>> -\tif (scu->dev == NULL) {\n>> -\t\tmutex_unlock(&ipclock);\n>> -\t\treturn -ENODEV;\n>> -\t}\n>> \tcmd = (addr >> 24) & 0xFF;\n>> \tif (cmd == IPC_I2C_READ) {\n>> -\t\twritel(addr, scu->i2c_base + IPC_I2C_CNTRL_ADDR);\n>> +\t\tregmap_write(scu->i2c_regs, IPC_I2C_CNTRL_ADDR, addr);\n>> \t\t/* Write not getting updated without delay */\n>> \t\tmdelay(1);\n>> -\t\t*data = readl(scu->i2c_base + I2C_DATA_ADDR);\n>> +\t\tregmap_read(scu->i2c_regs, I2C_DATA_ADDR, data);\n>> \t} else if (cmd == IPC_I2C_WRITE) {\n>> -\t\twritel(*data, scu->i2c_base + I2C_DATA_ADDR);\n>> +\t\tregmap_write(scu->i2c_regs, I2C_DATA_ADDR, *data);\n>> \t\tmdelay(1);\n>> -\t\twritel(addr, scu->i2c_base + IPC_I2C_CNTRL_ADDR);\n>> +\t\tregmap_write(scu->i2c_regs, IPC_I2C_CNTRL_ADDR, addr);\n>> \t} else {\n>> \t\tdev_err(scu->dev,\n>> \t\t\t\"intel_scu_ipc: I2C INVALID_CMD = 0x%x\\n\", cmd);\n>> \n>> -\t\tmutex_unlock(&ipclock);\n>> \t\treturn -EIO;\n>> \t}\n>> -\tmutex_unlock(&ipclock);\n>> \treturn 0;\n>> }\n>> EXPORT_SYMBOL(intel_scu_ipc_i2c_cntrl);\n>> \n>> -/*\n>> - * Interrupt handler gets called when ioc bit of IPC_COMMAND_REG set to 1\n>> - * When ioc bit is set to 1, caller api must wait for interrupt handler called\n>> - * which in turn unlocks the caller api. Currently this is not used\n>> - *\n>> - * This is edge triggered so we need take no action to clear anything\n>> - */\n>> -static irqreturn_t ioc(int irq, void *dev_id)\n>> +static int pre_simple_cmd_fn(u32 *cmd_list, u32 cmdlen)\n>> {\n>> -\tstruct intel_scu_ipc_dev *scu = dev_id;\n>> +\tif (!cmd_list || cmdlen != SCU_PARAM_LEN)\n>> +\t\treturn -EINVAL;\n>> \n>> -\tif (scu->irq_mode)\n>> -\t\tcomplete(&scu->cmd_complete);\n>> +\tcmd_list[0] |= (cmd_list[1] << IPC_CMD_SUBCMD);\n>> \n>> -\treturn IRQ_HANDLED;\n>> +\treturn 0;\n>> +}\n>> +\n>> +static int pre_cmd_fn(u32 *cmd_list, u32 cmdlen, u32 *in, u32 inlen,\n>> +\t\tu32 *out, u32 outlen)\n>> +{\n>> +\tint ret;\n>> +\n>> +\tif (inlen > IPC_WWBUF_SIZE_DWORD || outlen > IPC_RWBUF_SIZE_DWORD)\n>> +\t\treturn -EINVAL;\n>> +\n>> +\tret = pre_simple_cmd_fn(cmd_list, cmdlen);\n>> +\tif (ret < 0)\n>> +\t\treturn ret;\n>> +\n>> +\tcmd_list[0] |= (inlen << IPC_CMD_SIZE);\n>> +\n>> +\treturn 0;\n>> +}\n>> +\n>> +static int pre_raw_cmd_fn(u32 *cmd_list, u32 cmdlen, u8 *in, u32 inlen,\n>> +\t\tu32 *out, u32 outlen, u32 dptr, u32 sptr)\n>> +{\n>> +\tint ret;\n>> +\n>> +\tif (inlen > IPC_WWBUF_SIZE || outlen > IPC_RWBUF_SIZE_DWORD)\n>> +\t\treturn -EINVAL;\n>> +\n>> +\tret = pre_simple_cmd_fn(cmd_list, cmdlen);\n>> +\tif (ret < 0)\n>> +\t\treturn ret;\n>> +\n>> +\tcmd_list[0] |= (inlen << IPC_CMD_SIZE);\n>> +\n>> +\treturn 0;\n>> +}\n>> +\n>> +static int scu_ipc_err_code(int status)\n>> +{\n>> +\tif (status & IPC_DEV_SCU_CMD_STATUS_ERR)\n>> +\t\treturn (status & IPC_DEV_SCU_CMD_STATUS_ERR_MASK);\n>> +\telse\n>> +\t\treturn 0;\n>> +}\n>> +\n>> +static int scu_ipc_busy_check(int status)\n>> +{\n>> +\treturn status | IPC_DEV_SCU_CMD_STATUS_BUSY;\n>> +}\n>> +\n>> +static u32 scu_ipc_enable_msi(u32 cmd)\n>> +{\n>> +\treturn cmd | IPC_DEV_SCU_CMD_MSI;\n>> +}\n>> +\n>> +static struct intel_ipc_dev *intel_scu_ipc_dev_create(\n>> +\t\tstruct device *dev,\n>> +\t\tvoid __iomem *base,\n>> +\t\tint irq)\n>> +{\n>> +\tstruct intel_ipc_dev_ops *ops;\n>> +\tstruct intel_ipc_dev_cfg *cfg;\n>> +\tstruct regmap *ipc_regs;\n>> +\tstruct intel_scu_ipc_dev *scu = dev_get_drvdata(dev);\n>> +\n>> +\tcfg = devm_kzalloc(dev, sizeof(*cfg), GFP_KERNEL);\n>> +\tif (!cfg)\n>> +\t\treturn ERR_PTR(-ENOMEM);\n>> +\n>> +\tops = devm_kzalloc(dev, sizeof(*ops), GFP_KERNEL);\n>> +\tif (!ops)\n>> +\t\treturn ERR_PTR(-ENOMEM);\n>> +\n>> + ipc_regs = devm_regmap_init_mmio_clk(dev, NULL, base,\n>> +\t\t\t&ipc_regmap_config);\n>> + if (IS_ERR(ipc_regs)) {\n>> + dev_err(dev, \"ipc_regs regmap init failed\\n\");\n>> + return ERR_CAST(ipc_regs);;\n>> + }\n>> +\n>> +\tscu->ipc_regs = ipc_regs;\n>> +\n>> +\t/* set IPC dev ops */\n>> +\tops->to_err_code = scu_ipc_err_code;\n>> +\tops->busy_check = scu_ipc_busy_check;\n>> +\tops->enable_msi = scu_ipc_enable_msi;\n>> +\tops->pre_cmd_fn = pre_cmd_fn;\n>> +\tops->pre_raw_cmd_fn = pre_raw_cmd_fn;\n>> +\tops->pre_simple_cmd_fn = pre_simple_cmd_fn;\n>> +\n>> +\t/* set cfg options */\n>> +\tif (scu->irq_mode)\n>> +\t\tcfg->mode = IPC_DEV_MODE_IRQ;\n>> +\telse\n>> +\t\tcfg->mode = IPC_DEV_MODE_POLLING;\n>> +\n>> +\tcfg->chan_type = IPC_CHANNEL_IA_SCU;\n>> +\tcfg->irq = irq;\n>> +\tcfg->use_msi = true;\n>> +\tcfg->support_sptr = true;\n>> +\tcfg->support_dptr = true;\n>> +\tcfg->cmd_regs = ipc_regs;\n>> +\tcfg->data_regs = ipc_regs;\n>> +\tcfg->wrbuf_reg = IPC_DEV_SCU_WRBUF_OFFSET;\n>> +\tcfg->rbuf_reg = IPC_DEV_SCU_RBUF_OFFSET;\n>> +\tcfg->sptr_reg = IPC_DEV_SCU_SPTR_OFFSET;\n>> +\tcfg->dptr_reg = IPC_DEV_SCU_DPTR_OFFSET;\n>> +\tcfg->status_reg = IPC_DEV_SCU_STATUS_OFFSET;\n>> +\n>> +\treturn devm_intel_ipc_dev_create(dev, INTEL_SCU_IPC_DEV, cfg, ops);\n>> }\n>> \n>> /**\n>> @@ -650,25 +548,34 @@ static int ipc_probe(struct pci_dev *pdev, const struct pci_device_id *id)\n>> \tif (err)\n>> \t\treturn err;\n>> \n>> -\tinit_completion(&scu->cmd_complete);\n>> -\n>> \tscu->ipc_base = pcim_iomap_table(pdev)[0];\n>> \n>> -\tscu->i2c_base = ioremap_nocache(pdata->i2c_base, pdata->i2c_len);\n>> +\tscu->i2c_base = devm_ioremap_nocache(&pdev->dev, pdata->i2c_base,\n>> +\t\t\tpdata->i2c_len);\n>> \tif (!scu->i2c_base)\n>> \t\treturn -ENOMEM;\n>> \n>> -\terr = devm_request_irq(&pdev->dev, pdev->irq, ioc, 0, \"intel_scu_ipc\",\n>> -\t\t\t scu);\n>> -\tif (err)\n>> -\t\treturn err;\n>> +\tpci_set_drvdata(pdev, scu);\n>> +\n>> + scu->i2c_regs = devm_regmap_init_mmio_clk(&pdev->dev, NULL,\n>> +\t\t\tscu->i2c_base, &i2c_regmap_config);\n>> + if (IS_ERR(scu->i2c_regs)) {\n>> + dev_err(&pdev->dev, \"i2c_regs regmap init failed\\n\");\n>> + return PTR_ERR(scu->i2c_regs);;\n>> + }\n>> +\n>> +\tscu->ipc_dev = intel_scu_ipc_dev_create(&pdev->dev, scu->ipc_base,\n>> +\t\t\tpdev->irq);\n>> +\tif (IS_ERR(scu->ipc_dev)) {\n>> +\t\tdev_err(&pdev->dev, \"Failed to create SCU IPC device\\n\");\n>> +\t\treturn PTR_ERR(scu->ipc_dev);\n>> +\t}\n>> \n>> \t/* Assign device at last */\n>> \tscu->dev = &pdev->dev;\n>> \n>> \tintel_scu_devices_create();\n>> \n>> -\tpci_set_drvdata(pdev, scu);\n>> \treturn 0;\n>> }\n>> \n>> diff --git a/drivers/rtc/rtc-mrst.c b/drivers/rtc/rtc-mrst.c\n>> index 7334c44..a2d87e8 100644\n>> --- a/drivers/rtc/rtc-mrst.c\n>> +++ b/drivers/rtc/rtc-mrst.c\n>> @@ -36,6 +36,7 @@\n>> #include \n>> #include \n>> #include \n>> +#include \n>> \n>> #include \n>> #include \n>> @@ -46,6 +47,7 @@ struct mrst_rtc {\n>> \tstruct device\t\t*dev;\n>> \tint\t\t\tirq;\n>> \tstruct resource\t\t*iomem;\n>> +\tstruct intel_ipc_dev\t*ipc_dev;\n>> \n>> \tu8\t\t\tenabled_wake;\n>> \tu8\t\t\tsuspend_ctrl;\n>> @@ -110,10 +112,11 @@ static int mrst_read_time(struct device *dev, struct rtc_time *time)\n>> \n>> static int mrst_set_time(struct device *dev, struct rtc_time *time)\n>> {\n>> -\tint ret;\n>> \tunsigned long flags;\n>> \tunsigned char mon, day, hrs, min, sec;\n>> \tunsigned int yrs;\n>> +\tstruct mrst_rtc\t*mrst = dev_get_drvdata(dev);\n>> +\tu32 cmds[SCU_PARAM_LEN] = {IPCMSG_VRTC, IPC_CMD_VRTC_SETTIME};\n>> \n>> \tyrs = time->tm_year;\n>> \tmon = time->tm_mon + 1; /* tm_mon starts at zero */\n>> @@ -137,8 +140,7 @@ static int mrst_set_time(struct device *dev, struct rtc_time *time)\n>> \n>> \tspin_unlock_irqrestore(&rtc_lock, flags);\n>> \n>> -\tret = intel_scu_ipc_simple_command(IPCMSG_VRTC, IPC_CMD_VRTC_SETTIME);\n>> -\treturn ret;\n>> +\treturn ipc_dev_simple_cmd(mrst->ipc_dev, cmds, SCU_PARAM_LEN);\n>> }\n>> \n>> static int mrst_read_alarm(struct device *dev, struct rtc_wkalrm *t)\n>> @@ -210,6 +212,7 @@ static int mrst_set_alarm(struct device *dev, struct rtc_wkalrm *t)\n>> \tstruct mrst_rtc\t*mrst = dev_get_drvdata(dev);\n>> \tunsigned char hrs, min, sec;\n>> \tint ret = 0;\n>> +\tu32 cmds[SCU_PARAM_LEN] = {IPCMSG_VRTC, IPC_CMD_VRTC_SETALARM};\n>> \n>> \tif (!mrst->irq)\n>> \t\treturn -EIO;\n>> @@ -229,7 +232,7 @@ static int mrst_set_alarm(struct device *dev, struct rtc_wkalrm *t)\n>> \n>> \tspin_unlock_irq(&rtc_lock);\n>> \n>> -\tret = intel_scu_ipc_simple_command(IPCMSG_VRTC, IPC_CMD_VRTC_SETALARM);\n>> +\tret = ipc_dev_simple_cmd(mrst->ipc_dev, cmds, SCU_PARAM_LEN);\n>> \tif (ret)\n>> \t\treturn ret;\n>> \n>> @@ -329,6 +332,10 @@ static int vrtc_mrst_do_probe(struct device *dev, struct resource *iomem,\n>> \tif (!iomem)\n>> \t\treturn -ENODEV;\n>> \n>> +\tmrst_rtc.ipc_dev = intel_ipc_dev_get(INTEL_SCU_IPC_DEV);\n>> +\tif (IS_ERR_OR_NULL(mrst_rtc.ipc_dev))\n>> +\t\treturn PTR_ERR(mrst_rtc.ipc_dev);\n>> +\n>> \tiomem = request_mem_region(iomem->start, resource_size(iomem),\n>> \t\t\t\t driver_name);\n>> \tif (!iomem) {\n>> diff --git a/drivers/watchdog/intel-mid_wdt.c b/drivers/watchdog/intel-mid_wdt.c\n>> index 72c108a..a73559b 100644\n>> --- a/drivers/watchdog/intel-mid_wdt.c\n>> +++ b/drivers/watchdog/intel-mid_wdt.c\n>> @@ -18,6 +18,7 @@\n>> #include \n>> #include \n>> #include \n>> +#include \n>> \n>> #include \n>> #include \n>> @@ -29,6 +30,8 @@\n>> #define MID_WDT_TIMEOUT_MAX\t\t170\n>> #define MID_WDT_DEFAULT_TIMEOUT\t\t90\n>> \n>> +static struct intel_ipc_dev *scu_ipc_dev;\n>> +\n>> /* SCU watchdog messages */\n>> enum {\n>> \tSCU_WATCHDOG_START = 0,\n>> @@ -38,7 +41,10 @@ enum {\n>> \n>> static inline int wdt_command(int sub, u32 *in, int inlen)\n>> {\n>> -\treturn intel_scu_ipc_command(IPC_WATCHDOG, sub, in, inlen, NULL, 0);\n>> +\tu32 cmds[SCU_PARAM_LEN] = {IPC_WATCHDOG, sub};\n>> +\n>> +\treturn ipc_dev_cmd(scu_ipc_dev, cmds, SCU_PARAM_LEN, in,\n>> +\t\t\tinlen, NULL, 0);\n>> }\n>> \n>> static int wdt_start(struct watchdog_device *wd)\n>> @@ -129,6 +135,10 @@ static int mid_wdt_probe(struct platform_device *pdev)\n>> \tif (!wdt_dev)\n>> \t\treturn -ENOMEM;\n>> \n>> +\tscu_ipc_dev = intel_ipc_dev_get(INTEL_SCU_IPC_DEV);\n>> +\tif (IS_ERR_OR_NULL(scu_ipc_dev))\n>> +\t\treturn PTR_ERR(scu_ipc_dev);\n>> +\n>> \twdt_dev->info = &mid_wdt_info;\n>> \twdt_dev->ops = &mid_wdt_ops;\n>> \twdt_dev->min_timeout = MID_WDT_TIMEOUT_MIN;\n>> diff --git a/drivers/watchdog/intel_scu_watchdog.c b/drivers/watchdog/intel_scu_watchdog.c\n>> index 0caab62..9457c7a 100644\n>> --- a/drivers/watchdog/intel_scu_watchdog.c\n>> +++ b/drivers/watchdog/intel_scu_watchdog.c\n>> @@ -49,6 +49,7 @@\n>> #include \n>> #include \n>> #include \n>> +#include \n>> \n>> #include \"intel_scu_watchdog.h\"\n>> \n>> @@ -94,6 +95,8 @@ MODULE_PARM_DESC(force_boot,\n>> \n>> static struct intel_scu_watchdog_dev watchdog_device;\n>> \n>> +static struct intel_ipc_dev *scu_ipc_dev;\n>> +\n>> /* Forces restart, if force_reboot is set */\n>> static void watchdog_fire(void)\n>> {\n>> @@ -128,18 +131,14 @@ static int watchdog_set_ipc(int soft_threshold, int threshold)\n>> \tu32\t*ipc_wbuf;\n>> \tu8\t cbuf[16] = { '\\0' };\n>> \tint\t ipc_ret = 0;\n>> +\tu32 cmds[SCU_PARAM_LEN] = {IPC_SET_WATCHDOG_TIMER, 0};\n>> \n>> \tipc_wbuf = (u32 *)&cbuf;\n>> \tipc_wbuf[0] = soft_threshold;\n>> \tipc_wbuf[1] = threshold;\n>> \n>> -\tipc_ret = intel_scu_ipc_command(\n>> -\t\t\tIPC_SET_WATCHDOG_TIMER,\n>> -\t\t\t0,\n>> -\t\t\tipc_wbuf,\n>> -\t\t\t2,\n>> -\t\t\tNULL,\n>> -\t\t\t0);\n>> +\tipc_ret = ipc_dev_cmd(scu_ipc_dev, cmds, SCU_PARAM_LEN, ipc_wbuf,\n>> +\t\t\t2, NULL, 0);\n>> \n>> \tif (ipc_ret != 0)\n>> \t\tpr_err(\"Error setting SCU watchdog timer: %x\\n\", ipc_ret);\n>> @@ -460,6 +459,10 @@ static int __init intel_scu_watchdog_init(void)\n>> \tif (check_timer_margin(timer_margin))\n>> \t\treturn -EINVAL;\n>> \n>> +\tscu_ipc_dev = intel_ipc_dev_get(INTEL_SCU_IPC_DEV);\n>> +\tif (IS_ERR_OR_NULL(scu_ipc_dev))\n>> +\t\treturn PTR_ERR(scu_ipc_dev);\n>> +\n>> \twatchdog_device.timer_tbl_ptr = sfi_get_mtmr(sfi_mtimer_num-1);\n>> \n>> \tif (watchdog_device.timer_tbl_ptr == NULL) {\n>> -- \n>> 2.7.4\n>>\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; 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generic Intel IPC\n\tdevice calls","To":"Alexandre Belloni ,\n\tsathyanarayanan.kuppuswamy@linux.intel.com","Cc":"a.zummo@towertech.it, x86@kernel.org, wim@iguana.be,\n\tmingo@redhat.com, qipeng.zha@intel.com, hpa@zytor.com,\n\tdvhart@infradead.org, tglx@linutronix.de, lee.jones@linaro.org,\n\tandy@infradead.org, souvik.k.chakravarty@intel.com,\n\tlinux-rtc@vger.kernel.org, linux-watchdog@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org,\n\tsathyaosid@gmail.com","References":"\n\t<90f4d15c9ca0430f6ac4cfafe0eaf6ece6c8761c.1504588701.git.sathyanarayanan.kuppuswamy@linux.intel.com>\n\t<20170928125519.ol5suebaoqsiixm5@piout.net>","From":"Guenter Roeck ","Message-ID":"","Date":"Thu, 28 Sep 2017 06:35:18 -0700","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<20170928125519.ol5suebaoqsiixm5@piout.net>","Content-Type":"text/plain; charset=utf-8; format=flowed","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","Sender":"linux-rtc-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-rtc@vger.kernel.org"}},{"id":1779329,"web_url":"http://patchwork.ozlabs.org/comment/1779329/","msgid":"<965bdd3b-74a7-07ca-bba2-90e14f1e8bbe@linux.intel.com>","list_archive_url":null,"date":"2017-10-04T00:32:02","subject":"Re: [RFC v3 7/7] platform/x86: intel_scu_ipc: Use generic Intel IPC\n\tdevice calls","submitter":{"id":66129,"url":"http://patchwork.ozlabs.org/api/people/66129/","name":"Kuppuswamy Sathyanarayanan","email":"sathyanarayanan.kuppuswamy@linux.intel.com"},"content":"Hi Alexandre,\n\n\nOn 09/28/2017 05:55 AM, Alexandre Belloni wrote:\n> On 04/09/2017 at 22:37:27 -0700, sathyanarayanan.kuppuswamy@linux.intel.com wrote:\n>> From: Kuppuswamy Sathyanarayanan \n>>\n>> Removed redundant IPC helper functions and refactored the driver to use\n>> generic IPC device driver APIs.\n>>\n>> This patch also cleans-up SCU IPC user drivers to use APIs provided\n>> by generic IPC driver.\n>>\n>> Signed-off-by: Kuppuswamy Sathyanarayanan \n> For the RTC part:\n> Acked-by: Alexandre Belloni \nThanks for the review.\n>\n>\n>> ---\n>> arch/x86/include/asm/intel_scu_ipc.h | 23 +-\n>> arch/x86/platform/intel-mid/intel-mid.c | 12 +-\n>> drivers/platform/x86/Kconfig | 1 +\n>> drivers/platform/x86/intel_scu_ipc.c | 483 +++++++++++++-------------------\n>> drivers/rtc/rtc-mrst.c | 15 +-\n>> drivers/watchdog/intel-mid_wdt.c | 12 +-\n>> drivers/watchdog/intel_scu_watchdog.c | 17 +-\n>> 7 files changed, 251 insertions(+), 312 deletions(-)\n>>\n>> diff --git a/arch/x86/include/asm/intel_scu_ipc.h b/arch/x86/include/asm/intel_scu_ipc.h\n>> index 81d3d87..5842534 100644\n>> --- a/arch/x86/include/asm/intel_scu_ipc.h\n>> +++ b/arch/x86/include/asm/intel_scu_ipc.h\n>> @@ -14,9 +14,19 @@\n>> #define IPCMSG_COLD_BOOT\t0xF3\n>> \n>> #define IPCMSG_VRTC\t\t0xFA\t /* Set vRTC device */\n>> -\t/* Command id associated with message IPCMSG_VRTC */\n>> -\t#define IPC_CMD_VRTC_SETTIME 1 /* Set time */\n>> -\t#define IPC_CMD_VRTC_SETALARM 2 /* Set alarm */\n>> +\n>> +/* Command id associated with message IPCMSG_VRTC */\n>> +#define IPC_CMD_VRTC_SETTIME 1 /* Set time */\n>> +#define IPC_CMD_VRTC_SETALARM 2 /* Set alarm */\n>> +\n>> +#define INTEL_SCU_IPC_DEV\t\"intel_scu_ipc\"\n>> +#define SCU_PARAM_LEN\t\t2\n>> +\n>> +static inline void scu_cmd_init(u32 *cmd, u32 param1, u32 param2)\n>> +{\n>> +\tcmd[0] = param1;\n>> +\tcmd[1] = param2;\n>> +}\n>> \n>> /* Read single register */\n>> int intel_scu_ipc_ioread8(u16 addr, u8 *data);\n>> @@ -45,13 +55,6 @@ int intel_scu_ipc_writev(u16 *addr, u8 *data, int len);\n>> /* Update single register based on the mask */\n>> int intel_scu_ipc_update_register(u16 addr, u8 data, u8 mask);\n>> \n>> -/* Issue commands to the SCU with or without data */\n>> -int intel_scu_ipc_simple_command(int cmd, int sub);\n>> -int intel_scu_ipc_command(int cmd, int sub, u32 *in, int inlen,\n>> -\t\t\t u32 *out, int outlen);\n>> -int intel_scu_ipc_raw_command(int cmd, int sub, u8 *in, int inlen,\n>> -\t\t\t u32 *out, int outlen, u32 dptr, u32 sptr);\n>> -\n>> /* I2C control api */\n>> int intel_scu_ipc_i2c_cntrl(u32 addr, u32 *data);\n>> \n>> diff --git a/arch/x86/platform/intel-mid/intel-mid.c b/arch/x86/platform/intel-mid/intel-mid.c\n>> index 12a2725..27541e9 100644\n>> --- a/arch/x86/platform/intel-mid/intel-mid.c\n>> +++ b/arch/x86/platform/intel-mid/intel-mid.c\n>> @@ -22,6 +22,7 @@\n>> #include \n>> #include \n>> #include \n>> +#include \n>> \n>> #include \n>> #include \n>> @@ -68,18 +69,23 @@ static void *(*get_intel_mid_ops[])(void) = INTEL_MID_OPS_INIT;\n>> enum intel_mid_cpu_type __intel_mid_cpu_chip;\n>> EXPORT_SYMBOL_GPL(__intel_mid_cpu_chip);\n>> \n>> +static struct intel_ipc_dev *ipc_dev;\n>> +\n>> static void intel_mid_power_off(void)\n>> {\n>> +\tu32 cmds[SCU_PARAM_LEN] = {IPCMSG_COLD_OFF, 1};\n>> \t/* Shut down South Complex via PWRMU */\n>> \tintel_mid_pwr_power_off();\n>> \n>> \t/* Only for Tangier, the rest will ignore this command */\n>> -\tintel_scu_ipc_simple_command(IPCMSG_COLD_OFF, 1);\n>> +\tipc_dev_simple_cmd(ipc_dev, cmds, SCU_PARAM_LEN);\n>> };\n>> \n>> static void intel_mid_reboot(void)\n>> {\n>> -\tintel_scu_ipc_simple_command(IPCMSG_COLD_BOOT, 0);\n>> +\tu32 cmds[SCU_PARAM_LEN] = {IPCMSG_COLD_BOOT, 0};\n>> +\n>> +\tipc_dev_simple_cmd(ipc_dev, cmds, SCU_PARAM_LEN);\n>> }\n>> \n>> static unsigned long __init intel_mid_calibrate_tsc(void)\n>> @@ -206,6 +212,8 @@ void __init x86_intel_mid_early_setup(void)\n>> \tx86_init.mpparse.find_smp_config = x86_init_noop;\n>> \tx86_init.mpparse.get_smp_config = x86_init_uint_noop;\n>> \tset_bit(MP_BUS_ISA, mp_bus_not_pci);\n>> +\n>> +\tipc_dev = intel_ipc_dev_get(INTEL_SCU_IPC_DEV);\n>> }\n>> \n>> /*\n>> diff --git a/drivers/platform/x86/Kconfig b/drivers/platform/x86/Kconfig\n>> index 82479ca..e4e5822 100644\n>> --- a/drivers/platform/x86/Kconfig\n>> +++ b/drivers/platform/x86/Kconfig\n>> @@ -850,6 +850,7 @@ config INTEL_VBTN\n>> config INTEL_SCU_IPC\n>> \tbool \"Intel SCU IPC Support\"\n>> \tdepends on X86_INTEL_MID\n>> +\tselect REGMAP_MMIO\n>> \tdefault y\n>> \t---help---\n>> \t IPC is used to bridge the communications between kernel and SCU on\n>> diff --git a/drivers/platform/x86/intel_scu_ipc.c b/drivers/platform/x86/intel_scu_ipc.c\n>> index f7cf981..78013e4 100644\n>> --- a/drivers/platform/x86/intel_scu_ipc.c\n>> +++ b/drivers/platform/x86/intel_scu_ipc.c\n>> @@ -24,6 +24,8 @@\n>> #include \n>> #include \n>> #include \n>> +#include \n>> +#include \n>> #include \n>> #include \n>> \n>> @@ -39,6 +41,25 @@\n>> #define IPC_CMD_PCNTRL_R 1 /* Register read */\n>> #define IPC_CMD_PCNTRL_M 2 /* Register read-modify-write */\n>> \n>> +/* IPC dev register offsets */\n>> +/*\n>> + * IPC Read Buffer (Read Only):\n>> + * 16 byte buffer for receiving data from SCU, if IPC command\n>> + * processing results in response data\n>> + */\n>> +#define IPC_DEV_SCU_RBUF_OFFSET\t\t\t0x90\n>> +#define IPC_DEV_SCU_WRBUF_OFFSET\t\t0x80\n>> +#define IPC_DEV_SCU_SPTR_OFFSET\t\t\t0x08\n>> +#define IPC_DEV_SCU_DPTR_OFFSET\t\t\t0x0C\n>> +#define IPC_DEV_SCU_STATUS_OFFSET\t\t0x04\n>> +\n>> +/* IPC dev commands */\n>> +/* IPC command register IOC bit */\n>> +#define\tIPC_DEV_SCU_CMD_MSI\t\t\tBIT(8)\n>> +#define\tIPC_DEV_SCU_CMD_STATUS_ERR\t\tBIT(1)\n>> +#define\tIPC_DEV_SCU_CMD_STATUS_ERR_MASK\t\tGENMASK(7, 0)\n>> +#define\tIPC_DEV_SCU_CMD_STATUS_BUSY\t\tBIT(0)\n>> +\n>> /*\n>> * IPC register summary\n>> *\n>> @@ -59,6 +80,11 @@\n>> #define IPC_WWBUF_SIZE 20\t\t/* IPC Write buffer Size */\n>> #define IPC_RWBUF_SIZE 20\t\t/* IPC Read buffer Size */\n>> #define IPC_IOC\t 0x100\t\t/* IPC command register IOC bit */\n>> +#define\tIPC_CMD_SIZE 16\n>> +#define\tIPC_CMD_SUBCMD 12\n>> +#define\tIPC_RWBUF_SIZE_DWORD 5\n>> +#define\tIPC_WWBUF_SIZE_DWORD 5\n>> +\n>> \n>> #define PCI_DEVICE_ID_LINCROFT\t\t0x082a\n>> #define PCI_DEVICE_ID_PENWELL\t\t0x080e\n>> @@ -93,140 +119,49 @@ static struct intel_scu_ipc_pdata_t intel_scu_ipc_tangier_pdata = {\n>> \n>> struct intel_scu_ipc_dev {\n>> \tstruct device *dev;\n>> +\tstruct intel_ipc_dev *ipc_dev;\n>> \tvoid __iomem *ipc_base;\n>> \tvoid __iomem *i2c_base;\n>> -\tstruct completion cmd_complete;\n>> +\tstruct regmap *ipc_regs;\n>> +\tstruct regmap *i2c_regs;\n>> \tu8 irq_mode;\n>> };\n>> \n>> -static struct intel_scu_ipc_dev ipcdev; /* Only one for now */\n>> +static struct regmap_config ipc_regmap_config = {\n>> + .reg_bits = 32,\n>> + .reg_stride = 4,\n>> + .val_bits = 32,\n>> +};\n>> \n>> -/*\n>> - * IPC Read Buffer (Read Only):\n>> - * 16 byte buffer for receiving data from SCU, if IPC command\n>> - * processing results in response data\n>> - */\n>> -#define IPC_READ_BUFFER\t\t0x90\n>> +static struct regmap_config i2c_regmap_config = {\n>> + .reg_bits = 32,\n>> + .reg_stride = 4,\n>> + .val_bits = 32,\n>> +\t.fast_io = true,\n>> +};\n>> +\n>> +static struct intel_scu_ipc_dev ipcdev; /* Only one for now */\n>> \n>> #define IPC_I2C_CNTRL_ADDR\t0\n>> #define I2C_DATA_ADDR\t\t0x04\n>> \n>> -static DEFINE_MUTEX(ipclock); /* lock used to prevent multiple call to SCU */\n>> -\n>> -/*\n>> - * Send ipc command\n>> - * Command Register (Write Only):\n>> - * A write to this register results in an interrupt to the SCU core processor\n>> - * Format:\n>> - * |rfu2(8) | size(8) | command id(4) | rfu1(3) | ioc(1) | command(8)|\n>> - */\n>> -static inline void ipc_command(struct intel_scu_ipc_dev *scu, u32 cmd)\n>> -{\n>> -\tif (scu->irq_mode) {\n>> -\t\treinit_completion(&scu->cmd_complete);\n>> -\t\twritel(cmd | IPC_IOC, scu->ipc_base);\n>> -\t}\n>> -\twritel(cmd, scu->ipc_base);\n>> -}\n>> -\n>> -/*\n>> - * Write ipc data\n>> - * IPC Write Buffer (Write Only):\n>> - * 16-byte buffer for sending data associated with IPC command to\n>> - * SCU. Size of the data is specified in the IPC_COMMAND_REG register\n>> - */\n>> -static inline void ipc_data_writel(struct intel_scu_ipc_dev *scu, u32 data, u32 offset)\n>> -{\n>> -\twritel(data, scu->ipc_base + 0x80 + offset);\n>> -}\n>> -\n>> -/*\n>> - * Status Register (Read Only):\n>> - * Driver will read this register to get the ready/busy status of the IPC\n>> - * block and error status of the IPC command that was just processed by SCU\n>> - * Format:\n>> - * |rfu3(8)|error code(8)|initiator id(8)|cmd id(4)|rfu1(2)|error(1)|busy(1)|\n>> - */\n>> -static inline u8 ipc_read_status(struct intel_scu_ipc_dev *scu)\n>> -{\n>> -\treturn __raw_readl(scu->ipc_base + 0x04);\n>> -}\n>> -\n>> -/* Read ipc byte data */\n>> -static inline u8 ipc_data_readb(struct intel_scu_ipc_dev *scu, u32 offset)\n>> -{\n>> -\treturn readb(scu->ipc_base + IPC_READ_BUFFER + offset);\n>> -}\n>> -\n>> -/* Read ipc u32 data */\n>> -static inline u32 ipc_data_readl(struct intel_scu_ipc_dev *scu, u32 offset)\n>> -{\n>> -\treturn readl(scu->ipc_base + IPC_READ_BUFFER + offset);\n>> -}\n>> -\n>> -/* Wait till scu status is busy */\n>> -static inline int busy_loop(struct intel_scu_ipc_dev *scu)\n>> -{\n>> -\tu32 status = ipc_read_status(scu);\n>> -\tu32 loop_count = 100000;\n>> -\n>> -\t/* break if scu doesn't reset busy bit after huge retry */\n>> -\twhile ((status & BIT(0)) && --loop_count) {\n>> -\t\tudelay(1); /* scu processing time is in few u secods */\n>> -\t\tstatus = ipc_read_status(scu);\n>> -\t}\n>> -\n>> -\tif (status & BIT(0)) {\n>> -\t\tdev_err(scu->dev, \"IPC timed out\");\n>> -\t\treturn -ETIMEDOUT;\n>> -\t}\n>> -\n>> -\tif (status & BIT(1))\n>> -\t\treturn -EIO;\n>> -\n>> -\treturn 0;\n>> -}\n>> -\n>> -/* Wait till ipc ioc interrupt is received or timeout in 3 HZ */\n>> -static inline int ipc_wait_for_interrupt(struct intel_scu_ipc_dev *scu)\n>> -{\n>> -\tint status;\n>> -\n>> -\tif (!wait_for_completion_timeout(&scu->cmd_complete, 3 * HZ)) {\n>> -\t\tdev_err(scu->dev, \"IPC timed out\\n\");\n>> -\t\treturn -ETIMEDOUT;\n>> -\t}\n>> -\n>> -\tstatus = ipc_read_status(scu);\n>> -\tif (status & BIT(1))\n>> -\t\treturn -EIO;\n>> -\n>> -\treturn 0;\n>> -}\n>> -\n>> -static int intel_scu_ipc_check_status(struct intel_scu_ipc_dev *scu)\n>> -{\n>> -\treturn scu->irq_mode ? ipc_wait_for_interrupt(scu) : busy_loop(scu);\n>> -}\n>> -\n>> /* Read/Write power control(PMIC in Langwell, MSIC in PenWell) registers */\n>> static int pwr_reg_rdwr(u16 *addr, u8 *data, u32 count, u32 op, u32 id)\n>> {\n>> \tstruct intel_scu_ipc_dev *scu = &ipcdev;\n>> \tint nc;\n>> \tu32 offset = 0;\n>> -\tint err;\n>> +\tint err = -EIO;\n>> \tu8 cbuf[IPC_WWBUF_SIZE];\n>> \tu32 *wbuf = (u32 *)&cbuf;\n>> +\tu32 cmd[SCU_PARAM_LEN] = {0};\n>> +\t/* max rbuf size is 20 bytes */\n>> +\tu8 rbuf[IPC_RWBUF_SIZE] = {0};\n>> +\tu32 rbuflen = DIV_ROUND_UP(count, 4);\n>> \n>> \tmemset(cbuf, 0, sizeof(cbuf));\n>> \n>> -\tmutex_lock(&ipclock);\n>> -\n>> -\tif (scu->dev == NULL) {\n>> -\t\tmutex_unlock(&ipclock);\n>> -\t\treturn -ENODEV;\n>> -\t}\n>> +\tscu_cmd_init(cmd, op, id);\n>> \n>> \tfor (nc = 0; nc < count; nc++, offset += 2) {\n>> \t\tcbuf[offset] = addr[nc];\n>> @@ -234,30 +169,30 @@ static int pwr_reg_rdwr(u16 *addr, u8 *data, u32 count, u32 op, u32 id)\n>> \t}\n>> \n>> \tif (id == IPC_CMD_PCNTRL_R) {\n>> -\t\tfor (nc = 0, offset = 0; nc < count; nc++, offset += 4)\n>> -\t\t\tipc_data_writel(scu, wbuf[nc], offset);\n>> -\t\tipc_command(scu, (count * 2) << 16 | id << 12 | 0 << 8 | op);\n>> +\t\terr = ipc_dev_raw_cmd(scu->ipc_dev, cmd, SCU_PARAM_LEN,\n>> +\t\t\t\t(u8 *)wbuf, count * 2, (u32 *)rbuf,\n>> +\t\t\t\tIPC_RWBUF_SIZE_DWORD, 0, 0);\n>> \t} else if (id == IPC_CMD_PCNTRL_W) {\n>> \t\tfor (nc = 0; nc < count; nc++, offset += 1)\n>> \t\t\tcbuf[offset] = data[nc];\n>> -\t\tfor (nc = 0, offset = 0; nc < count; nc++, offset += 4)\n>> -\t\t\tipc_data_writel(scu, wbuf[nc], offset);\n>> -\t\tipc_command(scu, (count * 3) << 16 | id << 12 | 0 << 8 | op);\n>> +\t\terr = ipc_dev_raw_cmd(scu->ipc_dev, cmd, SCU_PARAM_LEN,\n>> +\t\t\t\t(u8 *)wbuf, count * 3, NULL, 0, 0, 0);\n>> +\n>> \t} else if (id == IPC_CMD_PCNTRL_M) {\n>> \t\tcbuf[offset] = data[0];\n>> \t\tcbuf[offset + 1] = data[1];\n>> -\t\tipc_data_writel(scu, wbuf[0], 0); /* Write wbuff */\n>> -\t\tipc_command(scu, 4 << 16 | id << 12 | 0 << 8 | op);\n>> +\t\terr = ipc_dev_raw_cmd(scu->ipc_dev, cmd, SCU_PARAM_LEN,\n>> +\t\t\t\t(u8 *)wbuf, 4, NULL, 0, 0, 0);\n>> \t}\n>> \n>> -\terr = intel_scu_ipc_check_status(scu);\n>> \tif (!err && id == IPC_CMD_PCNTRL_R) { /* Read rbuf */\n>> \t\t/* Workaround: values are read as 0 without memcpy_fromio */\n>> \t\tmemcpy_fromio(cbuf, scu->ipc_base + 0x90, 16);\n>> -\t\tfor (nc = 0; nc < count; nc++)\n>> -\t\t\tdata[nc] = ipc_data_readb(scu, nc);\n>> +\t\tregmap_bulk_read(scu->ipc_regs, IPC_DEV_SCU_RBUF_OFFSET,\n>> +\t\t\t\t\trbuf, rbuflen);\n>> +\t\tmemcpy(data, rbuf, count);\n>> \t}\n>> -\tmutex_unlock(&ipclock);\n>> +\n>> \treturn err;\n>> }\n>> \n>> @@ -422,138 +357,6 @@ int intel_scu_ipc_update_register(u16 addr, u8 bits, u8 mask)\n>> }\n>> EXPORT_SYMBOL(intel_scu_ipc_update_register);\n>> \n>> -/**\n>> - *\tintel_scu_ipc_simple_command\t-\tsend a simple command\n>> - *\t@cmd: command\n>> - *\t@sub: sub type\n>> - *\n>> - *\tIssue a simple command to the SCU. Do not use this interface if\n>> - *\tyou must then access data as any data values may be overwritten\n>> - *\tby another SCU access by the time this function returns.\n>> - *\n>> - *\tThis function may sleep. Locking for SCU accesses is handled for\n>> - *\tthe caller.\n>> - */\n>> -int intel_scu_ipc_simple_command(int cmd, int sub)\n>> -{\n>> -\tstruct intel_scu_ipc_dev *scu = &ipcdev;\n>> -\tint err;\n>> -\n>> -\tmutex_lock(&ipclock);\n>> -\tif (scu->dev == NULL) {\n>> -\t\tmutex_unlock(&ipclock);\n>> -\t\treturn -ENODEV;\n>> -\t}\n>> -\tipc_command(scu, sub << 12 | cmd);\n>> -\terr = intel_scu_ipc_check_status(scu);\n>> -\tmutex_unlock(&ipclock);\n>> -\treturn err;\n>> -}\n>> -EXPORT_SYMBOL(intel_scu_ipc_simple_command);\n>> -\n>> -/**\n>> - *\tintel_scu_ipc_command\t-\tcommand with data\n>> - *\t@cmd: command\n>> - *\t@sub: sub type\n>> - *\t@in: input data\n>> - *\t@inlen: input length in dwords\n>> - *\t@out: output data\n>> - *\t@outlein: output length in dwords\n>> - *\n>> - *\tIssue a command to the SCU which involves data transfers. Do the\n>> - *\tdata copies under the lock but leave it for the caller to interpret\n>> - */\n>> -int intel_scu_ipc_command(int cmd, int sub, u32 *in, int inlen,\n>> -\t\t\t u32 *out, int outlen)\n>> -{\n>> -\tstruct intel_scu_ipc_dev *scu = &ipcdev;\n>> -\tint i, err;\n>> -\n>> -\tmutex_lock(&ipclock);\n>> -\tif (scu->dev == NULL) {\n>> -\t\tmutex_unlock(&ipclock);\n>> -\t\treturn -ENODEV;\n>> -\t}\n>> -\n>> -\tfor (i = 0; i < inlen; i++)\n>> -\t\tipc_data_writel(scu, *in++, 4 * i);\n>> -\n>> -\tipc_command(scu, (inlen << 16) | (sub << 12) | cmd);\n>> -\terr = intel_scu_ipc_check_status(scu);\n>> -\n>> -\tif (!err) {\n>> -\t\tfor (i = 0; i < outlen; i++)\n>> -\t\t\t*out++ = ipc_data_readl(scu, 4 * i);\n>> -\t}\n>> -\n>> -\tmutex_unlock(&ipclock);\n>> -\treturn err;\n>> -}\n>> -EXPORT_SYMBOL(intel_scu_ipc_command);\n>> -\n>> -#define IPC_SPTR\t\t0x08\n>> -#define IPC_DPTR\t\t0x0C\n>> -\n>> -/**\n>> - * intel_scu_ipc_raw_command() - IPC command with data and pointers\n>> - * @cmd:\tIPC command code.\n>> - * @sub:\tIPC command sub type.\n>> - * @in:\t\tinput data of this IPC command.\n>> - * @inlen:\tinput data length in dwords.\n>> - * @out:\toutput data of this IPC command.\n>> - * @outlen:\toutput data length in dwords.\n>> - * @sptr:\tdata writing to SPTR register.\n>> - * @dptr:\tdata writing to DPTR register.\n>> - *\n>> - * Send an IPC command to SCU with input/output data and source/dest pointers.\n>> - *\n>> - * Return:\tan IPC error code or 0 on success.\n>> - */\n>> -int intel_scu_ipc_raw_command(int cmd, int sub, u8 *in, int inlen,\n>> -\t\t\t u32 *out, int outlen, u32 dptr, u32 sptr)\n>> -{\n>> -\tstruct intel_scu_ipc_dev *scu = &ipcdev;\n>> -\tint inbuflen = DIV_ROUND_UP(inlen, 4);\n>> -\tu32 inbuf[4];\n>> -\tint i, err;\n>> -\n>> -\t/* Up to 16 bytes */\n>> -\tif (inbuflen > 4)\n>> -\t\treturn -EINVAL;\n>> -\n>> -\tmutex_lock(&ipclock);\n>> -\tif (scu->dev == NULL) {\n>> -\t\tmutex_unlock(&ipclock);\n>> -\t\treturn -ENODEV;\n>> -\t}\n>> -\n>> -\twritel(dptr, scu->ipc_base + IPC_DPTR);\n>> -\twritel(sptr, scu->ipc_base + IPC_SPTR);\n>> -\n>> -\t/*\n>> -\t * SRAM controller doesn't support 8-bit writes, it only\n>> -\t * supports 32-bit writes, so we have to copy input data into\n>> -\t * the temporary buffer, and SCU FW will use the inlen to\n>> -\t * determine the actual input data length in the temporary\n>> -\t * buffer.\n>> -\t */\n>> -\tmemcpy(inbuf, in, inlen);\n>> -\n>> -\tfor (i = 0; i < inbuflen; i++)\n>> -\t\tipc_data_writel(scu, inbuf[i], 4 * i);\n>> -\n>> -\tipc_command(scu, (inlen << 16) | (sub << 12) | cmd);\n>> -\terr = intel_scu_ipc_check_status(scu);\n>> -\tif (!err) {\n>> -\t\tfor (i = 0; i < outlen; i++)\n>> -\t\t\t*out++ = ipc_data_readl(scu, 4 * i);\n>> -\t}\n>> -\n>> -\tmutex_unlock(&ipclock);\n>> -\treturn err;\n>> -}\n>> -EXPORT_SYMBOL_GPL(intel_scu_ipc_raw_command);\n>> -\n>> /* I2C commands */\n>> #define IPC_I2C_WRITE 1 /* I2C Write command */\n>> #define IPC_I2C_READ 2 /* I2C Read command */\n>> @@ -575,48 +378,143 @@ int intel_scu_ipc_i2c_cntrl(u32 addr, u32 *data)\n>> \tstruct intel_scu_ipc_dev *scu = &ipcdev;\n>> \tu32 cmd = 0;\n>> \n>> -\tmutex_lock(&ipclock);\n>> -\tif (scu->dev == NULL) {\n>> -\t\tmutex_unlock(&ipclock);\n>> -\t\treturn -ENODEV;\n>> -\t}\n>> \tcmd = (addr >> 24) & 0xFF;\n>> \tif (cmd == IPC_I2C_READ) {\n>> -\t\twritel(addr, scu->i2c_base + IPC_I2C_CNTRL_ADDR);\n>> +\t\tregmap_write(scu->i2c_regs, IPC_I2C_CNTRL_ADDR, addr);\n>> \t\t/* Write not getting updated without delay */\n>> \t\tmdelay(1);\n>> -\t\t*data = readl(scu->i2c_base + I2C_DATA_ADDR);\n>> +\t\tregmap_read(scu->i2c_regs, I2C_DATA_ADDR, data);\n>> \t} else if (cmd == IPC_I2C_WRITE) {\n>> -\t\twritel(*data, scu->i2c_base + I2C_DATA_ADDR);\n>> +\t\tregmap_write(scu->i2c_regs, I2C_DATA_ADDR, *data);\n>> \t\tmdelay(1);\n>> -\t\twritel(addr, scu->i2c_base + IPC_I2C_CNTRL_ADDR);\n>> +\t\tregmap_write(scu->i2c_regs, IPC_I2C_CNTRL_ADDR, addr);\n>> \t} else {\n>> \t\tdev_err(scu->dev,\n>> \t\t\t\"intel_scu_ipc: I2C INVALID_CMD = 0x%x\\n\", cmd);\n>> \n>> -\t\tmutex_unlock(&ipclock);\n>> \t\treturn -EIO;\n>> \t}\n>> -\tmutex_unlock(&ipclock);\n>> \treturn 0;\n>> }\n>> EXPORT_SYMBOL(intel_scu_ipc_i2c_cntrl);\n>> \n>> -/*\n>> - * Interrupt handler gets called when ioc bit of IPC_COMMAND_REG set to 1\n>> - * When ioc bit is set to 1, caller api must wait for interrupt handler called\n>> - * which in turn unlocks the caller api. Currently this is not used\n>> - *\n>> - * This is edge triggered so we need take no action to clear anything\n>> - */\n>> -static irqreturn_t ioc(int irq, void *dev_id)\n>> +static int pre_simple_cmd_fn(u32 *cmd_list, u32 cmdlen)\n>> {\n>> -\tstruct intel_scu_ipc_dev *scu = dev_id;\n>> +\tif (!cmd_list || cmdlen != SCU_PARAM_LEN)\n>> +\t\treturn -EINVAL;\n>> \n>> -\tif (scu->irq_mode)\n>> -\t\tcomplete(&scu->cmd_complete);\n>> +\tcmd_list[0] |= (cmd_list[1] << IPC_CMD_SUBCMD);\n>> \n>> -\treturn IRQ_HANDLED;\n>> +\treturn 0;\n>> +}\n>> +\n>> +static int pre_cmd_fn(u32 *cmd_list, u32 cmdlen, u32 *in, u32 inlen,\n>> +\t\tu32 *out, u32 outlen)\n>> +{\n>> +\tint ret;\n>> +\n>> +\tif (inlen > IPC_WWBUF_SIZE_DWORD || outlen > IPC_RWBUF_SIZE_DWORD)\n>> +\t\treturn -EINVAL;\n>> +\n>> +\tret = pre_simple_cmd_fn(cmd_list, cmdlen);\n>> +\tif (ret < 0)\n>> +\t\treturn ret;\n>> +\n>> +\tcmd_list[0] |= (inlen << IPC_CMD_SIZE);\n>> +\n>> +\treturn 0;\n>> +}\n>> +\n>> +static int pre_raw_cmd_fn(u32 *cmd_list, u32 cmdlen, u8 *in, u32 inlen,\n>> +\t\tu32 *out, u32 outlen, u32 dptr, u32 sptr)\n>> +{\n>> +\tint ret;\n>> +\n>> +\tif (inlen > IPC_WWBUF_SIZE || outlen > IPC_RWBUF_SIZE_DWORD)\n>> +\t\treturn -EINVAL;\n>> +\n>> +\tret = pre_simple_cmd_fn(cmd_list, cmdlen);\n>> +\tif (ret < 0)\n>> +\t\treturn ret;\n>> +\n>> +\tcmd_list[0] |= (inlen << IPC_CMD_SIZE);\n>> +\n>> +\treturn 0;\n>> +}\n>> +\n>> +static int scu_ipc_err_code(int status)\n>> +{\n>> +\tif (status & IPC_DEV_SCU_CMD_STATUS_ERR)\n>> +\t\treturn (status & IPC_DEV_SCU_CMD_STATUS_ERR_MASK);\n>> +\telse\n>> +\t\treturn 0;\n>> +}\n>> +\n>> +static int scu_ipc_busy_check(int status)\n>> +{\n>> +\treturn status | IPC_DEV_SCU_CMD_STATUS_BUSY;\n>> +}\n>> +\n>> +static u32 scu_ipc_enable_msi(u32 cmd)\n>> +{\n>> +\treturn cmd | IPC_DEV_SCU_CMD_MSI;\n>> +}\n>> +\n>> +static struct intel_ipc_dev *intel_scu_ipc_dev_create(\n>> +\t\tstruct device *dev,\n>> +\t\tvoid __iomem *base,\n>> +\t\tint irq)\n>> +{\n>> +\tstruct intel_ipc_dev_ops *ops;\n>> +\tstruct intel_ipc_dev_cfg *cfg;\n>> +\tstruct regmap *ipc_regs;\n>> +\tstruct intel_scu_ipc_dev *scu = dev_get_drvdata(dev);\n>> +\n>> +\tcfg = devm_kzalloc(dev, sizeof(*cfg), GFP_KERNEL);\n>> +\tif (!cfg)\n>> +\t\treturn ERR_PTR(-ENOMEM);\n>> +\n>> +\tops = devm_kzalloc(dev, sizeof(*ops), GFP_KERNEL);\n>> +\tif (!ops)\n>> +\t\treturn ERR_PTR(-ENOMEM);\n>> +\n>> + ipc_regs = devm_regmap_init_mmio_clk(dev, NULL, base,\n>> +\t\t\t&ipc_regmap_config);\n>> + if (IS_ERR(ipc_regs)) {\n>> + dev_err(dev, \"ipc_regs regmap init failed\\n\");\n>> + return ERR_CAST(ipc_regs);;\n>> + }\n>> +\n>> +\tscu->ipc_regs = ipc_regs;\n>> +\n>> +\t/* set IPC dev ops */\n>> +\tops->to_err_code = scu_ipc_err_code;\n>> +\tops->busy_check = scu_ipc_busy_check;\n>> +\tops->enable_msi = scu_ipc_enable_msi;\n>> +\tops->pre_cmd_fn = pre_cmd_fn;\n>> +\tops->pre_raw_cmd_fn = pre_raw_cmd_fn;\n>> +\tops->pre_simple_cmd_fn = pre_simple_cmd_fn;\n>> +\n>> +\t/* set cfg options */\n>> +\tif (scu->irq_mode)\n>> +\t\tcfg->mode = IPC_DEV_MODE_IRQ;\n>> +\telse\n>> +\t\tcfg->mode = IPC_DEV_MODE_POLLING;\n>> +\n>> +\tcfg->chan_type = IPC_CHANNEL_IA_SCU;\n>> +\tcfg->irq = irq;\n>> +\tcfg->use_msi = true;\n>> +\tcfg->support_sptr = true;\n>> +\tcfg->support_dptr = true;\n>> +\tcfg->cmd_regs = ipc_regs;\n>> +\tcfg->data_regs = ipc_regs;\n>> +\tcfg->wrbuf_reg = IPC_DEV_SCU_WRBUF_OFFSET;\n>> +\tcfg->rbuf_reg = IPC_DEV_SCU_RBUF_OFFSET;\n>> +\tcfg->sptr_reg = IPC_DEV_SCU_SPTR_OFFSET;\n>> +\tcfg->dptr_reg = IPC_DEV_SCU_DPTR_OFFSET;\n>> +\tcfg->status_reg = IPC_DEV_SCU_STATUS_OFFSET;\n>> +\n>> +\treturn devm_intel_ipc_dev_create(dev, INTEL_SCU_IPC_DEV, cfg, ops);\n>> }\n>> \n>> /**\n>> @@ -650,25 +548,34 @@ static int ipc_probe(struct pci_dev *pdev, const struct pci_device_id *id)\n>> \tif (err)\n>> \t\treturn err;\n>> \n>> -\tinit_completion(&scu->cmd_complete);\n>> -\n>> \tscu->ipc_base = pcim_iomap_table(pdev)[0];\n>> \n>> -\tscu->i2c_base = ioremap_nocache(pdata->i2c_base, pdata->i2c_len);\n>> +\tscu->i2c_base = devm_ioremap_nocache(&pdev->dev, pdata->i2c_base,\n>> +\t\t\tpdata->i2c_len);\n>> \tif (!scu->i2c_base)\n>> \t\treturn -ENOMEM;\n>> \n>> -\terr = devm_request_irq(&pdev->dev, pdev->irq, ioc, 0, \"intel_scu_ipc\",\n>> -\t\t\t scu);\n>> -\tif (err)\n>> -\t\treturn err;\n>> +\tpci_set_drvdata(pdev, scu);\n>> +\n>> + scu->i2c_regs = devm_regmap_init_mmio_clk(&pdev->dev, NULL,\n>> +\t\t\tscu->i2c_base, &i2c_regmap_config);\n>> + if (IS_ERR(scu->i2c_regs)) {\n>> + dev_err(&pdev->dev, \"i2c_regs regmap init failed\\n\");\n>> + return PTR_ERR(scu->i2c_regs);;\n>> + }\n>> +\n>> +\tscu->ipc_dev = intel_scu_ipc_dev_create(&pdev->dev, scu->ipc_base,\n>> +\t\t\tpdev->irq);\n>> +\tif (IS_ERR(scu->ipc_dev)) {\n>> +\t\tdev_err(&pdev->dev, \"Failed to create SCU IPC device\\n\");\n>> +\t\treturn PTR_ERR(scu->ipc_dev);\n>> +\t}\n>> \n>> \t/* Assign device at last */\n>> \tscu->dev = &pdev->dev;\n>> \n>> \tintel_scu_devices_create();\n>> \n>> -\tpci_set_drvdata(pdev, scu);\n>> \treturn 0;\n>> }\n>> \n>> diff --git a/drivers/rtc/rtc-mrst.c b/drivers/rtc/rtc-mrst.c\n>> index 7334c44..a2d87e8 100644\n>> --- a/drivers/rtc/rtc-mrst.c\n>> +++ b/drivers/rtc/rtc-mrst.c\n>> @@ -36,6 +36,7 @@\n>> #include \n>> #include \n>> #include \n>> +#include \n>> \n>> #include \n>> #include \n>> @@ -46,6 +47,7 @@ struct mrst_rtc {\n>> \tstruct device\t\t*dev;\n>> \tint\t\t\tirq;\n>> \tstruct resource\t\t*iomem;\n>> +\tstruct intel_ipc_dev\t*ipc_dev;\n>> \n>> \tu8\t\t\tenabled_wake;\n>> \tu8\t\t\tsuspend_ctrl;\n>> @@ -110,10 +112,11 @@ static int mrst_read_time(struct device *dev, struct rtc_time *time)\n>> \n>> static int mrst_set_time(struct device *dev, struct rtc_time *time)\n>> {\n>> -\tint ret;\n>> \tunsigned long flags;\n>> \tunsigned char mon, day, hrs, min, sec;\n>> \tunsigned int yrs;\n>> +\tstruct mrst_rtc\t*mrst = dev_get_drvdata(dev);\n>> +\tu32 cmds[SCU_PARAM_LEN] = {IPCMSG_VRTC, IPC_CMD_VRTC_SETTIME};\n>> \n>> \tyrs = time->tm_year;\n>> \tmon = time->tm_mon + 1; /* tm_mon starts at zero */\n>> @@ -137,8 +140,7 @@ static int mrst_set_time(struct device *dev, struct rtc_time *time)\n>> \n>> \tspin_unlock_irqrestore(&rtc_lock, flags);\n>> \n>> -\tret = intel_scu_ipc_simple_command(IPCMSG_VRTC, IPC_CMD_VRTC_SETTIME);\n>> -\treturn ret;\n>> +\treturn ipc_dev_simple_cmd(mrst->ipc_dev, cmds, SCU_PARAM_LEN);\n>> }\n>> \n>> static int mrst_read_alarm(struct device *dev, struct rtc_wkalrm *t)\n>> @@ -210,6 +212,7 @@ static int mrst_set_alarm(struct device *dev, struct rtc_wkalrm *t)\n>> \tstruct mrst_rtc\t*mrst = dev_get_drvdata(dev);\n>> \tunsigned char hrs, min, sec;\n>> \tint ret = 0;\n>> +\tu32 cmds[SCU_PARAM_LEN] = {IPCMSG_VRTC, IPC_CMD_VRTC_SETALARM};\n>> \n>> \tif (!mrst->irq)\n>> \t\treturn -EIO;\n>> @@ -229,7 +232,7 @@ static int mrst_set_alarm(struct device *dev, struct rtc_wkalrm *t)\n>> \n>> \tspin_unlock_irq(&rtc_lock);\n>> \n>> -\tret = intel_scu_ipc_simple_command(IPCMSG_VRTC, IPC_CMD_VRTC_SETALARM);\n>> +\tret = ipc_dev_simple_cmd(mrst->ipc_dev, cmds, SCU_PARAM_LEN);\n>> \tif (ret)\n>> \t\treturn ret;\n>> \n>> @@ -329,6 +332,10 @@ static int vrtc_mrst_do_probe(struct device *dev, struct resource *iomem,\n>> \tif (!iomem)\n>> \t\treturn -ENODEV;\n>> \n>> +\tmrst_rtc.ipc_dev = intel_ipc_dev_get(INTEL_SCU_IPC_DEV);\n>> +\tif (IS_ERR_OR_NULL(mrst_rtc.ipc_dev))\n>> +\t\treturn PTR_ERR(mrst_rtc.ipc_dev);\n>> +\n>> \tiomem = request_mem_region(iomem->start, resource_size(iomem),\n>> \t\t\t\t driver_name);\n>> \tif (!iomem) {\n>> diff --git a/drivers/watchdog/intel-mid_wdt.c b/drivers/watchdog/intel-mid_wdt.c\n>> index 72c108a..a73559b 100644\n>> --- a/drivers/watchdog/intel-mid_wdt.c\n>> +++ b/drivers/watchdog/intel-mid_wdt.c\n>> @@ -18,6 +18,7 @@\n>> #include \n>> #include \n>> #include \n>> +#include \n>> \n>> #include \n>> #include \n>> @@ -29,6 +30,8 @@\n>> #define MID_WDT_TIMEOUT_MAX\t\t170\n>> #define MID_WDT_DEFAULT_TIMEOUT\t\t90\n>> \n>> +static struct intel_ipc_dev *scu_ipc_dev;\n>> +\n>> /* SCU watchdog messages */\n>> enum {\n>> \tSCU_WATCHDOG_START = 0,\n>> @@ -38,7 +41,10 @@ enum {\n>> \n>> static inline int wdt_command(int sub, u32 *in, int inlen)\n>> {\n>> -\treturn intel_scu_ipc_command(IPC_WATCHDOG, sub, in, inlen, NULL, 0);\n>> +\tu32 cmds[SCU_PARAM_LEN] = {IPC_WATCHDOG, sub};\n>> +\n>> +\treturn ipc_dev_cmd(scu_ipc_dev, cmds, SCU_PARAM_LEN, in,\n>> +\t\t\tinlen, NULL, 0);\n>> }\n>> \n>> static int wdt_start(struct watchdog_device *wd)\n>> @@ -129,6 +135,10 @@ static int mid_wdt_probe(struct platform_device *pdev)\n>> \tif (!wdt_dev)\n>> \t\treturn -ENOMEM;\n>> \n>> +\tscu_ipc_dev = intel_ipc_dev_get(INTEL_SCU_IPC_DEV);\n>> +\tif (IS_ERR_OR_NULL(scu_ipc_dev))\n>> +\t\treturn PTR_ERR(scu_ipc_dev);\n>> +\n>> \twdt_dev->info = &mid_wdt_info;\n>> \twdt_dev->ops = &mid_wdt_ops;\n>> \twdt_dev->min_timeout = MID_WDT_TIMEOUT_MIN;\n>> diff --git a/drivers/watchdog/intel_scu_watchdog.c b/drivers/watchdog/intel_scu_watchdog.c\n>> index 0caab62..9457c7a 100644\n>> --- a/drivers/watchdog/intel_scu_watchdog.c\n>> +++ b/drivers/watchdog/intel_scu_watchdog.c\n>> @@ -49,6 +49,7 @@\n>> #include \n>> #include \n>> #include \n>> +#include \n>> \n>> #include \"intel_scu_watchdog.h\"\n>> \n>> @@ -94,6 +95,8 @@ MODULE_PARM_DESC(force_boot,\n>> \n>> static struct intel_scu_watchdog_dev watchdog_device;\n>> \n>> +static struct intel_ipc_dev *scu_ipc_dev;\n>> +\n>> /* Forces restart, if force_reboot is set */\n>> static void watchdog_fire(void)\n>> {\n>> @@ -128,18 +131,14 @@ static int watchdog_set_ipc(int soft_threshold, int threshold)\n>> \tu32\t*ipc_wbuf;\n>> \tu8\t cbuf[16] = { '\\0' };\n>> \tint\t ipc_ret = 0;\n>> +\tu32 cmds[SCU_PARAM_LEN] = {IPC_SET_WATCHDOG_TIMER, 0};\n>> \n>> \tipc_wbuf = (u32 *)&cbuf;\n>> \tipc_wbuf[0] = soft_threshold;\n>> \tipc_wbuf[1] = threshold;\n>> \n>> -\tipc_ret = intel_scu_ipc_command(\n>> -\t\t\tIPC_SET_WATCHDOG_TIMER,\n>> -\t\t\t0,\n>> -\t\t\tipc_wbuf,\n>> -\t\t\t2,\n>> -\t\t\tNULL,\n>> -\t\t\t0);\n>> +\tipc_ret = ipc_dev_cmd(scu_ipc_dev, cmds, SCU_PARAM_LEN, ipc_wbuf,\n>> +\t\t\t2, NULL, 0);\n>> \n>> \tif (ipc_ret != 0)\n>> \t\tpr_err(\"Error setting SCU watchdog timer: %x\\n\", ipc_ret);\n>> @@ -460,6 +459,10 @@ static int __init intel_scu_watchdog_init(void)\n>> \tif (check_timer_margin(timer_margin))\n>> \t\treturn -EINVAL;\n>> \n>> +\tscu_ipc_dev = intel_ipc_dev_get(INTEL_SCU_IPC_DEV);\n>> +\tif (IS_ERR_OR_NULL(scu_ipc_dev))\n>> +\t\treturn PTR_ERR(scu_ipc_dev);\n>> +\n>> \twatchdog_device.timer_tbl_ptr = sfi_get_mtmr(sfi_mtimer_num-1);\n>> \n>> \tif (watchdog_device.timer_tbl_ptr == NULL) {\n>> -- \n>> 2.7.4\n>>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-rtc-owner@vger.kernel.org;\n\treceiver=)","Received":["from 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d=\"scan'208\";a=\"142390452\"","Reply-To":"sathyanarayanan.kuppuswamy@linux.intel.com","Subject":"Re: [RFC v3 7/7] platform/x86: intel_scu_ipc: Use generic Intel IPC\n\tdevice calls","To":"Alexandre Belloni ","Cc":"a.zummo@towertech.it, x86@kernel.org, wim@iguana.be,\n\tmingo@redhat.com, qipeng.zha@intel.com, hpa@zytor.com,\n\tdvhart@infradead.org, tglx@linutronix.de, lee.jones@linaro.org,\n\tandy@infradead.org, souvik.k.chakravarty@intel.com,\n\tlinux-rtc@vger.kernel.org, linux-watchdog@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org,\n\tsathyaosid@gmail.com","References":"\n\t<90f4d15c9ca0430f6ac4cfafe0eaf6ece6c8761c.1504588701.git.sathyanarayanan.kuppuswamy@linux.intel.com>\n\t<20170928125519.ol5suebaoqsiixm5@piout.net>","From":"sathyanarayanan kuppuswamy \n\t","Organization":"Intel","Message-ID":"<965bdd3b-74a7-07ca-bba2-90e14f1e8bbe@linux.intel.com>","Date":"Tue, 3 Oct 2017 17:32:02 -0700","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<20170928125519.ol5suebaoqsiixm5@piout.net>","Content-Type":"text/plain; charset=utf-8; format=flowed","Content-Transfer-Encoding":"7bit","Content-Language":"en-US","Sender":"linux-rtc-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-rtc@vger.kernel.org"}},{"id":1779334,"web_url":"http://patchwork.ozlabs.org/comment/1779334/","msgid":"","list_archive_url":null,"date":"2017-10-04T00:55:21","subject":"Re: [RFC v3 7/7] platform/x86: intel_scu_ipc: Use generic Intel IPC\n\tdevice calls","submitter":{"id":66129,"url":"http://patchwork.ozlabs.org/api/people/66129/","name":"Kuppuswamy Sathyanarayanan","email":"sathyanarayanan.kuppuswamy@linux.intel.com"},"content":"Hi Guenter,\n\n\nOn 09/28/2017 06:35 AM, Guenter Roeck wrote:\n> On 09/28/2017 05:55 AM, Alexandre Belloni wrote:\n>> On 04/09/2017 at 22:37:27 -0700, \n>> sathyanarayanan.kuppuswamy@linux.intel.com wrote:\n>>> From: Kuppuswamy Sathyanarayanan \n>>> \n>>>\n>>> Removed redundant IPC helper functions and refactored the driver to use\n>>> generic IPC device driver APIs.\n>>>\n>>> This patch also cleans-up SCU IPC user drivers to use APIs provided\n>>> by generic IPC driver.\n>>>\n>>> Signed-off-by: Kuppuswamy Sathyanarayanan \n>>> \n>>\n>> For the RTC part:\n>> Acked-by: Alexandre Belloni \n>>  >\n>>> ---\n>>>   arch/x86/include/asm/intel_scu_ipc.h    |  23 +-\n>>>   arch/x86/platform/intel-mid/intel-mid.c |  12 +-\n>>>   drivers/platform/x86/Kconfig            |   1 +\n>>>   drivers/platform/x86/intel_scu_ipc.c    | 483 \n>>> +++++++++++++-------------------\n>>>   drivers/rtc/rtc-mrst.c                  |  15 +-\n>>>   drivers/watchdog/intel-mid_wdt.c        |  12 +-\n>>>   drivers/watchdog/intel_scu_watchdog.c   |  17 +-\n>>>   7 files changed, 251 insertions(+), 312 deletions(-)\n>\n> I think it would help in general to mention at least in the \n> description which drivers are touched.\nI will add this info in my next patch version.\n>\n> I see calls to intel_ipc_dev_get() but not associated put calls. \n> Missing the context, it may\n> well be that those are not necessary, but then how does the ipc code \n> know that the device\n> reference is no longer needed ?\nI also noticed this issue. Initially I thought we don't need to deal \nwith ref count because in most\ncases IPC client drivers are compiled as built-in drivers ( because \nthese APIs are required during\nearly boot process to send IPC commands to ARC processor) and hence will \nhave life-time until the\ndevice is powered-off.\n\nBut after looking into Kconfig params, I noticed that at least \nintel_pmc_ipc and intel_punit_ipc drivers can be\ncompiled as modules. And hence we will have dangling pointer reference \nissue if we don't maintain\nproper refcount for device references.\n\nSo, I have already fixed this problem by adding intel_ipc_dev_put() and  \ndevm_intel_ipc_dev_get() APIs.\n\nThis fix will be available in next version.\n\n> Guenter\n>\n>>>\n>>> diff --git a/arch/x86/include/asm/intel_scu_ipc.h \n>>> b/arch/x86/include/asm/intel_scu_ipc.h\n>>> index 81d3d87..5842534 100644\n>>> --- a/arch/x86/include/asm/intel_scu_ipc.h\n>>> +++ b/arch/x86/include/asm/intel_scu_ipc.h\n>>> @@ -14,9 +14,19 @@\n>>>   #define IPCMSG_COLD_BOOT    0xF3\n>>>     #define IPCMSG_VRTC        0xFA     /* Set vRTC device */\n>>> -    /* Command id associated with message IPCMSG_VRTC */\n>>> -    #define IPC_CMD_VRTC_SETTIME      1 /* Set time */\n>>> -    #define IPC_CMD_VRTC_SETALARM     2 /* Set alarm */\n>>> +\n>>> +/* Command id associated with message IPCMSG_VRTC */\n>>> +#define IPC_CMD_VRTC_SETTIME      1 /* Set time */\n>>> +#define IPC_CMD_VRTC_SETALARM     2 /* Set alarm */\n>>> +\n>>> +#define INTEL_SCU_IPC_DEV    \"intel_scu_ipc\"\n>>> +#define SCU_PARAM_LEN        2\n>>> +\n>>> +static inline void scu_cmd_init(u32 *cmd, u32 param1, u32 param2)\n>>> +{\n>>> +    cmd[0] = param1;\n>>> +    cmd[1] = param2;\n>>> +}\n>>>     /* Read single register */\n>>>   int intel_scu_ipc_ioread8(u16 addr, u8 *data);\n>>> @@ -45,13 +55,6 @@ int intel_scu_ipc_writev(u16 *addr, u8 *data, int \n>>> len);\n>>>   /* Update single register based on the mask */\n>>>   int intel_scu_ipc_update_register(u16 addr, u8 data, u8 mask);\n>>>   -/* Issue commands to the SCU with or without data */\n>>> -int intel_scu_ipc_simple_command(int cmd, int sub);\n>>> -int intel_scu_ipc_command(int cmd, int sub, u32 *in, int inlen,\n>>> -              u32 *out, int outlen);\n>>> -int intel_scu_ipc_raw_command(int cmd, int sub, u8 *in, int inlen,\n>>> -                  u32 *out, int outlen, u32 dptr, u32 sptr);\n>>> -\n>>>   /* I2C control api */\n>>>   int intel_scu_ipc_i2c_cntrl(u32 addr, u32 *data);\n>>>   diff --git a/arch/x86/platform/intel-mid/intel-mid.c \n>>> b/arch/x86/platform/intel-mid/intel-mid.c\n>>> index 12a2725..27541e9 100644\n>>> --- a/arch/x86/platform/intel-mid/intel-mid.c\n>>> +++ b/arch/x86/platform/intel-mid/intel-mid.c\n>>> @@ -22,6 +22,7 @@\n>>>   #include \n>>>   #include \n>>>   #include \n>>> +#include \n>>>     #include \n>>>   #include \n>>> @@ -68,18 +69,23 @@ static void *(*get_intel_mid_ops[])(void) = \n>>> INTEL_MID_OPS_INIT;\n>>>   enum intel_mid_cpu_type __intel_mid_cpu_chip;\n>>>   EXPORT_SYMBOL_GPL(__intel_mid_cpu_chip);\n>>>   +static struct intel_ipc_dev *ipc_dev;\n>>> +\n>>>   static void intel_mid_power_off(void)\n>>>   {\n>>> +    u32 cmds[SCU_PARAM_LEN] = {IPCMSG_COLD_OFF, 1};\n>>>       /* Shut down South Complex via PWRMU */\n>>>       intel_mid_pwr_power_off();\n>>>         /* Only for Tangier, the rest will ignore this command */\n>>> -    intel_scu_ipc_simple_command(IPCMSG_COLD_OFF, 1);\n>>> +    ipc_dev_simple_cmd(ipc_dev, cmds, SCU_PARAM_LEN);\n>>>   };\n>>>     static void intel_mid_reboot(void)\n>>>   {\n>>> -    intel_scu_ipc_simple_command(IPCMSG_COLD_BOOT, 0);\n>>> +    u32 cmds[SCU_PARAM_LEN] = {IPCMSG_COLD_BOOT, 0};\n>>> +\n>>> +    ipc_dev_simple_cmd(ipc_dev, cmds, SCU_PARAM_LEN);\n>>>   }\n>>>     static unsigned long __init intel_mid_calibrate_tsc(void)\n>>> @@ -206,6 +212,8 @@ void __init x86_intel_mid_early_setup(void)\n>>>       x86_init.mpparse.find_smp_config = x86_init_noop;\n>>>       x86_init.mpparse.get_smp_config = x86_init_uint_noop;\n>>>       set_bit(MP_BUS_ISA, mp_bus_not_pci);\n>>> +\n>>> +    ipc_dev = intel_ipc_dev_get(INTEL_SCU_IPC_DEV);\n>>>   }\n>>>     /*\n>>> diff --git a/drivers/platform/x86/Kconfig \n>>> b/drivers/platform/x86/Kconfig\n>>> index 82479ca..e4e5822 100644\n>>> --- a/drivers/platform/x86/Kconfig\n>>> +++ b/drivers/platform/x86/Kconfig\n>>> @@ -850,6 +850,7 @@ config INTEL_VBTN\n>>>   config INTEL_SCU_IPC\n>>>       bool \"Intel SCU IPC Support\"\n>>>       depends on X86_INTEL_MID\n>>> +    select REGMAP_MMIO\n>>>       default y\n>>>       ---help---\n>>>         IPC is used to bridge the communications between kernel and \n>>> SCU on\n>>> diff --git a/drivers/platform/x86/intel_scu_ipc.c \n>>> b/drivers/platform/x86/intel_scu_ipc.c\n>>> index f7cf981..78013e4 100644\n>>> --- a/drivers/platform/x86/intel_scu_ipc.c\n>>> +++ b/drivers/platform/x86/intel_scu_ipc.c\n>>> @@ -24,6 +24,8 @@\n>>>   #include \n>>>   #include \n>>>   #include \n>>> +#include \n>>> +#include \n>>>   #include \n>>>   #include \n>>>   @@ -39,6 +41,25 @@\n>>>   #define IPC_CMD_PCNTRL_R      1 /* Register read */\n>>>   #define IPC_CMD_PCNTRL_M      2 /* Register read-modify-write */\n>>>   +/* IPC dev register offsets */\n>>> +/*\n>>> + * IPC Read Buffer (Read Only):\n>>> + * 16 byte buffer for receiving data from SCU, if IPC command\n>>> + * processing results in response data\n>>> + */\n>>> +#define IPC_DEV_SCU_RBUF_OFFSET            0x90\n>>> +#define IPC_DEV_SCU_WRBUF_OFFSET        0x80\n>>> +#define IPC_DEV_SCU_SPTR_OFFSET            0x08\n>>> +#define IPC_DEV_SCU_DPTR_OFFSET            0x0C\n>>> +#define IPC_DEV_SCU_STATUS_OFFSET        0x04\n>>> +\n>>> +/* IPC dev commands */\n>>> +/* IPC command register IOC bit */\n>>> +#define    IPC_DEV_SCU_CMD_MSI            BIT(8)\n>>> +#define    IPC_DEV_SCU_CMD_STATUS_ERR        BIT(1)\n>>> +#define    IPC_DEV_SCU_CMD_STATUS_ERR_MASK        GENMASK(7, 0)\n>>> +#define    IPC_DEV_SCU_CMD_STATUS_BUSY        BIT(0)\n>>> +\n>>>   /*\n>>>    * IPC register summary\n>>>    *\n>>> @@ -59,6 +80,11 @@\n>>>   #define IPC_WWBUF_SIZE    20        /* IPC Write buffer Size */\n>>>   #define IPC_RWBUF_SIZE    20        /* IPC Read buffer Size */\n>>>   #define IPC_IOC              0x100        /* IPC command register \n>>> IOC bit */\n>>> +#define    IPC_CMD_SIZE            16\n>>> +#define    IPC_CMD_SUBCMD          12\n>>> +#define    IPC_RWBUF_SIZE_DWORD    5\n>>> +#define    IPC_WWBUF_SIZE_DWORD    5\n>>> +\n>>>     #define PCI_DEVICE_ID_LINCROFT        0x082a\n>>>   #define PCI_DEVICE_ID_PENWELL        0x080e\n>>> @@ -93,140 +119,49 @@ static struct intel_scu_ipc_pdata_t \n>>> intel_scu_ipc_tangier_pdata = {\n>>>     struct intel_scu_ipc_dev {\n>>>       struct device *dev;\n>>> +    struct intel_ipc_dev *ipc_dev;\n>>>       void __iomem *ipc_base;\n>>>       void __iomem *i2c_base;\n>>> -    struct completion cmd_complete;\n>>> +    struct regmap *ipc_regs;\n>>> +    struct regmap *i2c_regs;\n>>>       u8 irq_mode;\n>>>   };\n>>>   -static struct intel_scu_ipc_dev  ipcdev; /* Only one for now */\n>>> +static struct regmap_config ipc_regmap_config = {\n>>> +        .reg_bits = 32,\n>>> +        .reg_stride = 4,\n>>> +        .val_bits = 32,\n>>> +};\n>>>   -/*\n>>> - * IPC Read Buffer (Read Only):\n>>> - * 16 byte buffer for receiving data from SCU, if IPC command\n>>> - * processing results in response data\n>>> - */\n>>> -#define IPC_READ_BUFFER        0x90\n>>> +static struct regmap_config i2c_regmap_config = {\n>>> +        .reg_bits = 32,\n>>> +        .reg_stride = 4,\n>>> +        .val_bits = 32,\n>>> +    .fast_io = true,\n>>> +};\n>>> +\n>>> +static struct intel_scu_ipc_dev  ipcdev; /* Only one for now */\n>>>     #define IPC_I2C_CNTRL_ADDR    0\n>>>   #define I2C_DATA_ADDR        0x04\n>>>   -static DEFINE_MUTEX(ipclock); /* lock used to prevent multiple \n>>> call to SCU */\n>>> -\n>>> -/*\n>>> - * Send ipc command\n>>> - * Command Register (Write Only):\n>>> - * A write to this register results in an interrupt to the SCU core \n>>> processor\n>>> - * Format:\n>>> - * |rfu2(8) | size(8) | command id(4) | rfu1(3) | ioc(1) | command(8)|\n>>> - */\n>>> -static inline void ipc_command(struct intel_scu_ipc_dev *scu, u32 cmd)\n>>> -{\n>>> -    if (scu->irq_mode) {\n>>> -        reinit_completion(&scu->cmd_complete);\n>>> -        writel(cmd | IPC_IOC, scu->ipc_base);\n>>> -    }\n>>> -    writel(cmd, scu->ipc_base);\n>>> -}\n>>> -\n>>> -/*\n>>> - * Write ipc data\n>>> - * IPC Write Buffer (Write Only):\n>>> - * 16-byte buffer for sending data associated with IPC command to\n>>> - * SCU. Size of the data is specified in the IPC_COMMAND_REG register\n>>> - */\n>>> -static inline void ipc_data_writel(struct intel_scu_ipc_dev *scu, \n>>> u32 data, u32 offset)\n>>> -{\n>>> -    writel(data, scu->ipc_base + 0x80 + offset);\n>>> -}\n>>> -\n>>> -/*\n>>> - * Status Register (Read Only):\n>>> - * Driver will read this register to get the ready/busy status of \n>>> the IPC\n>>> - * block and error status of the IPC command that was just \n>>> processed by SCU\n>>> - * Format:\n>>> - * |rfu3(8)|error code(8)|initiator id(8)|cmd \n>>> id(4)|rfu1(2)|error(1)|busy(1)|\n>>> - */\n>>> -static inline u8 ipc_read_status(struct intel_scu_ipc_dev *scu)\n>>> -{\n>>> -    return __raw_readl(scu->ipc_base + 0x04);\n>>> -}\n>>> -\n>>> -/* Read ipc byte data */\n>>> -static inline u8 ipc_data_readb(struct intel_scu_ipc_dev *scu, u32 \n>>> offset)\n>>> -{\n>>> -    return readb(scu->ipc_base + IPC_READ_BUFFER + offset);\n>>> -}\n>>> -\n>>> -/* Read ipc u32 data */\n>>> -static inline u32 ipc_data_readl(struct intel_scu_ipc_dev *scu, u32 \n>>> offset)\n>>> -{\n>>> -    return readl(scu->ipc_base + IPC_READ_BUFFER + offset);\n>>> -}\n>>> -\n>>> -/* Wait till scu status is busy */\n>>> -static inline int busy_loop(struct intel_scu_ipc_dev *scu)\n>>> -{\n>>> -    u32 status = ipc_read_status(scu);\n>>> -    u32 loop_count = 100000;\n>>> -\n>>> -    /* break if scu doesn't reset busy bit after huge retry */\n>>> -    while ((status & BIT(0)) && --loop_count) {\n>>> -        udelay(1); /* scu processing time is in few u secods */\n>>> -        status = ipc_read_status(scu);\n>>> -    }\n>>> -\n>>> -    if (status & BIT(0)) {\n>>> -        dev_err(scu->dev, \"IPC timed out\");\n>>> -        return -ETIMEDOUT;\n>>> -    }\n>>> -\n>>> -    if (status & BIT(1))\n>>> -        return -EIO;\n>>> -\n>>> -    return 0;\n>>> -}\n>>> -\n>>> -/* Wait till ipc ioc interrupt is received or timeout in 3 HZ */\n>>> -static inline int ipc_wait_for_interrupt(struct intel_scu_ipc_dev \n>>> *scu)\n>>> -{\n>>> -    int status;\n>>> -\n>>> -    if (!wait_for_completion_timeout(&scu->cmd_complete, 3 * HZ)) {\n>>> -        dev_err(scu->dev, \"IPC timed out\\n\");\n>>> -        return -ETIMEDOUT;\n>>> -    }\n>>> -\n>>> -    status = ipc_read_status(scu);\n>>> -    if (status & BIT(1))\n>>> -        return -EIO;\n>>> -\n>>> -    return 0;\n>>> -}\n>>> -\n>>> -static int intel_scu_ipc_check_status(struct intel_scu_ipc_dev *scu)\n>>> -{\n>>> -    return scu->irq_mode ? ipc_wait_for_interrupt(scu) : \n>>> busy_loop(scu);\n>>> -}\n>>> -\n>>>   /* Read/Write power control(PMIC in Langwell, MSIC in PenWell) \n>>> registers */\n>>>   static int pwr_reg_rdwr(u16 *addr, u8 *data, u32 count, u32 op, \n>>> u32 id)\n>>>   {\n>>>       struct intel_scu_ipc_dev *scu = &ipcdev;\n>>>       int nc;\n>>>       u32 offset = 0;\n>>> -    int err;\n>>> +    int err = -EIO;\n>>>       u8 cbuf[IPC_WWBUF_SIZE];\n>>>       u32 *wbuf = (u32 *)&cbuf;\n>>> +    u32 cmd[SCU_PARAM_LEN] = {0};\n>>> +    /* max rbuf size is 20 bytes */\n>>> +    u8 rbuf[IPC_RWBUF_SIZE] = {0};\n>>> +    u32 rbuflen = DIV_ROUND_UP(count, 4);\n>>>         memset(cbuf, 0, sizeof(cbuf));\n>>>   -    mutex_lock(&ipclock);\n>>> -\n>>> -    if (scu->dev == NULL) {\n>>> -        mutex_unlock(&ipclock);\n>>> -        return -ENODEV;\n>>> -    }\n>>> +    scu_cmd_init(cmd, op, id);\n>>>         for (nc = 0; nc < count; nc++, offset += 2) {\n>>>           cbuf[offset] = addr[nc];\n>>> @@ -234,30 +169,30 @@ static int pwr_reg_rdwr(u16 *addr, u8 *data, \n>>> u32 count, u32 op, u32 id)\n>>>       }\n>>>         if (id == IPC_CMD_PCNTRL_R) {\n>>> -        for (nc = 0, offset = 0; nc < count; nc++, offset += 4)\n>>> -            ipc_data_writel(scu, wbuf[nc], offset);\n>>> -        ipc_command(scu, (count * 2) << 16 | id << 12 | 0 << 8 | op);\n>>> +        err = ipc_dev_raw_cmd(scu->ipc_dev, cmd, SCU_PARAM_LEN,\n>>> +                (u8 *)wbuf, count * 2, (u32 *)rbuf,\n>>> +                IPC_RWBUF_SIZE_DWORD, 0, 0);\n>>>       } else if (id == IPC_CMD_PCNTRL_W) {\n>>>           for (nc = 0; nc < count; nc++, offset += 1)\n>>>               cbuf[offset] = data[nc];\n>>> -        for (nc = 0, offset = 0; nc < count; nc++, offset += 4)\n>>> -            ipc_data_writel(scu, wbuf[nc], offset);\n>>> -        ipc_command(scu, (count * 3) << 16 | id << 12 | 0 << 8 | op);\n>>> +        err = ipc_dev_raw_cmd(scu->ipc_dev, cmd, SCU_PARAM_LEN,\n>>> +                (u8 *)wbuf, count * 3, NULL, 0, 0, 0);\n>>> +\n>>>       } else if (id == IPC_CMD_PCNTRL_M) {\n>>>           cbuf[offset] = data[0];\n>>>           cbuf[offset + 1] = data[1];\n>>> -        ipc_data_writel(scu, wbuf[0], 0); /* Write wbuff */\n>>> -        ipc_command(scu, 4 << 16 | id << 12 | 0 << 8 | op);\n>>> +        err = ipc_dev_raw_cmd(scu->ipc_dev, cmd, SCU_PARAM_LEN,\n>>> +                (u8 *)wbuf, 4, NULL, 0, 0, 0);\n>>>       }\n>>>   -    err = intel_scu_ipc_check_status(scu);\n>>>       if (!err && id == IPC_CMD_PCNTRL_R) { /* Read rbuf */\n>>>           /* Workaround: values are read as 0 without memcpy_fromio */\n>>>           memcpy_fromio(cbuf, scu->ipc_base + 0x90, 16);\n>>> -        for (nc = 0; nc < count; nc++)\n>>> -            data[nc] = ipc_data_readb(scu, nc);\n>>> +        regmap_bulk_read(scu->ipc_regs, IPC_DEV_SCU_RBUF_OFFSET,\n>>> +                    rbuf, rbuflen);\n>>> +        memcpy(data, rbuf, count);\n>>>       }\n>>> -    mutex_unlock(&ipclock);\n>>> +\n>>>       return err;\n>>>   }\n>>>   @@ -422,138 +357,6 @@ int intel_scu_ipc_update_register(u16 addr, \n>>> u8 bits, u8 mask)\n>>>   }\n>>>   EXPORT_SYMBOL(intel_scu_ipc_update_register);\n>>>   -/**\n>>> - *    intel_scu_ipc_simple_command    -    send a simple command\n>>> - *    @cmd: command\n>>> - *    @sub: sub type\n>>> - *\n>>> - *    Issue a simple command to the SCU. Do not use this interface if\n>>> - *    you must then access data as any data values may be overwritten\n>>> - *    by another SCU access by the time this function returns.\n>>> - *\n>>> - *    This function may sleep. Locking for SCU accesses is handled for\n>>> - *    the caller.\n>>> - */\n>>> -int intel_scu_ipc_simple_command(int cmd, int sub)\n>>> -{\n>>> -    struct intel_scu_ipc_dev *scu = &ipcdev;\n>>> -    int err;\n>>> -\n>>> -    mutex_lock(&ipclock);\n>>> -    if (scu->dev == NULL) {\n>>> -        mutex_unlock(&ipclock);\n>>> -        return -ENODEV;\n>>> -    }\n>>> -    ipc_command(scu, sub << 12 | cmd);\n>>> -    err = intel_scu_ipc_check_status(scu);\n>>> -    mutex_unlock(&ipclock);\n>>> -    return err;\n>>> -}\n>>> -EXPORT_SYMBOL(intel_scu_ipc_simple_command);\n>>> -\n>>> -/**\n>>> - *    intel_scu_ipc_command    -    command with data\n>>> - *    @cmd: command\n>>> - *    @sub: sub type\n>>> - *    @in: input data\n>>> - *    @inlen: input length in dwords\n>>> - *    @out: output data\n>>> - *    @outlein: output length in dwords\n>>> - *\n>>> - *    Issue a command to the SCU which involves data transfers. Do the\n>>> - *    data copies under the lock but leave it for the caller to \n>>> interpret\n>>> - */\n>>> -int intel_scu_ipc_command(int cmd, int sub, u32 *in, int inlen,\n>>> -              u32 *out, int outlen)\n>>> -{\n>>> -    struct intel_scu_ipc_dev *scu = &ipcdev;\n>>> -    int i, err;\n>>> -\n>>> -    mutex_lock(&ipclock);\n>>> -    if (scu->dev == NULL) {\n>>> -        mutex_unlock(&ipclock);\n>>> -        return -ENODEV;\n>>> -    }\n>>> -\n>>> -    for (i = 0; i < inlen; i++)\n>>> -        ipc_data_writel(scu, *in++, 4 * i);\n>>> -\n>>> -    ipc_command(scu, (inlen << 16) | (sub << 12) | cmd);\n>>> -    err = intel_scu_ipc_check_status(scu);\n>>> -\n>>> -    if (!err) {\n>>> -        for (i = 0; i < outlen; i++)\n>>> -            *out++ = ipc_data_readl(scu, 4 * i);\n>>> -    }\n>>> -\n>>> -    mutex_unlock(&ipclock);\n>>> -    return err;\n>>> -}\n>>> -EXPORT_SYMBOL(intel_scu_ipc_command);\n>>> -\n>>> -#define IPC_SPTR        0x08\n>>> -#define IPC_DPTR        0x0C\n>>> -\n>>> -/**\n>>> - * intel_scu_ipc_raw_command() - IPC command with data and pointers\n>>> - * @cmd:    IPC command code.\n>>> - * @sub:    IPC command sub type.\n>>> - * @in:        input data of this IPC command.\n>>> - * @inlen:    input data length in dwords.\n>>> - * @out:    output data of this IPC command.\n>>> - * @outlen:    output data length in dwords.\n>>> - * @sptr:    data writing to SPTR register.\n>>> - * @dptr:    data writing to DPTR register.\n>>> - *\n>>> - * Send an IPC command to SCU with input/output data and \n>>> source/dest pointers.\n>>> - *\n>>> - * Return:    an IPC error code or 0 on success.\n>>> - */\n>>> -int intel_scu_ipc_raw_command(int cmd, int sub, u8 *in, int inlen,\n>>> -                  u32 *out, int outlen, u32 dptr, u32 sptr)\n>>> -{\n>>> -    struct intel_scu_ipc_dev *scu = &ipcdev;\n>>> -    int inbuflen = DIV_ROUND_UP(inlen, 4);\n>>> -    u32 inbuf[4];\n>>> -    int i, err;\n>>> -\n>>> -    /* Up to 16 bytes */\n>>> -    if (inbuflen > 4)\n>>> -        return -EINVAL;\n>>> -\n>>> -    mutex_lock(&ipclock);\n>>> -    if (scu->dev == NULL) {\n>>> -        mutex_unlock(&ipclock);\n>>> -        return -ENODEV;\n>>> -    }\n>>> -\n>>> -    writel(dptr, scu->ipc_base + IPC_DPTR);\n>>> -    writel(sptr, scu->ipc_base + IPC_SPTR);\n>>> -\n>>> -    /*\n>>> -     * SRAM controller doesn't support 8-bit writes, it only\n>>> -     * supports 32-bit writes, so we have to copy input data into\n>>> -     * the temporary buffer, and SCU FW will use the inlen to\n>>> -     * determine the actual input data length in the temporary\n>>> -     * buffer.\n>>> -     */\n>>> -    memcpy(inbuf, in, inlen);\n>>> -\n>>> -    for (i = 0; i < inbuflen; i++)\n>>> -        ipc_data_writel(scu, inbuf[i], 4 * i);\n>>> -\n>>> -    ipc_command(scu, (inlen << 16) | (sub << 12) | cmd);\n>>> -    err = intel_scu_ipc_check_status(scu);\n>>> -    if (!err) {\n>>> -        for (i = 0; i < outlen; i++)\n>>> -            *out++ = ipc_data_readl(scu, 4 * i);\n>>> -    }\n>>> -\n>>> -    mutex_unlock(&ipclock);\n>>> -    return err;\n>>> -}\n>>> -EXPORT_SYMBOL_GPL(intel_scu_ipc_raw_command);\n>>> -\n>>>   /* I2C commands */\n>>>   #define IPC_I2C_WRITE 1 /* I2C Write command */\n>>>   #define IPC_I2C_READ  2 /* I2C Read command */\n>>> @@ -575,48 +378,143 @@ int intel_scu_ipc_i2c_cntrl(u32 addr, u32 *data)\n>>>       struct intel_scu_ipc_dev *scu = &ipcdev;\n>>>       u32 cmd = 0;\n>>>   -    mutex_lock(&ipclock);\n>>> -    if (scu->dev == NULL) {\n>>> -        mutex_unlock(&ipclock);\n>>> -        return -ENODEV;\n>>> -    }\n>>>       cmd = (addr >> 24) & 0xFF;\n>>>       if (cmd == IPC_I2C_READ) {\n>>> -        writel(addr, scu->i2c_base + IPC_I2C_CNTRL_ADDR);\n>>> +        regmap_write(scu->i2c_regs, IPC_I2C_CNTRL_ADDR, addr);\n>>>           /* Write not getting updated without delay */\n>>>           mdelay(1);\n>>> -        *data = readl(scu->i2c_base + I2C_DATA_ADDR);\n>>> +        regmap_read(scu->i2c_regs, I2C_DATA_ADDR, data);\n>>>       } else if (cmd == IPC_I2C_WRITE) {\n>>> -        writel(*data, scu->i2c_base + I2C_DATA_ADDR);\n>>> +        regmap_write(scu->i2c_regs, I2C_DATA_ADDR, *data);\n>>>           mdelay(1);\n>>> -        writel(addr, scu->i2c_base + IPC_I2C_CNTRL_ADDR);\n>>> +        regmap_write(scu->i2c_regs, IPC_I2C_CNTRL_ADDR, addr);\n>>>       } else {\n>>>           dev_err(scu->dev,\n>>>               \"intel_scu_ipc: I2C INVALID_CMD = 0x%x\\n\", cmd);\n>>>   -        mutex_unlock(&ipclock);\n>>>           return -EIO;\n>>>       }\n>>> -    mutex_unlock(&ipclock);\n>>>       return 0;\n>>>   }\n>>>   EXPORT_SYMBOL(intel_scu_ipc_i2c_cntrl);\n>>>   -/*\n>>> - * Interrupt handler gets called when ioc bit of IPC_COMMAND_REG \n>>> set to 1\n>>> - * When ioc bit is set to 1, caller api must wait for interrupt \n>>> handler called\n>>> - * which in turn unlocks the caller api. Currently this is not used\n>>> - *\n>>> - * This is edge triggered so we need take no action to clear anything\n>>> - */\n>>> -static irqreturn_t ioc(int irq, void *dev_id)\n>>> +static int pre_simple_cmd_fn(u32 *cmd_list, u32 cmdlen)\n>>>   {\n>>> -    struct intel_scu_ipc_dev *scu = dev_id;\n>>> +    if (!cmd_list || cmdlen != SCU_PARAM_LEN)\n>>> +        return -EINVAL;\n>>>   -    if (scu->irq_mode)\n>>> -        complete(&scu->cmd_complete);\n>>> +    cmd_list[0] |= (cmd_list[1] << IPC_CMD_SUBCMD);\n>>>   -    return IRQ_HANDLED;\n>>> +    return 0;\n>>> +}\n>>> +\n>>> +static int pre_cmd_fn(u32 *cmd_list, u32 cmdlen, u32 *in, u32 inlen,\n>>> +        u32 *out, u32 outlen)\n>>> +{\n>>> +    int ret;\n>>> +\n>>> +    if (inlen > IPC_WWBUF_SIZE_DWORD || outlen > IPC_RWBUF_SIZE_DWORD)\n>>> +        return -EINVAL;\n>>> +\n>>> +    ret = pre_simple_cmd_fn(cmd_list, cmdlen);\n>>> +    if (ret < 0)\n>>> +        return ret;\n>>> +\n>>> +    cmd_list[0] |= (inlen << IPC_CMD_SIZE);\n>>> +\n>>> +    return 0;\n>>> +}\n>>> +\n>>> +static int pre_raw_cmd_fn(u32 *cmd_list, u32 cmdlen, u8 *in, u32 \n>>> inlen,\n>>> +        u32 *out, u32 outlen, u32 dptr, u32 sptr)\n>>> +{\n>>> +    int ret;\n>>> +\n>>> +    if (inlen > IPC_WWBUF_SIZE || outlen > IPC_RWBUF_SIZE_DWORD)\n>>> +        return -EINVAL;\n>>> +\n>>> +    ret = pre_simple_cmd_fn(cmd_list, cmdlen);\n>>> +    if (ret < 0)\n>>> +        return ret;\n>>> +\n>>> +    cmd_list[0] |= (inlen << IPC_CMD_SIZE);\n>>> +\n>>> +    return 0;\n>>> +}\n>>> +\n>>> +static int scu_ipc_err_code(int status)\n>>> +{\n>>> +    if (status & IPC_DEV_SCU_CMD_STATUS_ERR)\n>>> +        return (status & IPC_DEV_SCU_CMD_STATUS_ERR_MASK);\n>>> +    else\n>>> +        return 0;\n>>> +}\n>>> +\n>>> +static int scu_ipc_busy_check(int status)\n>>> +{\n>>> +    return status | IPC_DEV_SCU_CMD_STATUS_BUSY;\n>>> +}\n>>> +\n>>> +static u32 scu_ipc_enable_msi(u32 cmd)\n>>> +{\n>>> +    return cmd | IPC_DEV_SCU_CMD_MSI;\n>>> +}\n>>> +\n>>> +static struct intel_ipc_dev *intel_scu_ipc_dev_create(\n>>> +        struct device *dev,\n>>> +        void __iomem *base,\n>>> +        int irq)\n>>> +{\n>>> +    struct intel_ipc_dev_ops *ops;\n>>> +    struct intel_ipc_dev_cfg *cfg;\n>>> +    struct regmap *ipc_regs;\n>>> +    struct intel_scu_ipc_dev *scu = dev_get_drvdata(dev);\n>>> +\n>>> +    cfg = devm_kzalloc(dev, sizeof(*cfg), GFP_KERNEL);\n>>> +    if (!cfg)\n>>> +        return ERR_PTR(-ENOMEM);\n>>> +\n>>> +    ops = devm_kzalloc(dev, sizeof(*ops), GFP_KERNEL);\n>>> +    if (!ops)\n>>> +        return ERR_PTR(-ENOMEM);\n>>> +\n>>> +        ipc_regs = devm_regmap_init_mmio_clk(dev, NULL, base,\n>>> +            &ipc_regmap_config);\n>>> +        if (IS_ERR(ipc_regs)) {\n>>> +                dev_err(dev, \"ipc_regs regmap init failed\\n\");\n>>> +                return ERR_CAST(ipc_regs);;\n>>> +        }\n>>> +\n>>> +    scu->ipc_regs = ipc_regs;\n>>> +\n>>> +    /* set IPC dev ops */\n>>> +    ops->to_err_code = scu_ipc_err_code;\n>>> +    ops->busy_check = scu_ipc_busy_check;\n>>> +    ops->enable_msi = scu_ipc_enable_msi;\n>>> +    ops->pre_cmd_fn = pre_cmd_fn;\n>>> +    ops->pre_raw_cmd_fn = pre_raw_cmd_fn;\n>>> +    ops->pre_simple_cmd_fn = pre_simple_cmd_fn;\n>>> +\n>>> +    /* set cfg options */\n>>> +    if (scu->irq_mode)\n>>> +        cfg->mode = IPC_DEV_MODE_IRQ;\n>>> +    else\n>>> +        cfg->mode = IPC_DEV_MODE_POLLING;\n>>> +\n>>> +    cfg->chan_type = IPC_CHANNEL_IA_SCU;\n>>> +    cfg->irq = irq;\n>>> +    cfg->use_msi = true;\n>>> +    cfg->support_sptr = true;\n>>> +    cfg->support_dptr = true;\n>>> +    cfg->cmd_regs = ipc_regs;\n>>> +    cfg->data_regs = ipc_regs;\n>>> +    cfg->wrbuf_reg = IPC_DEV_SCU_WRBUF_OFFSET;\n>>> +    cfg->rbuf_reg = IPC_DEV_SCU_RBUF_OFFSET;\n>>> +    cfg->sptr_reg = IPC_DEV_SCU_SPTR_OFFSET;\n>>> +    cfg->dptr_reg = IPC_DEV_SCU_DPTR_OFFSET;\n>>> +    cfg->status_reg = IPC_DEV_SCU_STATUS_OFFSET;\n>>> +\n>>> +    return devm_intel_ipc_dev_create(dev, INTEL_SCU_IPC_DEV, cfg, \n>>> ops);\n>>>   }\n>>>     /**\n>>> @@ -650,25 +548,34 @@ static int ipc_probe(struct pci_dev *pdev, \n>>> const struct pci_device_id *id)\n>>>       if (err)\n>>>           return err;\n>>>   -    init_completion(&scu->cmd_complete);\n>>> -\n>>>       scu->ipc_base = pcim_iomap_table(pdev)[0];\n>>>   -    scu->i2c_base = ioremap_nocache(pdata->i2c_base, \n>>> pdata->i2c_len);\n>>> +    scu->i2c_base = devm_ioremap_nocache(&pdev->dev, pdata->i2c_base,\n>>> +            pdata->i2c_len);\n>>>       if (!scu->i2c_base)\n>>>           return -ENOMEM;\n>>>   -    err = devm_request_irq(&pdev->dev, pdev->irq, ioc, 0, \n>>> \"intel_scu_ipc\",\n>>> -                   scu);\n>>> -    if (err)\n>>> -        return err;\n>>> +    pci_set_drvdata(pdev, scu);\n>>> +\n>>> +        scu->i2c_regs = devm_regmap_init_mmio_clk(&pdev->dev, NULL,\n>>> +            scu->i2c_base, &i2c_regmap_config);\n>>> +        if (IS_ERR(scu->i2c_regs)) {\n>>> +                dev_err(&pdev->dev, \"i2c_regs regmap init failed\\n\");\n>>> +                return PTR_ERR(scu->i2c_regs);;\n>>> +        }\n>>> +\n>>> +    scu->ipc_dev = intel_scu_ipc_dev_create(&pdev->dev, scu->ipc_base,\n>>> +            pdev->irq);\n>>> +    if (IS_ERR(scu->ipc_dev)) {\n>>> +        dev_err(&pdev->dev, \"Failed to create SCU IPC device\\n\");\n>>> +        return PTR_ERR(scu->ipc_dev);\n>>> +    }\n>>>         /* Assign device at last */\n>>>       scu->dev = &pdev->dev;\n>>>         intel_scu_devices_create();\n>>>   -    pci_set_drvdata(pdev, scu);\n>>>       return 0;\n>>>   }\n>>>   diff --git a/drivers/rtc/rtc-mrst.c b/drivers/rtc/rtc-mrst.c\n>>> index 7334c44..a2d87e8 100644\n>>> --- a/drivers/rtc/rtc-mrst.c\n>>> +++ b/drivers/rtc/rtc-mrst.c\n>>> @@ -36,6 +36,7 @@\n>>>   #include \n>>>   #include \n>>>   #include \n>>> +#include \n>>>     #include \n>>>   #include \n>>> @@ -46,6 +47,7 @@ struct mrst_rtc {\n>>>       struct device        *dev;\n>>>       int            irq;\n>>>       struct resource        *iomem;\n>>> +    struct intel_ipc_dev    *ipc_dev;\n>>>         u8            enabled_wake;\n>>>       u8            suspend_ctrl;\n>>> @@ -110,10 +112,11 @@ static int mrst_read_time(struct device *dev, \n>>> struct rtc_time *time)\n>>>     static int mrst_set_time(struct device *dev, struct rtc_time *time)\n>>>   {\n>>> -    int ret;\n>>>       unsigned long flags;\n>>>       unsigned char mon, day, hrs, min, sec;\n>>>       unsigned int yrs;\n>>> +    struct mrst_rtc    *mrst = dev_get_drvdata(dev);\n>>> +    u32 cmds[SCU_PARAM_LEN] = {IPCMSG_VRTC, IPC_CMD_VRTC_SETTIME};\n>>>         yrs = time->tm_year;\n>>>       mon = time->tm_mon + 1;   /* tm_mon starts at zero */\n>>> @@ -137,8 +140,7 @@ static int mrst_set_time(struct device *dev, \n>>> struct rtc_time *time)\n>>>         spin_unlock_irqrestore(&rtc_lock, flags);\n>>>   -    ret = intel_scu_ipc_simple_command(IPCMSG_VRTC, \n>>> IPC_CMD_VRTC_SETTIME);\n>>> -    return ret;\n>>> +    return ipc_dev_simple_cmd(mrst->ipc_dev, cmds, SCU_PARAM_LEN);\n>>>   }\n>>>     static int mrst_read_alarm(struct device *dev, struct rtc_wkalrm \n>>> *t)\n>>> @@ -210,6 +212,7 @@ static int mrst_set_alarm(struct device *dev, \n>>> struct rtc_wkalrm *t)\n>>>       struct mrst_rtc    *mrst = dev_get_drvdata(dev);\n>>>       unsigned char hrs, min, sec;\n>>>       int ret = 0;\n>>> +    u32 cmds[SCU_PARAM_LEN] = {IPCMSG_VRTC, IPC_CMD_VRTC_SETALARM};\n>>>         if (!mrst->irq)\n>>>           return -EIO;\n>>> @@ -229,7 +232,7 @@ static int mrst_set_alarm(struct device *dev, \n>>> struct rtc_wkalrm *t)\n>>>         spin_unlock_irq(&rtc_lock);\n>>>   -    ret = intel_scu_ipc_simple_command(IPCMSG_VRTC, \n>>> IPC_CMD_VRTC_SETALARM);\n>>> +    ret = ipc_dev_simple_cmd(mrst->ipc_dev, cmds, SCU_PARAM_LEN);\n>>>       if (ret)\n>>>           return ret;\n>>>   @@ -329,6 +332,10 @@ static int vrtc_mrst_do_probe(struct device \n>>> *dev, struct resource *iomem,\n>>>       if (!iomem)\n>>>           return -ENODEV;\n>>>   +    mrst_rtc.ipc_dev = intel_ipc_dev_get(INTEL_SCU_IPC_DEV);\n>>> +    if (IS_ERR_OR_NULL(mrst_rtc.ipc_dev))\n>>> +        return PTR_ERR(mrst_rtc.ipc_dev);\n>>> +\n>>>       iomem = request_mem_region(iomem->start, resource_size(iomem),\n>>>                      driver_name);\n>>>       if (!iomem) {\n>>> diff --git a/drivers/watchdog/intel-mid_wdt.c \n>>> b/drivers/watchdog/intel-mid_wdt.c\n>>> index 72c108a..a73559b 100644\n>>> --- a/drivers/watchdog/intel-mid_wdt.c\n>>> +++ b/drivers/watchdog/intel-mid_wdt.c\n>>> @@ -18,6 +18,7 @@\n>>>   #include \n>>>   #include \n>>>   #include \n>>> +#include \n>>>     #include \n>>>   #include \n>>> @@ -29,6 +30,8 @@\n>>>   #define MID_WDT_TIMEOUT_MAX        170\n>>>   #define MID_WDT_DEFAULT_TIMEOUT        90\n>>>   +static struct intel_ipc_dev *scu_ipc_dev;\n>>> +\n>>>   /* SCU watchdog messages */\n>>>   enum {\n>>>       SCU_WATCHDOG_START = 0,\n>>> @@ -38,7 +41,10 @@ enum {\n>>>     static inline int wdt_command(int sub, u32 *in, int inlen)\n>>>   {\n>>> -    return intel_scu_ipc_command(IPC_WATCHDOG, sub, in, inlen, \n>>> NULL, 0);\n>>> +    u32 cmds[SCU_PARAM_LEN] = {IPC_WATCHDOG, sub};\n>>> +\n>>> +    return ipc_dev_cmd(scu_ipc_dev, cmds, SCU_PARAM_LEN, in,\n>>> +            inlen, NULL, 0);\n>>>   }\n>>>     static int wdt_start(struct watchdog_device *wd)\n>>> @@ -129,6 +135,10 @@ static int mid_wdt_probe(struct platform_device \n>>> *pdev)\n>>>       if (!wdt_dev)\n>>>           return -ENOMEM;\n>>>   +    scu_ipc_dev = intel_ipc_dev_get(INTEL_SCU_IPC_DEV);\n>>> +    if (IS_ERR_OR_NULL(scu_ipc_dev))\n>>> +        return PTR_ERR(scu_ipc_dev);\n>>> +\n>>>       wdt_dev->info = &mid_wdt_info;\n>>>       wdt_dev->ops = &mid_wdt_ops;\n>>>       wdt_dev->min_timeout = MID_WDT_TIMEOUT_MIN;\n>>> diff --git a/drivers/watchdog/intel_scu_watchdog.c \n>>> b/drivers/watchdog/intel_scu_watchdog.c\n>>> index 0caab62..9457c7a 100644\n>>> --- a/drivers/watchdog/intel_scu_watchdog.c\n>>> +++ b/drivers/watchdog/intel_scu_watchdog.c\n>>> @@ -49,6 +49,7 @@\n>>>   #include \n>>>   #include \n>>>   #include \n>>> +#include \n>>>     #include \"intel_scu_watchdog.h\"\n>>>   @@ -94,6 +95,8 @@ MODULE_PARM_DESC(force_boot,\n>>>     static struct intel_scu_watchdog_dev watchdog_device;\n>>>   +static struct intel_ipc_dev *scu_ipc_dev;\n>>> +\n>>>   /* Forces restart, if force_reboot is set */\n>>>   static void watchdog_fire(void)\n>>>   {\n>>> @@ -128,18 +131,14 @@ static int watchdog_set_ipc(int \n>>> soft_threshold, int threshold)\n>>>       u32    *ipc_wbuf;\n>>>       u8     cbuf[16] = { '\\0' };\n>>>       int     ipc_ret = 0;\n>>> +    u32 cmds[SCU_PARAM_LEN] = {IPC_SET_WATCHDOG_TIMER, 0};\n>>>         ipc_wbuf = (u32 *)&cbuf;\n>>>       ipc_wbuf[0] = soft_threshold;\n>>>       ipc_wbuf[1] = threshold;\n>>>   -    ipc_ret = intel_scu_ipc_command(\n>>> -            IPC_SET_WATCHDOG_TIMER,\n>>> -            0,\n>>> -            ipc_wbuf,\n>>> -            2,\n>>> -            NULL,\n>>> -            0);\n>>> +    ipc_ret = ipc_dev_cmd(scu_ipc_dev, cmds, SCU_PARAM_LEN, ipc_wbuf,\n>>> +            2, NULL, 0);\n>>>         if (ipc_ret != 0)\n>>>           pr_err(\"Error setting SCU watchdog timer: %x\\n\", ipc_ret);\n>>> @@ -460,6 +459,10 @@ static int __init intel_scu_watchdog_init(void)\n>>>       if (check_timer_margin(timer_margin))\n>>>           return -EINVAL;\n>>>   +    scu_ipc_dev = intel_ipc_dev_get(INTEL_SCU_IPC_DEV);\n>>> +    if (IS_ERR_OR_NULL(scu_ipc_dev))\n>>> +        return PTR_ERR(scu_ipc_dev);\n>>> +\n>>>       watchdog_device.timer_tbl_ptr = sfi_get_mtmr(sfi_mtimer_num-1);\n>>>         if (watchdog_device.timer_tbl_ptr == NULL) {\n>>> -- \n>>> 2.7.4\n>>>\n>>\n>\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) 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(Postfix) with ESMTP id 136945802D8;\n\tTue, 3 Oct 2017 17:55:33 -0700 (PDT)"],"X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos;i=\"5.42,475,1500966000\"; d=\"scan'208\";a=\"156370124\"","Reply-To":"sathyanarayanan.kuppuswamy@linux.intel.com","Subject":"Re: [RFC v3 7/7] platform/x86: intel_scu_ipc: Use generic Intel IPC\n\tdevice calls","To":"Guenter Roeck ,\n\tAlexandre Belloni ","Cc":"a.zummo@towertech.it, x86@kernel.org, wim@iguana.be,\n\tmingo@redhat.com, qipeng.zha@intel.com, hpa@zytor.com,\n\tdvhart@infradead.org, tglx@linutronix.de, lee.jones@linaro.org,\n\tandy@infradead.org, souvik.k.chakravarty@intel.com,\n\tlinux-rtc@vger.kernel.org, linux-watchdog@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org,\n\tsathyaosid@gmail.com","References":"\n\t<90f4d15c9ca0430f6ac4cfafe0eaf6ece6c8761c.1504588701.git.sathyanarayanan.kuppuswamy@linux.intel.com>\n\t<20170928125519.ol5suebaoqsiixm5@piout.net>\n\t","From":"sathyanarayanan kuppuswamy \n\t","Organization":"Intel","Message-ID":"","Date":"Tue, 3 Oct 2017 17:55:21 -0700","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"","Content-Type":"text/plain; charset=utf-8; format=flowed","Content-Transfer-Encoding":"8bit","Content-Language":"en-US","Sender":"linux-rtc-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-rtc@vger.kernel.org"}}]