[{"id":1763745,"web_url":"http://patchwork.ozlabs.org/comment/1763745/","msgid":"<20170906103621.092395dd@roar.ozlabs.ibm.com>","date":"2017-09-06T00:36:21","subject":"Re: [rfc 2/3] powerpc/mce: Extract physical_address for UE errors","submitter":{"id":69518,"url":"http://patchwork.ozlabs.org/api/people/69518/","name":"Nicholas Piggin","email":"npiggin@gmail.com"},"content":"On Tue, 5 Sep 2017 14:15:54 +1000\nBalbir Singh wrote:\n\n> Walk the page table for NIP and extract the instruction. Then\n> use the instruction to find the effective address via analyse_instr().\n> \n> We might have page table walking races, but we expect them to\n> be rare, the physical address extraction is best effort. The idea\n> is to then hook up this infrastructure to memory failure eventually.\n\nCool. Too bad hardware doesn't give us the RA.\n\n> \n> Signed-off-by: Balbir Singh \n> ---\n> arch/powerpc/include/asm/mce.h | 2 +-\n> arch/powerpc/kernel/mce.c | 6 ++++-\n> arch/powerpc/kernel/mce_power.c | 60 +++++++++++++++++++++++++++++++++++++----\n> 3 files changed, 61 insertions(+), 7 deletions(-)\n> \n> diff --git a/arch/powerpc/include/asm/mce.h b/arch/powerpc/include/asm/mce.h\n> index 75292c7..3a1226e 100644\n> --- a/arch/powerpc/include/asm/mce.h\n> +++ b/arch/powerpc/include/asm/mce.h\n> @@ -204,7 +204,7 @@ struct mce_error_info {\n> \n> extern void save_mce_event(struct pt_regs *regs, long handled,\n> \t\t\t struct mce_error_info *mce_err, uint64_t nip,\n> -\t\t\t uint64_t addr);\n> +\t\t\t uint64_t addr, uint64_t phys_addr);\n> extern int get_mce_event(struct machine_check_event *mce, bool release);\n> extern void release_mce_event(void);\n> extern void machine_check_queue_event(void);\n> diff --git a/arch/powerpc/kernel/mce.c b/arch/powerpc/kernel/mce.c\n> index e254399..f41a75d 100644\n> --- a/arch/powerpc/kernel/mce.c\n> +++ b/arch/powerpc/kernel/mce.c\n> @@ -82,7 +82,7 @@ static void mce_set_error_info(struct machine_check_event *mce,\n> */\n> void save_mce_event(struct pt_regs *regs, long handled,\n> \t\t struct mce_error_info *mce_err,\n> -\t\t uint64_t nip, uint64_t addr)\n> +\t\t uint64_t nip, uint64_t addr, uint64_t phys_addr)\n> {\n> \tint index = __this_cpu_inc_return(mce_nest_count) - 1;\n> \tstruct machine_check_event *mce = this_cpu_ptr(&mce_event[index]);\n> @@ -140,6 +140,10 @@ void save_mce_event(struct pt_regs *regs, long handled,\n> \t} else if (mce->error_type == MCE_ERROR_TYPE_UE) {\n> \t\tmce->u.ue_error.effective_address_provided = true;\n> \t\tmce->u.ue_error.effective_address = addr;\n> +\t\tif (phys_addr != ULONG_MAX) {\n> +\t\t\tmce->u.ue_error.physical_address_provided = true;\n> +\t\t\tmce->u.ue_error.physical_address = phys_addr;\n> +\t\t}\n> \t}\n> \treturn;\n> }\n> diff --git a/arch/powerpc/kernel/mce_power.c b/arch/powerpc/kernel/mce_power.c\n> index b76ca19..b77a698 100644\n> --- a/arch/powerpc/kernel/mce_power.c\n> +++ b/arch/powerpc/kernel/mce_power.c\n> @@ -27,6 +27,25 @@\n> #include \n> #include \n> #include \n> +#include \n> +#include \n> +#include \n> +\n> +static unsigned long addr_to_pfn(struct mm_struct *mm, unsigned long addr)\n> +{\n> +\tpte_t *ptep;\n> +\tunsigned long flags;\n> +\n> +\tlocal_irq_save(flags);\n> +\tif (mm == current->mm)\n> +\t\tptep = find_current_mm_pte(mm->pgd, addr, NULL, NULL);\n> +\telse\n> +\t\tptep = find_init_mm_pte(addr, NULL);\n> +\tlocal_irq_restore(flags);\n> +\tif (!ptep)\n> +\t\treturn ULONG_MAX;\n> +\treturn pte_pfn(*ptep);\n\nI think you need to check that it's still cacheable memory here?\n!pte_speical && pfn <= highest_memmap_pfn?\n\n\n> +}\n> \n> static void flush_tlb_206(unsigned int num_sets, unsigned int action)\n> {\n> @@ -489,7 +508,8 @@ static int mce_handle_ierror(struct pt_regs *regs,\n> \n> static int mce_handle_derror(struct pt_regs *regs,\n> \t\tconst struct mce_derror_table table[],\n> -\t\tstruct mce_error_info *mce_err, uint64_t *addr)\n> +\t\tstruct mce_error_info *mce_err, uint64_t *addr,\n> +\t\tuint64_t *phys_addr)\n> {\n> \tuint64_t dsisr = regs->dsisr;\n> \tint handled = 0;\n> @@ -555,7 +575,37 @@ static int mce_handle_derror(struct pt_regs *regs,\n> \t\tmce_err->initiator = table[i].initiator;\n> \t\tif (table[i].dar_valid)\n> \t\t\t*addr = regs->dar;\n> -\n> +\t\telse if (mce_err->severity == MCE_SEV_ERROR_SYNC &&\n> +\t\t\t\ttable[i].error_type == MCE_ERROR_TYPE_UE) {\n> +\t\t\t/*\n> +\t\t\t * Carefully look at the NIP to determine\n> +\t\t\t * the instruction to analyse. Reading the NIP\n> +\t\t\t * in real-mode is tricky and can lead to recursive\n> +\t\t\t * faults\n> +\t\t\t */\n\nWhat recursive faults? If you ensure NIP is cacheable memory, I guess you\ncan get a recursive machine check from reading it, but that's probably\ntolerable.\n\n> +\t\t\tint instr;\n> +\t\t\tstruct mm_struct *mm;\n> +\t\t\tunsigned long nip = regs->nip;\n> +\t\t\tunsigned long pfn = 0, instr_addr;\n> +\t\t\tstruct instruction_op op;\n> +\t\t\tstruct pt_regs tmp = *regs;\n> +\n> +\t\t\tif (user_mode(regs))\n> +\t\t\t\tmm = current->mm;\n> +\t\t\telse\n> +\t\t\t\tmm = &init_mm;\n> +\n> +\t\t\tpfn = addr_to_pfn(mm, nip);\n> +\t\t\tif (pfn != ULONG_MAX) {\n> +\t\t\t\tinstr_addr = (pfn << PAGE_SHIFT) + (nip & ~PAGE_MASK);\n> +\t\t\t\tinstr = *(unsigned int *)(instr_addr);\n> +\t\t\t\tif (!analyse_instr(&op, &tmp, instr)) {\n> +\t\t\t\t\tpfn = addr_to_pfn(mm, op.ea);\n> +\t\t\t\t\t*addr = op.ea;\n> +\t\t\t\t\t*phys_addr = pfn;\n> +\t\t\t\t}\n\nInstruction may no longer be a load/store at this point, right? Or\ninstruction or page tables could have changed so this does not point to\na valid pfn of cacheable memory. memory_failure() has some checks, but\nI wouldn't mind if you put some checks in here so you can enumerate all\nthe ways this can go wrong :P\n\nHopefully after Paulus's instruction analyzer rework you'll be able to\navoid the pt_regs on stack, but that's probably okay for a backport.\nMCEs have a lot of stack and don't use too much.\n\nThanks,\nNick","headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org","linuxppc-dev@ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xn4SF5d5xz9t2y\n\tfor ;\n\tWed, 6 Sep 2017 10:38:05 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xn4SF4JCYzDrLC\n\tfor ;\n\tWed, 6 Sep 2017 10:38:05 +1000 (AEST)","from ozlabs.org (bilbo.ozlabs.org [103.22.144.67])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xn4Qb3jnvzDrFT\n\tfor ;\n\tWed, 6 Sep 2017 10:36:39 +1000 (AEST)","from ozlabs.org (ozlabs.org [IPv6:2401:3900:2:1::2])\n\tby bilbo.ozlabs.org (Postfix) with ESMTP id 3xn4QZ45tfz8tS1\n\tfor ;\n\tWed, 6 Sep 2017 10:36:38 +1000 (AEST)","by ozlabs.org (Postfix)\n\tid 3xn4QZ3l8Vz9t3f; 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x86_64-pc-linux-gnu)","MIME-Version":"1.0","Content-Type":"text/plain; charset=US-ASCII","Content-Transfer-Encoding":"7bit","X-BeenThere":"linuxppc-dev@lists.ozlabs.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"Linux on PowerPC Developers Mail List\n\t","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"linuxppc-dev@ozlabs.org, mahesh@linux.vnet.ibm.com,\n\tPaul Mackerras , alistair@popple.id.au","Errors-To":"linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org","Sender":"\"Linuxppc-dev\"\n\t"}},{"id":1763808,"web_url":"http://patchwork.ozlabs.org/comment/1763808/","msgid":"","date":"2017-09-06T04:37:05","subject":"Re: [rfc 2/3] powerpc/mce: Extract physical_address for UE errors","submitter":{"id":9347,"url":"http://patchwork.ozlabs.org/api/people/9347/","name":"Balbir Singh","email":"bsingharora@gmail.com"},"content":"On Wed, Sep 6, 2017 at 10:36 AM, Nicholas Piggin wrote:\n> On Tue, 5 Sep 2017 14:15:54 +1000\n> Balbir Singh wrote:\n>\n>> Walk the page table for NIP and extract the instruction. Then\n>> use the instruction to find the effective address via analyse_instr().\n>>\n>> We might have page table walking races, but we expect them to\n>> be rare, the physical address extraction is best effort. The idea\n>> is to then hook up this infrastructure to memory failure eventually.\n>\n> Cool. Too bad hardware doesn't give us the RA.\n>\n>>\n>> Signed-off-by: Balbir Singh \n>> ---\n>> arch/powerpc/include/asm/mce.h | 2 +-\n>> arch/powerpc/kernel/mce.c | 6 ++++-\n>> arch/powerpc/kernel/mce_power.c | 60 +++++++++++++++++++++++++++++++++++++----\n>> 3 files changed, 61 insertions(+), 7 deletions(-)\n>>\n>> diff --git a/arch/powerpc/include/asm/mce.h b/arch/powerpc/include/asm/mce.h\n>> index 75292c7..3a1226e 100644\n>> --- a/arch/powerpc/include/asm/mce.h\n>> +++ b/arch/powerpc/include/asm/mce.h\n>> @@ -204,7 +204,7 @@ struct mce_error_info {\n>>\n>> extern void save_mce_event(struct pt_regs *regs, long handled,\n>> struct mce_error_info *mce_err, uint64_t nip,\n>> - uint64_t addr);\n>> + uint64_t addr, uint64_t phys_addr);\n>> extern int get_mce_event(struct machine_check_event *mce, bool release);\n>> extern void release_mce_event(void);\n>> extern void machine_check_queue_event(void);\n>> diff --git a/arch/powerpc/kernel/mce.c b/arch/powerpc/kernel/mce.c\n>> index e254399..f41a75d 100644\n>> --- a/arch/powerpc/kernel/mce.c\n>> +++ b/arch/powerpc/kernel/mce.c\n>> @@ -82,7 +82,7 @@ static void mce_set_error_info(struct machine_check_event *mce,\n>> */\n>> void save_mce_event(struct pt_regs *regs, long handled,\n>> struct mce_error_info *mce_err,\n>> - uint64_t nip, uint64_t addr)\n>> + uint64_t nip, uint64_t addr, uint64_t phys_addr)\n>> {\n>> int index = __this_cpu_inc_return(mce_nest_count) - 1;\n>> struct machine_check_event *mce = this_cpu_ptr(&mce_event[index]);\n>> @@ -140,6 +140,10 @@ void save_mce_event(struct pt_regs *regs, long handled,\n>> } else if (mce->error_type == MCE_ERROR_TYPE_UE) {\n>> mce->u.ue_error.effective_address_provided = true;\n>> mce->u.ue_error.effective_address = addr;\n>> + if (phys_addr != ULONG_MAX) {\n>> + mce->u.ue_error.physical_address_provided = true;\n>> + mce->u.ue_error.physical_address = phys_addr;\n>> + }\n>> }\n>> return;\n>> }\n>> diff --git a/arch/powerpc/kernel/mce_power.c b/arch/powerpc/kernel/mce_power.c\n>> index b76ca19..b77a698 100644\n>> --- a/arch/powerpc/kernel/mce_power.c\n>> +++ b/arch/powerpc/kernel/mce_power.c\n>> @@ -27,6 +27,25 @@\n>> #include \n>> #include \n>> #include \n>> +#include \n>> +#include \n>> +#include \n>> +\n>> +static unsigned long addr_to_pfn(struct mm_struct *mm, unsigned long addr)\n>> +{\n>> + pte_t *ptep;\n>> + unsigned long flags;\n>> +\n>> + local_irq_save(flags);\n>> + if (mm == current->mm)\n>> + ptep = find_current_mm_pte(mm->pgd, addr, NULL, NULL);\n>> + else\n>> + ptep = find_init_mm_pte(addr, NULL);\n>> + local_irq_restore(flags);\n>> + if (!ptep)\n>> + return ULONG_MAX;\n>> + return pte_pfn(*ptep);\n>\n> I think you need to check that it's still cacheable memory here?\n> !pte_speical && pfn <= highest_memmap_pfn?\n>\n\nfind_*pte will return a NULL PTE, so we do have a check there. !pte_special is a\ngood check to have, I'll add it\n\n\n>\n>> +}\n>>\n>> static void flush_tlb_206(unsigned int num_sets, unsigned int action)\n>> {\n>> @@ -489,7 +508,8 @@ static int mce_handle_ierror(struct pt_regs *regs,\n>>\n>> static int mce_handle_derror(struct pt_regs *regs,\n>> const struct mce_derror_table table[],\n>> - struct mce_error_info *mce_err, uint64_t *addr)\n>> + struct mce_error_info *mce_err, uint64_t *addr,\n>> + uint64_t *phys_addr)\n>> {\n>> uint64_t dsisr = regs->dsisr;\n>> int handled = 0;\n>> @@ -555,7 +575,37 @@ static int mce_handle_derror(struct pt_regs *regs,\n>> mce_err->initiator = table[i].initiator;\n>> if (table[i].dar_valid)\n>> *addr = regs->dar;\n>> -\n>> + else if (mce_err->severity == MCE_SEV_ERROR_SYNC &&\n>> + table[i].error_type == MCE_ERROR_TYPE_UE) {\n>> + /*\n>> + * Carefully look at the NIP to determine\n>> + * the instruction to analyse. Reading the NIP\n>> + * in real-mode is tricky and can lead to recursive\n>> + * faults\n>> + */\n>\n> What recursive faults? If you ensure NIP is cacheable memory, I guess you\n> can get a recursive machine check from reading it, but that's probably\n> tolerable.\n\n\nYep, just wanted to call it out here.\n\n>\n>> + int instr;\n>> + struct mm_struct *mm;\n>> + unsigned long nip = regs->nip;\n>> + unsigned long pfn = 0, instr_addr;\n>> + struct instruction_op op;\n>> + struct pt_regs tmp = *regs;\n>> +\n>> + if (user_mode(regs))\n>> + mm = current->mm;\n>> + else\n>> + mm = &init_mm;\n>> +\n>> + pfn = addr_to_pfn(mm, nip);\n>> + if (pfn != ULONG_MAX) {\n>> + instr_addr = (pfn << PAGE_SHIFT) + (nip & ~PAGE_MASK);\n>> + instr = *(unsigned int *)(instr_addr);\n>> + if (!analyse_instr(&op, &tmp, instr)) {\n>> + pfn = addr_to_pfn(mm, op.ea);\n>> + *addr = op.ea;\n>> + *phys_addr = pfn;\n>> + }\n>\n> Instruction may no longer be a load/store at this point, right? Or\n> instruction or page tables could have changed so this does not point to\n> a valid pfn of cacheable memory. memory_failure() has some checks, but\n> I wouldn't mind if you put some checks in here so you can enumerate all\n> the ways this can go wrong :P\n\nOK.. I'll add a comment or a warning to indicate the error, I suspect at this\npoint, it means we raced w.r.t pte entry or we had a bad NIP/EA. It could\nalso mean the opcode was not a load store.\n\n>\n> Hopefully after Paulus's instruction analyzer rework you'll be able to\n> avoid the pt_regs on stack, but that's probably okay for a backport.\n> MCEs have a lot of stack and don't use too much.\n>\n\nYep, I kept it so that it could be backported, but I can change it in\na follow-up\npatch\n\nThanks for the detailed review!\n\nBalbir Singh.","headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org","linuxppc-dev@ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xn9nt6bM9z9sNV\n\tfor ;\n\tWed, 6 Sep 2017 14:38:42 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xn9nt5RYVzDrRw\n\tfor ;\n\tWed, 6 Sep 2017 14:38:42 +1000 (AEST)","from ozlabs.org (ozlabs.org [IPv6:2401:3900:2:1::2])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xn9m55JGdzDrJL\n\tfor ;\n\tWed, 6 Sep 2017 14:37:09 +1000 (AEST)","from ozlabs.org (ozlabs.org [IPv6:2401:3900:2:1::2])\n\tby bilbo.ozlabs.org (Postfix) with ESMTP id 3xn9m53R9Pz8t37\n\tfor ;\n\tWed, 6 Sep 2017 14:37:09 +1000 (AEST)","by ozlabs.org (Postfix)\n\tid 3xn9m534wmz9sP3; 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charset=\"UTF-8\"","X-BeenThere":"linuxppc-dev@lists.ozlabs.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"Linux on PowerPC Developers Mail List\n\t","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"linuxppc-dev ,\n\tMahesh Jagannath Salgaonkar ,\n\tPaul Mackerras ,\n\tAlistair Popple ","Errors-To":"linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org","Sender":"\"Linuxppc-dev\"\n\t"}},{"id":1764424,"web_url":"http://patchwork.ozlabs.org/comment/1764424/","msgid":"<1504738572.2371.3.camel@au1.ibm.com>","date":"2017-09-06T22:56:12","subject":"Re: [rfc 2/3] powerpc/mce: Extract physical_address for UE errors","submitter":{"id":83,"url":"http://patchwork.ozlabs.org/api/people/83/","name":"Benjamin Herrenschmidt","email":"benh@au1.ibm.com"},"content":"On Tue, 2017-09-05 at 14:15 +1000, Balbir Singh wrote:\n> void save_mce_event(struct pt_regs *regs, long handled,\n> struct mce_error_info *mce_err,\n> - uint64_t nip, uint64_t addr)\n> + uint64_t nip, uint64_t addr, uint64_t phys_addr)\n> {\n> int index = __this_cpu_inc_return(mce_nest_count) - 1;\n> struct machine_check_event *mce = this_cpu_ptr(&mce_event[index]);\n> @@ -140,6 +140,10 @@ void save_mce_event(struct pt_regs *regs, long handled,\n> } else if (mce->error_type == MCE_ERROR_TYPE_UE) {\n> mce->u.ue_error.effective_address_provided = true;\n> mce->u.ue_error.effective_address = addr;\n> + if (phys_addr != ULONG_MAX) {\n> + mce->u.ue_error.physical_address_provided = true;\n> + mce->u.ue_error.physical_address = phys_addr;\n> + }\n> }\n> return;\n\nWhere is \"addr\" coming from ? Keep in mind that on P9 at least, a UE\nwill *not* give you an EA in DAR in most cases.\n\nBen.","headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org","linuxppc-dev@ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xnf9Y57vnz9t2R\n\tfor ;\n\tThu, 7 Sep 2017 08:57:21 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xnf9Y3VplzDrWj\n\tfor ;\n\tThu, 7 Sep 2017 08:57:21 +1000 (AEST)","from ozlabs.org (bilbo.ozlabs.org [103.22.144.67])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xnf8P4ssNzDrVk\n\tfor ;\n\tThu, 7 Sep 2017 08:56:21 +1000 (AEST)","from ozlabs.org (bilbo.ozlabs.org [103.22.144.67])\n\tby bilbo.ozlabs.org (Postfix) with ESMTP id 3xnf8P4L16z8w2j\n\tfor ;\n\tThu, 7 Sep 2017 08:56:21 +1000 (AEST)","by ozlabs.org (Postfix)\n\tid 3xnf8P42Pbz9t2r; Thu, 7 Sep 2017 08:56:21 +1000 (AEST)","from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com\n\t[148.163.156.1])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xnf8P1LY0z9t2R\n\tfor ; Thu, 7 Sep 2017 08:56:20 +1000 (AEST)","from pps.filterd (m0098410.ppops.net [127.0.0.1])\n\tby mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv86MrfYM135865\n\tfor ; Wed, 6 Sep 2017 18:56:18 -0400","from e23smtp07.au.ibm.com (e23smtp07.au.ibm.com [202.81.31.140])\n\tby mx0a-001b2d01.pphosted.com with ESMTP id 2ctsxdrtj1-1\n\t(version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT)\n\tfor ; Wed, 06 Sep 2017 18:56:18 -0400","from localhost\n\tby e23smtp07.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! 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Keep in mind that on P9 at least, a UE\n> will *not* give you an EA in DAR in most cases.\n\nThe EA is derived in mce_handle_derror() via page table walk and\nanalyse_instr(), its the best\nwe can do FWIK\n\nBalbir Singh.","headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org","linuxppc-dev@ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xnk561Ggfz9s8J\n\tfor ;\n\tThu, 7 Sep 2017 11:53:46 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xnk556zlZzDrWX\n\tfor ;\n\tThu, 7 Sep 2017 11:53:45 +1000 (AEST)","from ozlabs.org (bilbo.ozlabs.org [103.22.144.67])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xnk3R0HTFzDrVm\n\tfor ;\n\tThu, 7 Sep 2017 11:52:19 +1000 (AEST)","from ozlabs.org (ozlabs.org [IPv6:2401:3900:2:1::2])\n\tby bilbo.ozlabs.org (Postfix) with ESMTP id 3xnk3Q6hWFz8shS\n\tfor ;\n\tThu, 7 Sep 2017 11:52:18 +1000 (AEST)","by ozlabs.org (Postfix)\n\tid 3xnk3Q6W1Xz9t2v; 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charset=\"UTF-8\"","X-BeenThere":"linuxppc-dev@lists.ozlabs.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"Linux on PowerPC Developers Mail List\n\t","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"linuxppc-dev ,\n\tMahesh Jagannath Salgaonkar ,\n\tNicholas Piggin ,\n\tAlistair Popple ","Errors-To":"linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org","Sender":"\"Linuxppc-dev\"\n\t"}},{"id":1765066,"web_url":"http://patchwork.ozlabs.org/comment/1765066/","msgid":"<910bf7a9-a7e1-9f26-2f63-88578bed72a6@linux.vnet.ibm.com>","date":"2017-09-08T03:41:24","subject":"Re: [rfc 2/3] powerpc/mce: Extract physical_address for UE errors","submitter":{"id":1436,"url":"http://patchwork.ozlabs.org/api/people/1436/","name":"Mahesh J Salgaonkar","email":"mahesh@linux.vnet.ibm.com"},"content":"On 09/05/2017 09:45 AM, Balbir Singh wrote:\n> Walk the page table for NIP and extract the instruction. Then\n> use the instruction to find the effective address via analyse_instr().\n> \n> We might have page table walking races, but we expect them to\n> be rare, the physical address extraction is best effort. The idea\n> is to then hook up this infrastructure to memory failure eventually.\n> \n> Signed-off-by: Balbir Singh \n> ---\n> arch/powerpc/include/asm/mce.h | 2 +-\n> arch/powerpc/kernel/mce.c | 6 ++++-\n> arch/powerpc/kernel/mce_power.c | 60 +++++++++++++++++++++++++++++++++++++----\n> 3 files changed, 61 insertions(+), 7 deletions(-)\n> \n> diff --git a/arch/powerpc/include/asm/mce.h b/arch/powerpc/include/asm/mce.h\n> index 75292c7..3a1226e 100644\n> --- a/arch/powerpc/include/asm/mce.h\n> +++ b/arch/powerpc/include/asm/mce.h\n> @@ -204,7 +204,7 @@ struct mce_error_info {\n> \n> extern void save_mce_event(struct pt_regs *regs, long handled,\n> \t\t\t struct mce_error_info *mce_err, uint64_t nip,\n> -\t\t\t uint64_t addr);\n> +\t\t\t uint64_t addr, uint64_t phys_addr);\n> extern int get_mce_event(struct machine_check_event *mce, bool release);\n> extern void release_mce_event(void);\n> extern void machine_check_queue_event(void);\n> diff --git a/arch/powerpc/kernel/mce.c b/arch/powerpc/kernel/mce.c\n> index e254399..f41a75d 100644\n> --- a/arch/powerpc/kernel/mce.c\n> +++ b/arch/powerpc/kernel/mce.c\n> @@ -82,7 +82,7 @@ static void mce_set_error_info(struct machine_check_event *mce,\n> */\n> void save_mce_event(struct pt_regs *regs, long handled,\n> \t\t struct mce_error_info *mce_err,\n> -\t\t uint64_t nip, uint64_t addr)\n> +\t\t uint64_t nip, uint64_t addr, uint64_t phys_addr)\n> {\n> \tint index = __this_cpu_inc_return(mce_nest_count) - 1;\n> \tstruct machine_check_event *mce = this_cpu_ptr(&mce_event[index]);\n> @@ -140,6 +140,10 @@ void save_mce_event(struct pt_regs *regs, long handled,\n> \t} else if (mce->error_type == MCE_ERROR_TYPE_UE) {\n> \t\tmce->u.ue_error.effective_address_provided = true;\n> \t\tmce->u.ue_error.effective_address = addr;\n> +\t\tif (phys_addr != ULONG_MAX) {\n> +\t\t\tmce->u.ue_error.physical_address_provided = true;\n> +\t\t\tmce->u.ue_error.physical_address = phys_addr;\n> +\t\t}\n> \t}\n> \treturn;\n> }\n> diff --git a/arch/powerpc/kernel/mce_power.c b/arch/powerpc/kernel/mce_power.c\n> index b76ca19..b77a698 100644\n> --- a/arch/powerpc/kernel/mce_power.c\n> +++ b/arch/powerpc/kernel/mce_power.c\n> @@ -27,6 +27,25 @@\n> #include \n> #include \n> #include \n> +#include \n> +#include \n> +#include \n> +\n> +static unsigned long addr_to_pfn(struct mm_struct *mm, unsigned long addr)\n> +{\n> +\tpte_t *ptep;\n> +\tunsigned long flags;\n> +\n> +\tlocal_irq_save(flags);\n> +\tif (mm == current->mm)\n> +\t\tptep = find_current_mm_pte(mm->pgd, addr, NULL, NULL);\n> +\telse\n> +\t\tptep = find_init_mm_pte(addr, NULL);\n> +\tlocal_irq_restore(flags);\n> +\tif (!ptep)\n> +\t\treturn ULONG_MAX;\n> +\treturn pte_pfn(*ptep);\n> +}\n> \n> static void flush_tlb_206(unsigned int num_sets, unsigned int action)\n> {\n> @@ -489,7 +508,8 @@ static int mce_handle_ierror(struct pt_regs *regs,\n> \n> static int mce_handle_derror(struct pt_regs *regs,\n> \t\tconst struct mce_derror_table table[],\n> -\t\tstruct mce_error_info *mce_err, uint64_t *addr)\n> +\t\tstruct mce_error_info *mce_err, uint64_t *addr,\n> +\t\tuint64_t *phys_addr)\n> {\n> \tuint64_t dsisr = regs->dsisr;\n> \tint handled = 0;\n> @@ -555,7 +575,37 @@ static int mce_handle_derror(struct pt_regs *regs,\n> \t\tmce_err->initiator = table[i].initiator;\n> \t\tif (table[i].dar_valid)\n> \t\t\t*addr = regs->dar;\n> -\n> +\t\telse if (mce_err->severity == MCE_SEV_ERROR_SYNC &&\n> +\t\t\t\ttable[i].error_type == MCE_ERROR_TYPE_UE) {\n> +\t\t\t/*\n> +\t\t\t * Carefully look at the NIP to determine\n> +\t\t\t * the instruction to analyse. Reading the NIP\n> +\t\t\t * in real-mode is tricky and can lead to recursive\n> +\t\t\t * faults\n> +\t\t\t */\n> +\t\t\tint instr;\n> +\t\t\tstruct mm_struct *mm;\n> +\t\t\tunsigned long nip = regs->nip;\n> +\t\t\tunsigned long pfn = 0, instr_addr;\n> +\t\t\tstruct instruction_op op;\n> +\t\t\tstruct pt_regs tmp = *regs;\n> +\n> +\t\t\tif (user_mode(regs))\n> +\t\t\t\tmm = current->mm;\n> +\t\t\telse\n> +\t\t\t\tmm = &init_mm;\n> +\n> +\t\t\tpfn = addr_to_pfn(mm, nip);\n> +\t\t\tif (pfn != ULONG_MAX) {\n> +\t\t\t\tinstr_addr = (pfn << PAGE_SHIFT) + (nip & ~PAGE_MASK);\n> +\t\t\t\tinstr = *(unsigned int *)(instr_addr);\n> +\t\t\t\tif (!analyse_instr(&op, &tmp, instr)) {\n> +\t\t\t\t\tpfn = addr_to_pfn(mm, op.ea);\n> +\t\t\t\t\t*addr = op.ea;\n> +\t\t\t\t\t*phys_addr = pfn;\n> +\t\t\t\t}\n> +\t\t\t}\n> +\t\t}\n> \t\tfound = 1;\n> \t}\n> \n> @@ -592,19 +642,19 @@ static long mce_handle_error(struct pt_regs *regs,\n> \t\tconst struct mce_ierror_table itable[])\n> {\n> \tstruct mce_error_info mce_err = { 0 };\n> -\tuint64_t addr;\n> +\tuint64_t addr, phys_addr;\n\nYou may want to initialize phys_addr with ULONG_MAX.\n\n> \tuint64_t srr1 = regs->msr;\n> \tlong handled;\n> \n> \tif (SRR1_MC_LOADSTORE(srr1))\n> -\t\thandled = mce_handle_derror(regs, dtable, &mce_err, &addr);\n> +\t\thandled = mce_handle_derror(regs, dtable, &mce_err, &addr, &phys_addr);\n> \telse\n> \t\thandled = mce_handle_ierror(regs, itable, &mce_err, &addr);\n> \n> \tif (!handled && mce_err.error_type == MCE_ERROR_TYPE_UE)\n> \t\thandled = mce_handle_ue_error(regs);\n> \n> -\tsave_mce_event(regs, handled, &mce_err, regs->nip, addr);\n> +\tsave_mce_event(regs, handled, &mce_err, regs->nip, addr, phys_addr);\n> \n> \treturn handled;\n> }\n> \n\nThanks,\n-Mahesh.","headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org","linuxppc-dev@ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xpNTp0kr0z9sPk\n\tfor ;\n\tFri, 8 Sep 2017 13:43:58 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xpNTp0103zDrZQ\n\tfor ;\n\tFri, 8 Sep 2017 13:43:58 +1000 (AEST)","from ozlabs.org (ozlabs.org [IPv6:2401:3900:2:1::2])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xpNR772dFzDrYp\n\tfor ;\n\tFri, 8 Sep 2017 13:41:39 +1000 (AEST)","from ozlabs.org (ozlabs.org [IPv6:2401:3900:2:1::2])\n\tby bilbo.ozlabs.org (Postfix) with ESMTP id 3xpNR72d3Kz8tNJ\n\tfor ;\n\tFri, 8 Sep 2017 13:41:39 +1000 (AEST)","by ozlabs.org (Postfix)\n\tid 3xpNR71H15z9sMN; Fri, 8 Sep 2017 13:41:39 +1000 (AEST)","from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com\n\t[148.163.158.5])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xpNR42tjYz9t2Q\n\tfor ; Fri, 8 Sep 2017 13:41:35 +1000 (AEST)","from pps.filterd (m0098416.ppops.net [127.0.0.1])\n\tby mx0b-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv883dYL0126614\n\tfor ; Thu, 7 Sep 2017 23:41:33 -0400","from e23smtp04.au.ibm.com (e23smtp04.au.ibm.com [202.81.31.146])\n\tby mx0b-001b2d01.pphosted.com with ESMTP id 2cuc9mum4q-1\n\t(version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT)\n\tfor ; Thu, 07 Sep 2017 23:41:33 -0400","from localhost\n\tby e23smtp04.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! 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