[{"id":1763054,"web_url":"http://patchwork.ozlabs.org/comment/1763054/","msgid":"","date":"2017-09-05T08:10:03","subject":"Re: [PATCH 2/2] powerpc/powernv/npu: Don't explicitly flush nmmu tlb","submitter":{"id":67555,"url":"http://patchwork.ozlabs.org/api/people/67555/","name":"Frederic Barrat","email":"fbarrat@linux.vnet.ibm.com"},"content":"Le 05/09/2017 à 05:57, Alistair Popple a écrit :\n> The nest mmu required an explicit flush as a tlbi would not flush it in the\n> same way as the core. However an alternate firmware fix exists which should\n> eliminate the need for this flush, so instead add a device-tree property\n> (ibm,nmmu-flush) on the NVLink2 PHB to enable it only if required.\n> \n> Signed-off-by: Alistair Popple \n> ---\n> arch/powerpc/platforms/powernv/npu-dma.c | 28 +++++++++++++++++++++++-----\n> arch/powerpc/platforms/powernv/pci.h | 3 +++\n> 2 files changed, 26 insertions(+), 5 deletions(-)\n> \n> diff --git a/arch/powerpc/platforms/powernv/npu-dma.c b/arch/powerpc/platforms/powernv/npu-dma.c\n> index 2fff9a65..4b4fcac 100644\n> --- a/arch/powerpc/platforms/powernv/npu-dma.c\n> +++ b/arch/powerpc/platforms/powernv/npu-dma.c\n> @@ -395,6 +395,7 @@ struct npu_context {\n> \tstruct pci_dev *npdev[NV_MAX_NPUS][NV_MAX_LINKS];\n> \tstruct mmu_notifier mn;\n> \tstruct kref kref;\n> +\tbool nmmu_flush;\n> \n> \t/* Callback to stop translation requests on a given GPU */\n> \tstruct npu_context *(*release_cb)(struct npu_context *, void *);\n> @@ -545,11 +546,13 @@ static void mmio_invalidate(struct npu_context *npu_context, int va,\n> \tstruct mmio_atsd_reg mmio_atsd_reg[NV_MAX_NPUS];\n> \tunsigned long pid = npu_context->mm->context.id;\n> \n> -\t/*\n> -\t * Unfortunately the nest mmu does not support flushing specific\n> -\t * addresses so we have to flush the whole mm.\n> -\t */\n> -\tflush_all_mm(npu_context->mm);\n> +\tif (npu_context->nmmu_flush)\n> +\t\t/*\n> +\t\t * Unfortunately the nest mmu does not support flushing specific\n> +\t\t * addresses so we have to flush the whole mm once before\n> +\t\t * shooting down the GPU translation.\n> +\t\t */\n> +\t\tflush_all_mm(npu_context->mm);\n> \n> \t/*\n> \t * Loop over all the NPUs this process is active on and launch\n> @@ -722,6 +725,16 @@ struct npu_context *pnv_npu2_init_context(struct pci_dev *gpdev,\n> \t\treturn ERR_PTR(-ENODEV);\n> \tnpu_context->npdev[npu->index][nvlink_index] = npdev;\n> \n> +\tif (!nphb->npu.nmmu_flush) {\n> +\t\t/*\n> +\t\t * If we're not explicitly flushing ourselves we need to mark\n> +\t\t * the thread for global flushes\n> +\t\t */\n> +\t\tnpu_context->nmmu_flush = false;\n> +\t\tinc_mm_active_cpus(mm);\n\n\nI can see that you use the inc_mm_active_cpus()/dec_mm_active_cpus() and \nnot the new mm_context_add_copro()/mm_context_remove_copro(). The only \ndifference is that mm_context_remove_copro() adds an extra flush of the \nfull mm (pwc and tlb) before decrementing the active cpu count.\n\nBut don't you need the flush when releasing the context? As soon as the \nactive cpu count is decremented, the next TLBI may be local and not \nvisible to the nMMU, so the nMMU could keep obsolete/wrong entries in \nits cache.\n\n Fred\n\n\n\n> +\t} else\n> +\t\tnpu_context->nmmu_flush = true;\n> +\n> \treturn npu_context;\n> }\n> EXPORT_SYMBOL(pnv_npu2_init_context);\n> @@ -731,6 +744,9 @@ static void pnv_npu2_release_context(struct kref *kref)\n> \tstruct npu_context *npu_context =\n> \t\tcontainer_of(kref, struct npu_context, kref);\n> \n> +\tif (!npu_context->nmmu_flush)\n> +\t\tdec_mm_active_cpus(npu_context->mm);\n> +\n> \tnpu_context->mm->context.npu_context = NULL;\n> \tmmu_notifier_unregister(&npu_context->mn,\n> \t\t\t\tnpu_context->mm);\n> @@ -819,6 +835,8 @@ int pnv_npu2_init(struct pnv_phb *phb)\n> \tstatic int npu_index;\n> \tuint64_t rc = 0;\n> \n> +\tphb->npu.nmmu_flush =\n> +\t\tof_property_read_bool(phb->hose->dn, \"ibm,nmmu-flush\");\n> \tfor_each_child_of_node(phb->hose->dn, dn) {\n> \t\tgpdev = pnv_pci_get_gpu_dev(get_pci_dev(dn));\n> \t\tif (gpdev) {\n> diff --git a/arch/powerpc/platforms/powernv/pci.h b/arch/powerpc/platforms/powernv/pci.h\n> index a95273c..22025c6 100644\n> --- a/arch/powerpc/platforms/powernv/pci.h\n> +++ b/arch/powerpc/platforms/powernv/pci.h\n> @@ -187,6 +187,9 @@ struct pnv_phb {\n> \n> \t\t/* Bitmask for MMIO register usage */\n> \t\tunsigned long mmio_atsd_usage;\n> +\n> +\t\t/* Do we need to explicitly flush the nest mmu? */\n> +\t\tbool nmmu_flush;\n> \t} npu;\n> \n> #ifdef CONFIG_CXL_BASE\n>","headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xmfZD6FgDz9s0g\n\tfor ;\n\tTue, 5 Sep 2017 18:11:48 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xmfZD5RVhzDrL8\n\tfor ;\n\tTue, 5 Sep 2017 18:11:48 +1000 (AEST)","from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com\n\t[148.163.156.1])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xmfXS2PqbzDrHr\n\tfor ;\n\tTue, 5 Sep 2017 18:10:16 +1000 (AEST)","from pps.filterd (m0098396.ppops.net [127.0.0.1])\n\tby mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv8589pAu108482\n\tfor ; Tue, 5 Sep 2017 04:10:14 -0400","from e06smtp15.uk.ibm.com (e06smtp15.uk.ibm.com [195.75.94.111])\n\tby mx0a-001b2d01.pphosted.com with ESMTP id 2csks2mb9r-1\n\t(version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT)\n\tfor ; Tue, 05 Sep 2017 04:10:12 -0400","from localhost\n\tby e06smtp15.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! 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Violators will be prosecuted; \n\tTue, 5 Sep 2017 09:10:05 +0100","from d06av23.portsmouth.uk.ibm.com (d06av23.portsmouth.uk.ibm.com\n\t[9.149.105.59])\n\tby b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with\n\tESMTP id v858A4Xn29032506; Tue, 5 Sep 2017 08:10:04 GMT","from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1])\n\tby IMSVA (Postfix) with ESMTP id 87D91A4053;\n\tTue, 5 Sep 2017 09:06:25 +0100 (BST)","from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1])\n\tby IMSVA (Postfix) with ESMTP id E17F4A4051;\n\tTue, 5 Sep 2017 09:06:24 +0100 (BST)","from [9.164.145.197] (unknown [9.164.145.197])\n\tby d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP;\n\tTue, 5 Sep 2017 09:06:24 +0100 (BST)"],"Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com\n\t(client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com;\n\tenvelope-from=fbarrat@linux.vnet.ibm.com; receiver=)","Subject":"Re: [PATCH 2/2] powerpc/powernv/npu: Don't explicitly flush nmmu tlb","To":"Alistair Popple , linuxppc-dev@lists.ozlabs.org","References":"<1504583864-8169-1-git-send-email-alistair@popple.id.au>\n\t<1504583864-8169-2-git-send-email-alistair@popple.id.au>","From":"Frederic Barrat ","Date":"Tue, 5 Sep 2017 10:10:03 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"<1504583864-8169-2-git-send-email-alistair@popple.id.au>","Content-Type":"text/plain; charset=utf-8; format=flowed","Content-Language":"en-US","Content-Transfer-Encoding":"8bit","X-TM-AS-GCONF":"00","x-cbid":"17090508-0020-0000-0000-000003B3A236","X-IBM-AV-DETECTION":"SAVI=unused REMOTE=unused XFE=unused","x-cbparentid":"17090508-0021-0000-0000-000042440A08","Message-Id":"","X-Proofpoint-Virus-Version":"vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-09-05_03:, , signatures=0","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n\tspamscore=0 suspectscore=0\n\tmalwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam\n\tadjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000\n\tdefinitions=main-1709050125","X-BeenThere":"linuxppc-dev@lists.ozlabs.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"Linux on PowerPC Developers Mail List\n\t","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"andrew.donnellan@au1.ibm.com, arbab@linux.vnet.ibm.com","Errors-To":"linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org","Sender":"\"Linuxppc-dev\"\n\t"}},{"id":1763259,"web_url":"http://patchwork.ozlabs.org/comment/1763259/","msgid":"<11943565.fESM0TqCRL@new-mexico>","date":"2017-09-05T11:48:59","subject":"Re: [PATCH 2/2] powerpc/powernv/npu: Don't explicitly flush nmmu tlb","submitter":{"id":24781,"url":"http://patchwork.ozlabs.org/api/people/24781/","name":"Alistair Popple","email":"alistair@popple.id.au"},"content":"Hi,\n\nOn Tue, 5 Sep 2017 10:10:03 AM Frederic Barrat wrote:\n> > \n> > +\tif (!nphb->npu.nmmu_flush) {\n> > +\t\t/*\n> > +\t\t * If we're not explicitly flushing ourselves we need to mark\n> > +\t\t * the thread for global flushes\n> > +\t\t */\n> > +\t\tnpu_context->nmmu_flush = false;\n> > +\t\tinc_mm_active_cpus(mm);\n> \n> \n> I can see that you use the inc_mm_active_cpus()/dec_mm_active_cpus() and \n> not the new mm_context_add_copro()/mm_context_remove_copro(). The only \n> difference is that mm_context_remove_copro() adds an extra flush of the \n> full mm (pwc and tlb) before decrementing the active cpu count.\n\nThanks for pointing that out, I'd overlooked the difference between the two.\n\n> But don't you need the flush when releasing the context? As soon as the \n> active cpu count is decremented, the next TLBI may be local and not \n> visible to the nMMU, so the nMMU could keep obsolete/wrong entries in \n> its cache.\n\nYes, I think you're right. In practice I doubt we'd ever hit it as the driver\nnever calls pnv_npu2_destroy_context() prior to the process being torn down\n(which should trigger the right global tlbies). But obviously something that\nneeds fixing so I will post a v2 ... thanks for reviewing!\n\nRegards,\n\nAlistair\n\n> Fred\n> \n> \n> \n> > +\t} else\n> > +\t\tnpu_context->nmmu_flush = true;\n> > +\n> > \treturn npu_context;\n> > }\n> > EXPORT_SYMBOL(pnv_npu2_init_context);\n> > @@ -731,6 +744,9 @@ static void pnv_npu2_release_context(struct kref *kref)\n> > \tstruct npu_context *npu_context =\n> > \t\tcontainer_of(kref, struct npu_context, kref);\n> > \n> > +\tif (!npu_context->nmmu_flush)\n> > +\t\tdec_mm_active_cpus(npu_context->mm);\n> > +\n> > \tnpu_context->mm->context.npu_context = NULL;\n> > \tmmu_notifier_unregister(&npu_context->mn,\n> > \t\t\t\tnpu_context->mm);\n> > @@ -819,6 +835,8 @@ int pnv_npu2_init(struct pnv_phb *phb)\n> > \tstatic int npu_index;\n> > \tuint64_t rc = 0;\n> > \n> > +\tphb->npu.nmmu_flush =\n> > +\t\tof_property_read_bool(phb->hose->dn, \"ibm,nmmu-flush\");\n> > \tfor_each_child_of_node(phb->hose->dn, dn) {\n> > \t\tgpdev = pnv_pci_get_gpu_dev(get_pci_dev(dn));\n> > \t\tif (gpdev) {\n> > diff --git a/arch/powerpc/platforms/powernv/pci.h b/arch/powerpc/platforms/powernv/pci.h\n> > index a95273c..22025c6 100644\n> > --- a/arch/powerpc/platforms/powernv/pci.h\n> > +++ b/arch/powerpc/platforms/powernv/pci.h\n> > @@ -187,6 +187,9 @@ struct pnv_phb {\n> > \n> > \t\t/* Bitmask for MMIO register usage */\n> > \t\tunsigned long mmio_atsd_usage;\n> > +\n> > +\t\t/* Do we need to explicitly flush the nest mmu? */\n> > +\t\tbool nmmu_flush;\n> > \t} npu;\n> > \n> > #ifdef CONFIG_CXL_BASE\n> > \n>","headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xmlQq6RxWz9sPs\n\tfor ;\n\tTue, 5 Sep 2017 21:50:43 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xmlQq5c95zDrLK\n\tfor ;\n\tTue, 5 Sep 2017 21:50:43 +1000 (AEST)","from ipmail01.adl6.internode.on.net (ipmail01.adl6.internode.on.net\n\t[150.101.137.136])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xmlNx1MJ8zDq8f\n\tfor ;\n\tTue, 5 Sep 2017 21:49:05 +1000 (AEST)","from ppp121-45-222-8.bras1.cbr2.internode.on.net (HELO\n\tnew-mexico.localnet) ([121.45.222.8])\n\tby ipmail01.adl6.internode.on.net with ESMTP;\n\t05 Sep 2017 21:19:02 +0930"],"Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=popple.id.au\n\t(client-ip=150.101.137.136; helo=ipmail01.adl6.internode.on.net;\n\tenvelope-from=alistair@popple.id.au; receiver=)","X-IronPort-Anti-Spam-Filtered":"true","X-IronPort-Anti-Spam-Result":"A2C9/wCLjq5ZAAjeLXlehSeGMoFMh2mPLAGaKkQBhH0EAgKEK0QUAwEBAQEBAQEPAQEBMk+FGQEFOhwjBQsLDgoJFRAPASkeBopDsxGMCYMqiFuKaQWgdJVDkX+WYjYggQ4cFhgJCBgZh3Yui0oBAQE","X-IronPort-SPAM":"SPAM","From":"Alistair Popple ","To":"Frederic Barrat ","Subject":"Re: [PATCH 2/2] powerpc/powernv/npu: Don't explicitly flush nmmu tlb","Date":"Tue, 05 Sep 2017 21:48:59 +1000","Message-ID":"<11943565.fESM0TqCRL@new-mexico>","User-Agent":"KMail/4.14.1 (Linux/4.9.0-0.bpo.3-amd64; KDE/4.14.2; x86_64; ; )","In-Reply-To":"","References":"<1504583864-8169-1-git-send-email-alistair@popple.id.au>\n\t<1504583864-8169-2-git-send-email-alistair@popple.id.au>\n\t","MIME-Version":"1.0","Content-Transfer-Encoding":"7Bit","Content-Type":"text/plain; charset=\"us-ascii\"","X-BeenThere":"linuxppc-dev@lists.ozlabs.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"Linux on PowerPC Developers Mail List\n\t","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"linuxppc-dev@lists.ozlabs.org, andrew.donnellan@au1.ibm.com,\n\tarbab@linux.vnet.ibm.com","Errors-To":"linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org","Sender":"\"Linuxppc-dev\"\n\t"}},{"id":1765074,"web_url":"http://patchwork.ozlabs.org/comment/1765074/","msgid":"<201709081201.0KTtjfCD%fengguang.wu@intel.com>","date":"2017-09-08T04:36:02","subject":"Re: [PATCH 2/2] powerpc/powernv/npu: Don't explicitly flush nmmu tlb","submitter":{"id":67315,"url":"http://patchwork.ozlabs.org/api/people/67315/","name":"kernel test robot","email":"lkp@intel.com"},"content":"Hi Alistair,\n\n[auto build test ERROR on powerpc/next]\n[also build test ERROR on next-20170907]\n[cannot apply to v4.13]\n[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]\n\nurl: https://github.com/0day-ci/linux/commits/Alistair-Popple/powerpc-npu-Use-flush_all_mm-instead-of-flush_tlb_mm/20170908-072908\nbase: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next\nconfig: powerpc-defconfig (attached as .config)\ncompiler: powerpc64-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705\nreproduce:\n wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross\n chmod +x ~/bin/make.cross\n # save the attached .config to linux build tree\n make.cross ARCH=powerpc \n\nAll errors (new ones prefixed by >>):\n\n arch/powerpc/platforms/powernv/npu-dma.c: In function 'mmio_invalidate':\n arch/powerpc/platforms/powernv/npu-dma.c:555:3: error: implicit declaration of function 'flush_all_mm' [-Werror=implicit-function-declaration]\n flush_all_mm(npu_context->mm);\n ^~~~~~~~~~~~\n arch/powerpc/platforms/powernv/npu-dma.c: In function 'pnv_npu2_init_context':\n>> arch/powerpc/platforms/powernv/npu-dma.c:744:3: error: implicit declaration of function 'inc_mm_active_cpus' [-Werror=implicit-function-declaration]\n inc_mm_active_cpus(mm);\n ^~~~~~~~~~~~~~~~~~\n arch/powerpc/platforms/powernv/npu-dma.c: In function 'pnv_npu2_release_context':\n>> arch/powerpc/platforms/powernv/npu-dma.c:758:3: error: implicit declaration of function 'dec_mm_active_cpus' [-Werror=implicit-function-declaration]\n dec_mm_active_cpus(npu_context->mm);\n ^~~~~~~~~~~~~~~~~~\n cc1: all warnings being treated as errors\n\nvim +/inc_mm_active_cpus +744 arch/powerpc/platforms/powernv/npu-dma.c\n\n 534\t\n 535\t/*\n 536\t * Invalidate either a single address or an entire PID depending on\n 537\t * the value of va.\n 538\t */\n 539\tstatic void mmio_invalidate(struct npu_context *npu_context, int va,\n 540\t\t\t\tunsigned long address, bool flush)\n 541\t{\n 542\t\tint i, j;\n 543\t\tstruct npu *npu;\n 544\t\tstruct pnv_phb *nphb;\n 545\t\tstruct pci_dev *npdev;\n 546\t\tstruct mmio_atsd_reg mmio_atsd_reg[NV_MAX_NPUS];\n 547\t\tunsigned long pid = npu_context->mm->context.id;\n 548\t\n 549\t\tif (npu_context->nmmu_flush)\n 550\t\t\t/*\n 551\t\t\t * Unfortunately the nest mmu does not support flushing specific\n 552\t\t\t * addresses so we have to flush the whole mm once before\n 553\t\t\t * shooting down the GPU translation.\n 554\t\t\t */\n > 555\t\t\tflush_all_mm(npu_context->mm);\n 556\t\n 557\t\t/*\n 558\t\t * Loop over all the NPUs this process is active on and launch\n 559\t\t * an invalidate.\n 560\t\t */\n 561\t\tfor (i = 0; i <= max_npu2_index; i++) {\n 562\t\t\tmmio_atsd_reg[i].reg = -1;\n 563\t\t\tfor (j = 0; j < NV_MAX_LINKS; j++) {\n 564\t\t\t\tnpdev = npu_context->npdev[i][j];\n 565\t\t\t\tif (!npdev)\n 566\t\t\t\t\tcontinue;\n 567\t\n 568\t\t\t\tnphb = pci_bus_to_host(npdev->bus)->private_data;\n 569\t\t\t\tnpu = &nphb->npu;\n 570\t\t\t\tmmio_atsd_reg[i].npu = npu;\n 571\t\n 572\t\t\t\tif (va)\n 573\t\t\t\t\tmmio_atsd_reg[i].reg =\n 574\t\t\t\t\t\tmmio_invalidate_va(npu, address, pid,\n 575\t\t\t\t\t\t\t\tflush);\n 576\t\t\t\telse\n 577\t\t\t\t\tmmio_atsd_reg[i].reg =\n 578\t\t\t\t\t\tmmio_invalidate_pid(npu, pid, flush);\n 579\t\n 580\t\t\t\t/*\n 581\t\t\t\t * The NPU hardware forwards the shootdown to all GPUs\n 582\t\t\t\t * so we only have to launch one shootdown per NPU.\n 583\t\t\t\t */\n 584\t\t\t\tbreak;\n 585\t\t\t}\n 586\t\t}\n 587\t\n 588\t\tmmio_invalidate_wait(mmio_atsd_reg, flush);\n 589\t\tif (flush)\n 590\t\t\t/* Wait for the flush to complete */\n 591\t\t\tmmio_invalidate_wait(mmio_atsd_reg, false);\n 592\t}\n 593\t\n 594\tstatic void pnv_npu2_mn_release(struct mmu_notifier *mn,\n 595\t\t\t\t\tstruct mm_struct *mm)\n 596\t{\n 597\t\tstruct npu_context *npu_context = mn_to_npu_context(mn);\n 598\t\n 599\t\t/* Call into device driver to stop requests to the NMMU */\n 600\t\tif (npu_context->release_cb)\n 601\t\t\tnpu_context->release_cb(npu_context, npu_context->priv);\n 602\t\n 603\t\t/*\n 604\t\t * There should be no more translation requests for this PID, but we\n 605\t\t * need to ensure any entries for it are removed from the TLB.\n 606\t\t */\n 607\t\tmmio_invalidate(npu_context, 0, 0, true);\n 608\t}\n 609\t\n 610\tstatic void pnv_npu2_mn_change_pte(struct mmu_notifier *mn,\n 611\t\t\t\t\tstruct mm_struct *mm,\n 612\t\t\t\t\tunsigned long address,\n 613\t\t\t\t\tpte_t pte)\n 614\t{\n 615\t\tstruct npu_context *npu_context = mn_to_npu_context(mn);\n 616\t\n 617\t\tmmio_invalidate(npu_context, 1, address, true);\n 618\t}\n 619\t\n 620\tstatic void pnv_npu2_mn_invalidate_page(struct mmu_notifier *mn,\n 621\t\t\t\t\t\tstruct mm_struct *mm,\n 622\t\t\t\t\t\tunsigned long address)\n 623\t{\n 624\t\tstruct npu_context *npu_context = mn_to_npu_context(mn);\n 625\t\n 626\t\tmmio_invalidate(npu_context, 1, address, true);\n 627\t}\n 628\t\n 629\tstatic void pnv_npu2_mn_invalidate_range(struct mmu_notifier *mn,\n 630\t\t\t\t\t\tstruct mm_struct *mm,\n 631\t\t\t\t\t\tunsigned long start, unsigned long end)\n 632\t{\n 633\t\tstruct npu_context *npu_context = mn_to_npu_context(mn);\n 634\t\tunsigned long address;\n 635\t\n 636\t\tfor (address = start; address < end; address += PAGE_SIZE)\n 637\t\t\tmmio_invalidate(npu_context, 1, address, false);\n 638\t\n 639\t\t/* Do the flush only on the final addess == end */\n 640\t\tmmio_invalidate(npu_context, 1, address, true);\n 641\t}\n 642\t\n 643\tstatic const struct mmu_notifier_ops nv_nmmu_notifier_ops = {\n 644\t\t.release = pnv_npu2_mn_release,\n 645\t\t.change_pte = pnv_npu2_mn_change_pte,\n 646\t\t.invalidate_page = pnv_npu2_mn_invalidate_page,\n 647\t\t.invalidate_range = pnv_npu2_mn_invalidate_range,\n 648\t};\n 649\t\n 650\t/*\n 651\t * Call into OPAL to setup the nmmu context for the current task in\n 652\t * the NPU. This must be called to setup the context tables before the\n 653\t * GPU issues ATRs. pdev should be a pointed to PCIe GPU device.\n 654\t *\n 655\t * A release callback should be registered to allow a device driver to\n 656\t * be notified that it should not launch any new translation requests\n 657\t * as the final TLB invalidate is about to occur.\n 658\t *\n 659\t * Returns an error if there no contexts are currently available or a\n 660\t * npu_context which should be passed to pnv_npu2_handle_fault().\n 661\t *\n 662\t * mmap_sem must be held in write mode.\n 663\t */\n 664\tstruct npu_context *pnv_npu2_init_context(struct pci_dev *gpdev,\n 665\t\t\t\tunsigned long flags,\n 666\t\t\t\tstruct npu_context *(*cb)(struct npu_context *, void *),\n 667\t\t\t\tvoid *priv)\n 668\t{\n 669\t\tint rc;\n 670\t\tu32 nvlink_index;\n 671\t\tstruct device_node *nvlink_dn;\n 672\t\tstruct mm_struct *mm = current->mm;\n 673\t\tstruct pnv_phb *nphb;\n 674\t\tstruct npu *npu;\n 675\t\tstruct npu_context *npu_context;\n 676\t\n 677\t\t/*\n 678\t\t * At present we don't support GPUs connected to multiple NPUs and I'm\n 679\t\t * not sure the hardware does either.\n 680\t\t */\n 681\t\tstruct pci_dev *npdev = pnv_pci_get_npu_dev(gpdev, 0);\n 682\t\n 683\t\tif (!firmware_has_feature(FW_FEATURE_OPAL))\n 684\t\t\treturn ERR_PTR(-ENODEV);\n 685\t\n 686\t\tif (!npdev)\n 687\t\t\t/* No nvlink associated with this GPU device */\n 688\t\t\treturn ERR_PTR(-ENODEV);\n 689\t\n 690\t\tif (!mm || mm->context.id == 0) {\n 691\t\t\t/*\n 692\t\t\t * Kernel thread contexts are not supported and context id 0 is\n 693\t\t\t * reserved on the GPU.\n 694\t\t\t */\n 695\t\t\treturn ERR_PTR(-EINVAL);\n 696\t\t}\n 697\t\n 698\t\tnphb = pci_bus_to_host(npdev->bus)->private_data;\n 699\t\tnpu = &nphb->npu;\n 700\t\n 701\t\t/*\n 702\t\t * Setup the NPU context table for a particular GPU. These need to be\n 703\t\t * per-GPU as we need the tables to filter ATSDs when there are no\n 704\t\t * active contexts on a particular GPU.\n 705\t\t */\n 706\t\trc = opal_npu_init_context(nphb->opal_id, mm->context.id, flags,\n 707\t\t\t\t\tPCI_DEVID(gpdev->bus->number, gpdev->devfn));\n 708\t\tif (rc < 0)\n 709\t\t\treturn ERR_PTR(-ENOSPC);\n 710\t\n 711\t\t/*\n 712\t\t * We store the npu pci device so we can more easily get at the\n 713\t\t * associated npus.\n 714\t\t */\n 715\t\tnpu_context = mm->context.npu_context;\n 716\t\tif (!npu_context) {\n 717\t\t\tnpu_context = kzalloc(sizeof(struct npu_context), GFP_KERNEL);\n 718\t\t\tif (!npu_context)\n 719\t\t\t\treturn ERR_PTR(-ENOMEM);\n 720\t\n 721\t\t\tmm->context.npu_context = npu_context;\n 722\t\t\tnpu_context->mm = mm;\n 723\t\t\tnpu_context->mn.ops = &nv_nmmu_notifier_ops;\n 724\t\t\t__mmu_notifier_register(&npu_context->mn, mm);\n 725\t\t\tkref_init(&npu_context->kref);\n 726\t\t} else {\n 727\t\t\tkref_get(&npu_context->kref);\n 728\t\t}\n 729\t\n 730\t\tnpu_context->release_cb = cb;\n 731\t\tnpu_context->priv = priv;\n 732\t\tnvlink_dn = of_parse_phandle(npdev->dev.of_node, \"ibm,nvlink\", 0);\n 733\t\tif (WARN_ON(of_property_read_u32(nvlink_dn, \"ibm,npu-link-index\",\n 734\t\t\t\t\t\t\t\t&nvlink_index)))\n 735\t\t\treturn ERR_PTR(-ENODEV);\n 736\t\tnpu_context->npdev[npu->index][nvlink_index] = npdev;\n 737\t\n 738\t\tif (!nphb->npu.nmmu_flush) {\n 739\t\t\t/*\n 740\t\t\t * If we're not explicitly flushing ourselves we need to mark\n 741\t\t\t * the thread for global flushes\n 742\t\t\t */\n 743\t\t\tnpu_context->nmmu_flush = false;\n > 744\t\t\tinc_mm_active_cpus(mm);\n 745\t\t} else\n 746\t\t\tnpu_context->nmmu_flush = true;\n 747\t\n 748\t\treturn npu_context;\n 749\t}\n 750\tEXPORT_SYMBOL(pnv_npu2_init_context);\n 751\t\n 752\tstatic void pnv_npu2_release_context(struct kref *kref)\n 753\t{\n 754\t\tstruct npu_context *npu_context =\n 755\t\t\tcontainer_of(kref, struct npu_context, kref);\n 756\t\n 757\t\tif (!npu_context->nmmu_flush)\n > 758\t\t\tdec_mm_active_cpus(npu_context->mm);\n 759\t\n 760\t\tnpu_context->mm->context.npu_context = NULL;\n 761\t\tmmu_notifier_unregister(&npu_context->mn,\n 762\t\t\t\t\tnpu_context->mm);\n 763\t\n 764\t\tkfree(npu_context);\n 765\t}\n 766\t\n\n---\n0-DAY kernel test infrastructure Open Source Technology Center\nhttps://lists.01.org/pipermail/kbuild-all Intel Corporation","headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xpPh80yPKz9s7p\n\tfor ;\n\tFri, 8 Sep 2017 14:38:00 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xpPh76Hj0zDrbK\n\tfor ;\n\tFri, 8 Sep 2017 14:37:59 +1000 (AEST)","from mga01.intel.com (mga01.intel.com [192.55.52.88])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xpPfc5YQQzDrYn\n\tfor ;\n\tFri, 8 Sep 2017 14:36:37 +1000 (AEST)","from fmsmga001.fm.intel.com ([10.253.24.23])\n\tby fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t07 Sep 2017 21:36:32 -0700","from bee.sh.intel.com (HELO bee) ([10.239.97.14])\n\tby fmsmga001.fm.intel.com with ESMTP; 07 Sep 2017 21:36:30 -0700","from kbuild by bee with local (Exim 4.84_2)\n\t(envelope-from )\n\tid 1dqB6i-000Wo3-CX; Fri, 08 Sep 2017 12:41:32 +0800"],"Authentication-Results":"ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=intel.com\n\t(client-ip=192.55.52.88; helo=mga01.intel.com;\n\tenvelope-from=fengguang.wu@intel.com; receiver=)","X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos;i=\"5.42,360,1500966000\"; \n\td=\"gz'50?scan'50,208,50\";a=\"1192856632\"","Date":"Fri, 8 Sep 2017 12:36:02 +0800","From":"kbuild test robot ","To":"Alistair Popple ","Subject":"Re: [PATCH 2/2] powerpc/powernv/npu: Don't explicitly flush nmmu tlb","Message-ID":"<201709081201.0KTtjfCD%fengguang.wu@intel.com>","MIME-Version":"1.0","Content-Type":"multipart/mixed; boundary=\"TB36FDmn/VVEgNH/\"","Content-Disposition":"inline","In-Reply-To":"<1504583864-8169-2-git-send-email-alistair@popple.id.au>","User-Agent":"Mutt/1.5.23 (2014-03-12)","X-SA-Exim-Connect-IP":"","X-SA-Exim-Mail-From":"fengguang.wu@intel.com","X-SA-Exim-Scanned":"No (on bee); SAEximRunCond expanded to false","X-BeenThere":"linuxppc-dev@lists.ozlabs.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"Linux on PowerPC Developers Mail List\n\t","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Alistair Popple , arbab@linux.vnet.ibm.com,\n\tfbarrat@linux.vnet.ibm.com, andrew.donnellan@au1.ibm.com,\n\tlinuxppc-dev@lists.ozlabs.org, kbuild-all@01.org","Errors-To":"linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org","Sender":"\"Linuxppc-dev\"\n\t"}}]