[{"id":1765714,"web_url":"http://patchwork.ozlabs.org/comment/1765714/","msgid":"","list_archive_url":null,"date":"2017-09-09T04:51:59","subject":"Re: [U-Boot] [PATCH v5 1/1] mmc: Add MMC support for stm32h7 Socs","submitter":{"id":6170,"url":"http://patchwork.ozlabs.org/api/people/6170/","name":"Simon Glass","email":"sjg@chromium.org"},"content":"On 4 September 2017 at 09:56, wrote:\n> From: Patrice Chotard \n>\n> This patch adds SD/MMC support for STM32H7 SoCs.\n>\n> Here is an extraction of SDMMC main features, embedded in\n> STM32H7 SoCs.\n> The SD/MMC block include the following:\n> _ Full compliance with MultiMediaCard System Specification\n> Version 4.51. Card support for three different databus modes:\n> 1-bit (default), 4-bit and 8-bit.\n> _ Full compatibility with previous versions of MultiMediaCards\n> (backward compatibility).\n> _ Full compliance with SD memory card specifications version 4.1.\n> (SDR104 SDMMC_CK speed limited to maximum allowed IO speed,\n> SPI mode and UHS-II mode not supported).\n> _ Full compliance with SDIO card specification version 4.0.\n> Card support for two different databus modes: 1-bit (default)\n> and 4-bit. (SDR104 SDMMC_CK speed limited to maximum allowed IO\n> speed, SPI mode and UHS-II mode not supported).\n> _ Data transfer up to 208 Mbyte/s for the 8 bit mode.\n> (depending maximum allowed IO speed).\n> _ Data and command output enable signals to control external\n> bidirectional drivers.\n>\n> The current version of the SDMMC supports only one SD/SDIO/MMC card\n> at any one time and a stack of MMC Version 4.51 or previous.\n>\n> Signed-off-by: Christophe Kerello \n> Signed-off-by: Patrice Chotard \n> ---\n>\n> v5: _ give a more meaningful name to stm32_sdmmc2_start_cmd() last param\n> _ use readl_poll_timeout() instead of using while in stm32_sdmmc2_end_cmd()\n> v4: _ replace mmc_create() usage by mmc_bind() callback\n> _ rename struct stm32_sdmmc2_host to stm32_sdmmc2_priv\n> v3: _ use registers offset instead of registers struct description\n> _ rename clk_reg_add and pwr_reg_add to respectively clk_reg_msk and pwr_reg_msk\n> _ don't exit in error if DT bus-width value is not correct, force it to 1\n> and continue\n> v2: _ add .get_cd() callback support\n>\n> drivers/mmc/Kconfig | 8 +\n> drivers/mmc/Makefile | 1 +\n> drivers/mmc/stm32_sdmmc2.c | 608 +++++++++++++++++++++++++++++++++++++++++++++\n> 3 files changed, 617 insertions(+)\n> create mode 100644 drivers/mmc/stm32_sdmmc2.c\n\nReviewed-by: Simon Glass ","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1777342,"web_url":"http://patchwork.ozlabs.org/comment/1777342/","msgid":"","list_archive_url":null,"date":"2017-09-29T02:30:38","subject":"Re: [U-Boot] [PATCH v5 1/1] mmc: Add MMC support for stm32h7 Socs","submitter":{"id":8006,"url":"http://patchwork.ozlabs.org/api/people/8006/","name":"Jaehoon Chung","email":"jh80.chung@samsung.com"},"content":"On 09/09/2017 01:51 PM, Simon Glass wrote:\n> On 4 September 2017 at 09:56, wrote:\n>> From: Patrice Chotard \n>>\n>> This patch adds SD/MMC support for STM32H7 SoCs.\n>>\n>> Here is an extraction of SDMMC main features, embedded in\n>> STM32H7 SoCs.\n>> The SD/MMC block include the following:\n>> _ Full compliance with MultiMediaCard System Specification\n>> Version 4.51. Card support for three different databus modes:\n>> 1-bit (default), 4-bit and 8-bit.\n>> _ Full compatibility with previous versions of MultiMediaCards\n>> (backward compatibility).\n>> _ Full compliance with SD memory card specifications version 4.1.\n>> (SDR104 SDMMC_CK speed limited to maximum allowed IO speed,\n>> SPI mode and UHS-II mode not supported).\n>> _ Full compliance with SDIO card specification version 4.0.\n>> Card support for two different databus modes: 1-bit (default)\n>> and 4-bit. (SDR104 SDMMC_CK speed limited to maximum allowed IO\n>> speed, SPI mode and UHS-II mode not supported).\n>> _ Data transfer up to 208 Mbyte/s for the 8 bit mode.\n>> (depending maximum allowed IO speed).\n>> _ Data and command output enable signals to control external\n>> bidirectional drivers.\n>>\n>> The current version of the SDMMC supports only one SD/SDIO/MMC card\n>> at any one time and a stack of MMC Version 4.51 or previous.\n>>\n>> Signed-off-by: Christophe Kerello \n>> Signed-off-by: Patrice Chotard \n>> ---\n>>\n>> v5: _ give a more meaningful name to stm32_sdmmc2_start_cmd() last param\n>> _ use readl_poll_timeout() instead of using while in stm32_sdmmc2_end_cmd()\n>> v4: _ replace mmc_create() usage by mmc_bind() callback\n>> _ rename struct stm32_sdmmc2_host to stm32_sdmmc2_priv\n>> v3: _ use registers offset instead of registers struct description\n>> _ rename clk_reg_add and pwr_reg_add to respectively clk_reg_msk and pwr_reg_msk\n>> _ don't exit in error if DT bus-width value is not correct, force it to 1\n>> and continue\n>> v2: _ add .get_cd() callback support\n>>\n>> drivers/mmc/Kconfig | 8 +\n>> drivers/mmc/Makefile | 1 +\n>> drivers/mmc/stm32_sdmmc2.c | 608 +++++++++++++++++++++++++++++++++++++++++++++\n>> 3 files changed, 617 insertions(+)\n>> create mode 100644 drivers/mmc/stm32_sdmmc2.c\n> \n> Reviewed-by: Simon Glass \n\nApplied to u-boot-mmc. Thanks!\n\nBest Regards,\nJaehoon Chung\n\n> \n> \n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y3Fsn6gT7z9t3R\n\tfor ;\n\tFri, 29 Sep 2017 12:30:53 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 76A22C21DA2; Fri, 29 Sep 2017 02:30:48 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 8DB12C21CB1;\n\tFri, 29 Sep 2017 02:30:45 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 51ED1C21CB1; Fri, 29 Sep 2017 02:30:44 +0000 (UTC)","from mailout3.samsung.com (mailout3.samsung.com [203.254.224.33])\n\tby lists.denx.de (Postfix) with ESMTPS id 6EBA9C21C57\n\tfor ; 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