[{"id":1763669,"web_url":"http://patchwork.ozlabs.org/comment/1763669/","msgid":"<20170905213152.GG17184@localhost.localdomain>","list_archive_url":null,"date":"2017-09-05T21:31:52","subject":"Re: [Qemu-devel] [PATCH 6/6] arm: drop intermadiate cpu_model ->\n\tcpu type parsing and use cpu type directly","submitter":{"id":195,"url":"http://patchwork.ozlabs.org/api/people/195/","name":"Eduardo Habkost","email":"ehabkost@redhat.com"},"content":"On Mon, Sep 04, 2017 at 04:01:02PM +0200, Igor Mammedov wrote:\n> there are 2 use cases to deal with:\n> 1: fixed CPU models per board/soc\n> 2: boards with user configurable cpu_model and fallback to\n> default cpu_model if user hasn't specified one explicitly\n> \n> For the 1st\n> drop intermediate cpu_model parsing and use const cpu type\n> directly, which replaces:\n> typename = object_class_get_name(\n> cpu_class_by_name(TYPE_ARM_CPU, cpu_model))\n> object_new(typename)\n> with\n> object_new(FOO_CPU_TYPE_NAME)\n> or\n> cpu_generic_init(BASE_CPU_TYPE, \"my cpu model\")\n> with\n> cpu_create(FOO_CPU_TYPE_NAME)\n> \n> as result 1st use case doesn't have to invoke not necessary\n> translation and not needed code is removed.\n> \n> For the 2nd\n> 1: set default cpu type with MachineClass::default_cpu_type and\n> 2: use generic cpu_model parsing that done before machine_init()\n> is run and:\n> 2.1: drop custom cpu_model parsing where pattern is:\n> typename = object_class_get_name(\n> cpu_class_by_name(TYPE_ARM_CPU, cpu_model))\n> [parse_features(typename, cpu_model, &err) ]\n> \n> 2.2: or replace cpu_generic_init() which does what\n> 2.1 does + create_cpu(typename) with just\n> create_cpu(machine->cpu_type)\n> as result cpu_name -> cpu_type translation is done using\n> generic machine code one including parsing optional features\n> if supported/present (removes a bunch of duplicated cpu_model\n> parsing code) and default cpu type is defined in an uniform way\n> within machine_class_init callbacks instead of adhoc places\n> in boadr's machine_init code.\n> \n> Signed-off-by: Igor Mammedov \n> ---\n> CC: Peter Maydell \n> CC: Igor Mitsyanko \n> CC: Rob Herring \n> CC: Andrzej Zaborowski \n> CC: Jan Kiszka \n> CC: Alistair Francis \n> CC: \"Edgar E. Iglesias\" \n> CC: qemu-arm@nongnu.org \n> ---\n> include/hw/arm/armv7m.h | 2 +-\n> include/hw/arm/aspeed_soc.h | 2 +-\n> include/hw/arm/stm32f205_soc.h | 2 +-\n> target/arm/cpu.h | 3 +++\n> hw/arm/armv7m.c | 40 +++++-------------------------------\n> hw/arm/aspeed_soc.c | 13 +++++-------\n> hw/arm/collie.c | 10 +++------\n> hw/arm/exynos4210.c | 6 +-----\n> hw/arm/gumstix.c | 5 +++--\n> hw/arm/highbank.c | 10 ++++-----\n> hw/arm/integratorcp.c | 30 ++-------------------------\n> hw/arm/mainstone.c | 9 ++++-----\n> hw/arm/mps2.c | 17 +++++++---------\n> hw/arm/musicpal.c | 7 ++-----\n> hw/arm/netduino2.c | 2 +-\n> hw/arm/nseries.c | 4 +++-\n> hw/arm/omap1.c | 7 ++-----\n> hw/arm/omap2.c | 4 ++--\n> hw/arm/omap_sx1.c | 5 ++++-\n> hw/arm/palm.c | 5 +++--\n> hw/arm/pxa2xx.c | 10 ++++-----\n> hw/arm/realview.c | 25 +++++------------------\n> hw/arm/spitz.c | 12 ++++++-----\n> hw/arm/stellaris.c | 16 +++++++--------\n> hw/arm/stm32f205_soc.c | 4 ++--\n> hw/arm/strongarm.c | 10 +++------\n> hw/arm/tosa.c | 4 ----\n> hw/arm/versatilepb.c | 15 +++-----------\n> hw/arm/vexpress.c | 32 +++++++++--------------------\n> hw/arm/virt.c | 46 +++++++++---------------------------------\n> hw/arm/xilinx_zynq.c | 10 ++-------\n> hw/arm/z2.c | 9 +++------\n> target/arm/cpu.c | 2 +-\n> 33 files changed, 114 insertions(+), 264 deletions(-)\n> \n> diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h\n> index a9b3f2a..8496743 100644\n> --- a/include/hw/arm/armv7m.h\n> +++ b/include/hw/arm/armv7m.h\n> @@ -55,7 +55,7 @@ typedef struct ARMv7MState {\n> MemoryRegion container;\n> \n> /* Properties */\n> - char *cpu_model;\n> + char *cpu_type;\n> /* MemoryRegion the board provides to us (with its devices, RAM, etc) */\n> MemoryRegion *board_memory;\n> } ARMv7MState;\n> diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h\n> index 0b88baa..f26914a 100644\n> --- a/include/hw/arm/aspeed_soc.h\n> +++ b/include/hw/arm/aspeed_soc.h\n> @@ -49,7 +49,7 @@ typedef struct AspeedSoCState {\n> \n> typedef struct AspeedSoCInfo {\n> const char *name;\n> - const char *cpu_model;\n> + const char *cpu_type;\n> uint32_t silicon_rev;\n> hwaddr sdram_base;\n> uint64_t sram_size;\n> diff --git a/include/hw/arm/stm32f205_soc.h b/include/hw/arm/stm32f205_soc.h\n> index e2dce11..922a733 100644\n> --- a/include/hw/arm/stm32f205_soc.h\n> +++ b/include/hw/arm/stm32f205_soc.h\n> @@ -52,7 +52,7 @@ typedef struct STM32F205State {\n> SysBusDevice parent_obj;\n> /*< public >*/\n> \n> - char *cpu_model;\n> + char *cpu_type;\n> \n> ARMv7MState armv7m;\n> \n> diff --git a/target/arm/cpu.h b/target/arm/cpu.h\n> index 5932ef1..3e1ba19 100644\n> --- a/target/arm/cpu.h\n> +++ b/target/arm/cpu.h\n> @@ -2002,6 +2002,9 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,\n> \n> #define cpu_init(cpu_model) cpu_generic_init(TYPE_ARM_CPU, cpu_model)\n> \n> +#define ARM_CPU_TYPE_SUFFIX \"-\" TYPE_ARM_CPU\n> +#define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX)\n> +\n> #define cpu_signal_handler cpu_arm_signal_handler\n> #define cpu_list arm_cpu_list\n> \n> diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c\n> index c8a11f2..9c45f26 100644\n> --- a/hw/arm/armv7m.c\n> +++ b/hw/arm/armv7m.c\n> @@ -163,10 +163,6 @@ static void armv7m_realize(DeviceState *dev, Error **errp)\n> SysBusDevice *sbd;\n> Error *err = NULL;\n> int i;\n> - char **cpustr;\n> - ObjectClass *oc;\n> - const char *typename;\n> - CPUClass *cc;\n> \n> if (!s->board_memory) {\n> error_setg(errp, \"memory property was not set\");\n> @@ -175,29 +171,7 @@ static void armv7m_realize(DeviceState *dev, Error **errp)\n> \n> memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1);\n> \n> - cpustr = g_strsplit(s->cpu_model, \",\", 2);\n> -\n> - oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]);\n> - if (!oc) {\n> - error_setg(errp, \"Unknown CPU model %s\", cpustr[0]);\n> - g_strfreev(cpustr);\n> - return;\n> - }\n> -\n> - cc = CPU_CLASS(oc);\n> - typename = object_class_get_name(oc);\n> - cc->parse_features(typename, cpustr[1], &err);\n> - g_strfreev(cpustr);\n> - if (err) {\n> - error_propagate(errp, err);\n> - return;\n> - }\n> -\n> - s->cpu = ARM_CPU(object_new(typename));\n> - if (!s->cpu) {\n> - error_setg(errp, \"Unknown CPU model %s\", s->cpu_model);\n> - return;\n> - }\n> + s->cpu = ARM_CPU(object_new(s->cpu_type));\n\nNice.\n\n> \n> object_property_set_link(OBJECT(s->cpu), OBJECT(&s->container), \"memory\",\n> &error_abort);\n> @@ -253,7 +227,7 @@ static void armv7m_realize(DeviceState *dev, Error **errp)\n> }\n> \n> static Property armv7m_properties[] = {\n> - DEFINE_PROP_STRING(\"cpu-model\", ARMv7MState, cpu_model),\n> + DEFINE_PROP_STRING(\"cpu-type\", ARMv7MState, cpu_type),\n\nAre we 100% sure the cpu-model property is never manually set by\nusers?\n\n\n> DEFINE_PROP_END_OF_LIST(),\n> };\n> \n> @@ -285,20 +259,16 @@ static void armv7m_reset(void *opaque)\n> Returns the ARMv7M device. */\n> \n> DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,\n> - const char *kernel_filename, const char *cpu_model)\n> + const char *kernel_filename, const char *cpu_type)\n> {\n> DeviceState *armv7m;\n> \n> - if (cpu_model == NULL) {\n> - cpu_model = \"cortex-m3\";\n> - }\n> -\n\nI was going to suggest doing the default_cpu_type stuff in a\nseparate patch, but it might require touching those lines twice.\nSo I guess this is OK.\n\n\n> armv7m = qdev_create(NULL, \"armv7m\");\n> qdev_prop_set_uint32(armv7m, \"num-irq\", num_irq);\n> - qdev_prop_set_string(armv7m, \"cpu-model\", cpu_model);\n> + qdev_prop_set_string(armv7m, \"cpu-type\", cpu_type);\n> object_property_set_link(OBJECT(armv7m), OBJECT(get_system_memory()),\n> \"memory\", &error_abort);\n> - /* This will exit with an error if the user passed us a bad cpu_model */\n> + /* This will exit with an error if the user passed us a bad cpu_type */\n> qdev_init_nofail(armv7m);\n> \n> armv7m_load_kernel(ARM_CPU(first_cpu), kernel_filename, mem_size);\n> diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c\n> index 5529024..cd7bb94 100644\n> --- a/hw/arm/aspeed_soc.c\n> +++ b/hw/arm/aspeed_soc.c\n> @@ -54,7 +54,7 @@ static const char *aspeed_soc_ast2500_typenames[] = {\n> static const AspeedSoCInfo aspeed_socs[] = {\n> {\n> .name = \"ast2400-a0\",\n> - .cpu_model = \"arm926\",\n> + .cpu_type = ARM_CPU_TYPE_NAME(\"arm926\"),\n> .silicon_rev = AST2400_A0_SILICON_REV,\n> .sdram_base = AST2400_SDRAM_BASE,\n> .sram_size = 0x8000,\n> @@ -65,7 +65,7 @@ static const AspeedSoCInfo aspeed_socs[] = {\n> .wdts_num = 2,\n> }, {\n> .name = \"ast2400-a1\",\n> - .cpu_model = \"arm926\",\n> + .cpu_type = ARM_CPU_TYPE_NAME(\"arm926\"),\n> .silicon_rev = AST2400_A1_SILICON_REV,\n> .sdram_base = AST2400_SDRAM_BASE,\n> .sram_size = 0x8000,\n> @@ -76,7 +76,7 @@ static const AspeedSoCInfo aspeed_socs[] = {\n> .wdts_num = 2,\n> }, {\n> .name = \"ast2400\",\n> - .cpu_model = \"arm926\",\n> + .cpu_type = ARM_CPU_TYPE_NAME(\"arm926\"),\n> .silicon_rev = AST2400_A0_SILICON_REV,\n> .sdram_base = AST2400_SDRAM_BASE,\n> .sram_size = 0x8000,\n> @@ -87,7 +87,7 @@ static const AspeedSoCInfo aspeed_socs[] = {\n> .wdts_num = 2,\n> }, {\n> .name = \"ast2500-a1\",\n> - .cpu_model = \"arm1176\",\n> + .cpu_type = ARM_CPU_TYPE_NAME(\"arm1176\"),\n> .silicon_rev = AST2500_A1_SILICON_REV,\n> .sdram_base = AST2500_SDRAM_BASE,\n> .sram_size = 0x9000,\n> @@ -128,13 +128,10 @@ static void aspeed_soc_init(Object *obj)\n> {\n> AspeedSoCState *s = ASPEED_SOC(obj);\n> AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);\n> - char *cpu_typename;\n> int i;\n> \n> - cpu_typename = g_strdup_printf(\"%s-\" TYPE_ARM_CPU, sc->info->cpu_model);\n> - object_initialize(&s->cpu, sizeof(s->cpu), cpu_typename);\n> + object_initialize(&s->cpu, sizeof(s->cpu), sc->info->cpu_type);\n> object_property_add_child(obj, \"cpu\", OBJECT(&s->cpu), NULL);\n> - g_free(cpu_typename);\n> \n\nNice.\n\n> object_initialize(&s->vic, sizeof(s->vic), TYPE_ASPEED_VIC);\n> object_property_add_child(obj, \"vic\", OBJECT(&s->vic), NULL);\n> diff --git a/hw/arm/collie.c b/hw/arm/collie.c\n> index 2e69531..f043cd8 100644\n> --- a/hw/arm/collie.c\n> +++ b/hw/arm/collie.c\n> @@ -18,7 +18,7 @@\n> #include \"hw/block/flash.h\"\n> #include \"sysemu/block-backend.h\"\n> #include \"exec/address-spaces.h\"\n> -#include \"qom/cpu.h\"\n> +#include \"cpu.h\"\n> \n> static struct arm_boot_info collie_binfo = {\n> .loader_start = SA_SDCS0,\n> @@ -27,7 +27,6 @@ static struct arm_boot_info collie_binfo = {\n> \n> static void collie_init(MachineState *machine)\n> {\n> - const char *cpu_model = machine->cpu_model;\n> const char *kernel_filename = machine->kernel_filename;\n> const char *kernel_cmdline = machine->kernel_cmdline;\n> const char *initrd_filename = machine->initrd_filename;\n> @@ -35,11 +34,7 @@ static void collie_init(MachineState *machine)\n> DriveInfo *dinfo;\n> MemoryRegion *sysmem = get_system_memory();\n> \n> - if (!cpu_model) {\n> - cpu_model = \"sa1110\";\n> - }\n> -\n> - s = sa1110_init(sysmem, collie_binfo.ram_size, cpu_model);\n> + s = sa1110_init(sysmem, collie_binfo.ram_size, machine->cpu_type);\n> \n> dinfo = drive_get(IF_PFLASH, 0, 0);\n> pflash_cfi01_register(SA_CS0, NULL, \"collie.fl1\", 0x02000000,\n> @@ -64,6 +59,7 @@ static void collie_machine_init(MachineClass *mc)\n> {\n> mc->desc = \"Sharp SL-5500 (Collie) PDA (SA-1110)\";\n> mc->init = collie_init;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"sa1110\");\n> }\n> \n> DEFINE_MACHINE(\"collie\", collie_machine_init)\n> diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c\n> index f9e79f3..81f12e3 100644\n> --- a/hw/arm/exynos4210.c\n> +++ b/hw/arm/exynos4210.c\n> @@ -169,15 +169,11 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem)\n> Exynos4210State *s = g_new(Exynos4210State, 1);\n> qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];\n> SysBusDevice *busdev;\n> - ObjectClass *cpu_oc;\n> DeviceState *dev;\n> int i, n;\n> \n> - cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, \"cortex-a9\");\n> - assert(cpu_oc);\n> -\n> for (n = 0; n < EXYNOS4210_NCPUS; n++) {\n> - Object *cpuobj = object_new(object_class_get_name(cpu_oc));\n> + Object *cpuobj = object_new(ARM_CPU_TYPE_NAME(\"cortex-a9\"));\n> \n> /* By default A9 CPUs have EL3 enabled. This board does not currently\n> * support EL3 so the CPU EL3 property is disabled before realization.\n> diff --git a/hw/arm/gumstix.c b/hw/arm/gumstix.c\n> index d59d9ba..2b66bb7 100644\n> --- a/hw/arm/gumstix.c\n> +++ b/hw/arm/gumstix.c\n> @@ -44,6 +44,7 @@\n> #include \"sysemu/block-backend.h\"\n> #include \"exec/address-spaces.h\"\n> #include \"sysemu/qtest.h\"\n> +#include \"cpu.h\"\n> \n> static const int sector_len = 128 * 1024;\n> \n> @@ -86,7 +87,6 @@ static void connex_init(MachineState *machine)\n> \n> static void verdex_init(MachineState *machine)\n> {\n> - const char *cpu_model = machine->cpu_model;\n> PXA2xxState *cpu;\n> DriveInfo *dinfo;\n> int be;\n> @@ -95,7 +95,7 @@ static void verdex_init(MachineState *machine)\n> uint32_t verdex_rom = 0x02000000;\n> uint32_t verdex_ram = 0x10000000;\n> \n> - cpu = pxa270_init(address_space_mem, verdex_ram, cpu_model ?: \"pxa270-c0\");\n> + cpu = pxa270_init(address_space_mem, verdex_ram, machine->cpu_type);\n> \n> dinfo = drive_get(IF_PFLASH, 0, 0);\n> if (!dinfo && !qtest_enabled()) {\n> @@ -142,6 +142,7 @@ static void verdex_class_init(ObjectClass *oc, void *data)\n> \n> mc->desc = \"Gumstix Verdex (PXA270)\";\n> mc->init = verdex_init;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"pxa270-c0\");\n> }\n> \n> static const TypeInfo verdex_type = {\n> diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c\n> index 20e60f1..0d7190a 100644\n> --- a/hw/arm/highbank.c\n> +++ b/hw/arm/highbank.c\n> @@ -219,7 +219,6 @@ enum cxmachines {\n> static void calxeda_init(MachineState *machine, enum cxmachines machine_id)\n> {\n> ram_addr_t ram_size = machine->ram_size;\n> - const char *cpu_model = machine->cpu_model;\n> const char *kernel_filename = machine->kernel_filename;\n> const char *kernel_cmdline = machine->kernel_cmdline;\n> const char *initrd_filename = machine->initrd_filename;\n> @@ -236,19 +235,20 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id)\n> \n> switch (machine_id) {\n> case CALXEDA_HIGHBANK:\n> - cpu_model = \"cortex-a9\";\n> + machine->cpu_type = ARM_CPU_TYPE_NAME(\"cortex-a9\");\n> break;\n> case CALXEDA_MIDWAY:\n> - cpu_model = \"cortex-a15\";\n> + machine->cpu_type = ARM_CPU_TYPE_NAME(\"cortex-a15\");\n> break;\n> + default:\n> + assert(0);\n> }\n\nWhy not delete this switch statement completely and set\ndefault_cpu_type at midway_class_init() and\nhighbank_class_init()?\n\n\n> \n> for (n = 0; n < smp_cpus; n++) {\n> - ObjectClass *oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);\n> Object *cpuobj;\n> ARMCPU *cpu;\n> \n> - cpuobj = object_new(object_class_get_name(oc));\n> + cpuobj = object_new(machine->cpu_type);\n> cpu = ARM_CPU(cpuobj);\n> \n> object_property_set_int(cpuobj, QEMU_PSCI_CONDUIT_SMC,\n> diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c\n> index d9530ed..44d247e 100644\n> --- a/hw/arm/integratorcp.c\n> +++ b/hw/arm/integratorcp.c\n> @@ -572,46 +572,19 @@ static struct arm_boot_info integrator_binfo = {\n> static void integratorcp_init(MachineState *machine)\n> {\n> ram_addr_t ram_size = machine->ram_size;\n> - const char *cpu_model = machine->cpu_model;\n> const char *kernel_filename = machine->kernel_filename;\n> const char *kernel_cmdline = machine->kernel_cmdline;\n> const char *initrd_filename = machine->initrd_filename;\n> - char **cpustr;\n> - ObjectClass *cpu_oc;\n> - CPUClass *cc;\n> Object *cpuobj;\n> ARMCPU *cpu;\n> - const char *typename;\n> MemoryRegion *address_space_mem = get_system_memory();\n> MemoryRegion *ram = g_new(MemoryRegion, 1);\n> MemoryRegion *ram_alias = g_new(MemoryRegion, 1);\n> qemu_irq pic[32];\n> DeviceState *dev, *sic, *icp;\n> int i;\n> - Error *err = NULL;\n> \n> - if (!cpu_model) {\n> - cpu_model = \"arm926\";\n> - }\n> -\n> - cpustr = g_strsplit(cpu_model, \",\", 2);\n> -\n> - cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]);\n> - if (!cpu_oc) {\n> - fprintf(stderr, \"Unable to find CPU definition\\n\");\n> - exit(1);\n> - }\n> - typename = object_class_get_name(cpu_oc);\n> -\n> - cc = CPU_CLASS(cpu_oc);\n> - cc->parse_features(typename, cpustr[1], &err);\n> - g_strfreev(cpustr);\n> - if (err) {\n> - error_report_err(err);\n> - exit(1);\n> - }\n> -\n> - cpuobj = object_new(typename);\n> + cpuobj = object_new(machine->cpu_type);\n\nNice.\n\n> \n> /* By default ARM1176 CPUs have EL3 enabled. This board does not\n> * currently support EL3 so the CPU EL3 property is disabled before\n> @@ -681,6 +654,7 @@ static void integratorcp_machine_init(MachineClass *mc)\n> {\n> mc->desc = \"ARM Integrator/CP (ARM926EJ-S)\";\n> mc->init = integratorcp_init;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"arm926\");\n> }\n> \n> DEFINE_MACHINE(\"integratorcp\", integratorcp_machine_init)\n> diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c\n> index fb268e6..2b13d30 100644\n> --- a/hw/arm/mainstone.c\n> +++ b/hw/arm/mainstone.c\n> @@ -24,6 +24,7 @@\n> #include \"hw/sysbus.h\"\n> #include \"exec/address-spaces.h\"\n> #include \"sysemu/qtest.h\"\n> +#include \"cpu.h\"\n> \n> /* Device addresses */\n> #define MST_FPGA_PHYS\t0x08000000\n> @@ -121,13 +122,10 @@ static void mainstone_common_init(MemoryRegion *address_space_mem,\n> int i;\n> int be;\n> MemoryRegion *rom = g_new(MemoryRegion, 1);\n> - const char *cpu_model = machine->cpu_model;\n> -\n> - if (!cpu_model)\n> - cpu_model = \"pxa270-c5\";\n> \n> /* Setup CPU & memory */\n> - mpu = pxa270_init(address_space_mem, mainstone_binfo.ram_size, cpu_model);\n> + mpu = pxa270_init(address_space_mem, mainstone_binfo.ram_size,\n> + machine->cpu_type);\n> memory_region_init_ram(rom, NULL, \"mainstone.rom\", MAINSTONE_ROM,\n> &error_fatal);\n> memory_region_set_readonly(rom, true);\n> @@ -196,6 +194,7 @@ static void mainstone2_machine_init(MachineClass *mc)\n> {\n> mc->desc = \"Mainstone II (PXA27x)\";\n> mc->init = mainstone_init;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"pxa270-c5\");\n> }\n> \n> DEFINE_MACHINE(\"mainstone\", mainstone2_machine_init)\n> diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c\n> index abb0ab6..aeaad80 100644\n> --- a/hw/arm/mps2.c\n> +++ b/hw/arm/mps2.c\n> @@ -46,7 +46,6 @@ typedef enum MPS2FPGAType {\n> typedef struct {\n> MachineClass parent;\n> MPS2FPGAType fpga_type;\n> - const char *cpu_model;\n> uint32_t scc_id;\n> } MPS2MachineClass;\n> \n> @@ -107,14 +106,12 @@ static void mps2_common_init(MachineState *machine)\n> MPS2MachineState *mms = MPS2_MACHINE(machine);\n> MPS2MachineClass *mmc = MPS2_MACHINE_GET_CLASS(machine);\n> MemoryRegion *system_memory = get_system_memory();\n> + MachineClass *mc = MACHINE_GET_CLASS(machine);\n> DeviceState *armv7m, *sccdev;\n> \n> - if (!machine->cpu_model) {\n> - machine->cpu_model = mmc->cpu_model;\n> - }\n> -\n> - if (strcmp(machine->cpu_model, mmc->cpu_model) != 0) {\n> - error_report(\"This board can only be used with CPU %s\", mmc->cpu_model);\n> + if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {\n> + error_report(\"This board can only be used with CPU %s\",\n> + mc->default_cpu_type);\n\nSuggestion for later: a generic mechanism to let the machine\nclass validate the CPU type this way. Maybe a\nMachineClass::configurable_cpu_type=false field?\n\n\n> exit(1);\n> }\n> \n> @@ -188,7 +185,7 @@ static void mps2_common_init(MachineState *machine)\n> default:\n> g_assert_not_reached();\n> }\n> - qdev_prop_set_string(armv7m, \"cpu-model\", machine->cpu_model);\n> + qdev_prop_set_string(armv7m, \"cpu-type\", machine->cpu_type);\n> object_property_set_link(OBJECT(&mms->armv7m), OBJECT(system_memory),\n> \"memory\", &error_abort);\n> object_property_set_bool(OBJECT(&mms->armv7m), true, \"realized\",\n> @@ -339,7 +336,7 @@ static void mps2_an385_class_init(ObjectClass *oc, void *data)\n> \n> mc->desc = \"ARM MPS2 with AN385 FPGA image for Cortex-M3\";\n> mmc->fpga_type = FPGA_AN385;\n> - mmc->cpu_model = \"cortex-m3\";\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"cortex-m3\");\n> mmc->scc_id = 0x41040000 | (385 << 4);\n> }\n> \n> @@ -350,7 +347,7 @@ static void mps2_an511_class_init(ObjectClass *oc, void *data)\n> \n> mc->desc = \"ARM MPS2 with AN511 DesignStart FPGA image for Cortex-M3\";\n> mmc->fpga_type = FPGA_AN511;\n> - mmc->cpu_model = \"cortex-m3\";\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"cortex-m3\");\n> mmc->scc_id = 0x4104000 | (511 << 4);\n> }\n> \n> diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c\n> index 64c8e09..9b2000d 100644\n> --- a/hw/arm/musicpal.c\n> +++ b/hw/arm/musicpal.c\n> @@ -1570,7 +1570,6 @@ static struct arm_boot_info musicpal_binfo = {\n> \n> static void musicpal_init(MachineState *machine)\n> {\n> - const char *cpu_model = machine->cpu_model;\n> const char *kernel_filename = machine->kernel_filename;\n> const char *kernel_cmdline = machine->kernel_cmdline;\n> const char *initrd_filename = machine->initrd_filename;\n> @@ -1590,10 +1589,7 @@ static void musicpal_init(MachineState *machine)\n> MemoryRegion *ram = g_new(MemoryRegion, 1);\n> MemoryRegion *sram = g_new(MemoryRegion, 1);\n> \n> - if (!cpu_model) {\n> - cpu_model = \"arm926\";\n> - }\n> - cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model));\n> + cpu = ARM_CPU(cpu_create(machine->cpu_type));\n> \n> /* For now we use a fixed - the original - RAM size */\n> memory_region_allocate_system_memory(ram, NULL, \"musicpal.ram\",\n> @@ -1714,6 +1710,7 @@ static void musicpal_machine_init(MachineClass *mc)\n> {\n> mc->desc = \"Marvell 88w8618 / MusicPal (ARM926EJ-S)\";\n> mc->init = musicpal_init;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"arm926\");\n> }\n> \n> DEFINE_MACHINE(\"musicpal\", musicpal_machine_init)\n> diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c\n> index 3cfe332..4790824 100644\n> --- a/hw/arm/netduino2.c\n> +++ b/hw/arm/netduino2.c\n> @@ -34,7 +34,7 @@ static void netduino2_init(MachineState *machine)\n> DeviceState *dev;\n> \n> dev = qdev_create(NULL, TYPE_STM32F205_SOC);\n> - qdev_prop_set_string(dev, \"cpu-model\", \"cortex-m3\");\n> + qdev_prop_set_string(dev, \"cpu-type\", ARM_CPU_TYPE_NAME(\"cortex-m3\"));\n> object_property_set_bool(OBJECT(dev), true, \"realized\", &error_fatal);\n> \n> armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,\n> diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c\n> index 503a3b6..b41850e 100644\n> --- a/hw/arm/nseries.c\n> +++ b/hw/arm/nseries.c\n> @@ -1310,7 +1310,7 @@ static void n8x0_init(MachineState *machine,\n> struct n800_s *s = (struct n800_s *) g_malloc0(sizeof(*s));\n> int sdram_size = binfo->ram_size;\n> \n> - s->mpu = omap2420_mpu_init(sysmem, sdram_size, machine->cpu_model);\n> + s->mpu = omap2420_mpu_init(sysmem, sdram_size, machine->cpu_type);\n> \n> /* Setup peripherals\n> *\n> @@ -1425,6 +1425,7 @@ static void n800_class_init(ObjectClass *oc, void *data)\n> mc->desc = \"Nokia N800 tablet aka. RX-34 (OMAP2420)\";\n> mc->init = n800_init;\n> mc->default_boot_order = \"\";\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"arm1136-r2\");\n> }\n> \n> static const TypeInfo n800_type = {\n> @@ -1440,6 +1441,7 @@ static void n810_class_init(ObjectClass *oc, void *data)\n> mc->desc = \"Nokia N810 tablet aka. RX-44 (OMAP2420)\";\n> mc->init = n810_init;\n> mc->default_boot_order = \"\";\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"arm1136-r2\");\n> }\n> \n> static const TypeInfo n810_type = {\n> diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c\n> index 04e65ce..b3e7625 100644\n> --- a/hw/arm/omap1.c\n> +++ b/hw/arm/omap1.c\n> @@ -3850,7 +3850,7 @@ static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s,\n> \n> struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,\n> unsigned long sdram_size,\n> - const char *core)\n> + const char *cpu_type)\n> {\n> int i;\n> struct omap_mpu_state_s *s = g_new0(struct omap_mpu_state_s, 1);\n> @@ -3858,12 +3858,9 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,\n> DriveInfo *dinfo;\n> SysBusDevice *busdev;\n> \n> - if (!core)\n> - core = \"ti925t\";\n> -\n> /* Core */\n> s->mpu_model = omap310;\n> - s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, core));\n> + s->cpu = ARM_CPU(cpu_create(cpu_type));\n> s->sdram_size = sdram_size;\n> s->sram_size = OMAP15XX_SRAM_SIZE;\n> \n> diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c\n> index 5821477..3f6076e 100644\n> --- a/hw/arm/omap2.c\n> +++ b/hw/arm/omap2.c\n> @@ -2250,7 +2250,7 @@ static const struct dma_irq_map omap2_dma_irq_map[] = {\n> \n> struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,\n> unsigned long sdram_size,\n> - const char *core)\n> + const char *cpu_type)\n> {\n> struct omap_mpu_state_s *s = g_new0(struct omap_mpu_state_s, 1);\n> qemu_irq dma_irqs[4];\n> @@ -2261,7 +2261,7 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,\n> \n> /* Core */\n> s->mpu_model = omap2420;\n> - s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, core ?: \"arm1136-r2\"));\n> + s->cpu = ARM_CPU(cpu_create(cpu_type));\n> s->sdram_size = sdram_size;\n> s->sram_size = OMAP242X_SRAM_SIZE;\n> \n> diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c\n> index 9809106..1236ec1 100644\n> --- a/hw/arm/omap_sx1.c\n> +++ b/hw/arm/omap_sx1.c\n> @@ -36,6 +36,7 @@\n> #include \"sysemu/block-backend.h\"\n> #include \"sysemu/qtest.h\"\n> #include \"exec/address-spaces.h\"\n> +#include \"cpu.h\"\n> \n> /*****************************************************************************/\n> /* Siemens SX1 Cellphone V1 */\n> @@ -120,7 +121,7 @@ static void sx1_init(MachineState *machine, const int version)\n> }\n> \n> mpu = omap310_mpu_init(address_space, sx1_binfo.ram_size,\n> - machine->cpu_model);\n> + machine->cpu_type);\n> \n> /* External Flash (EMIFS) */\n> memory_region_init_ram(flash, NULL, \"omap_sx1.flash0-0\", flash_size,\n> @@ -223,6 +224,7 @@ static void sx1_machine_v2_class_init(ObjectClass *oc, void *data)\n> \n> mc->desc = \"Siemens SX1 (OMAP310) V2\";\n> mc->init = sx1_init_v2;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"ti925t\");\n> }\n> \n> static const TypeInfo sx1_machine_v2_type = {\n> @@ -237,6 +239,7 @@ static void sx1_machine_v1_class_init(ObjectClass *oc, void *data)\n> \n> mc->desc = \"Siemens SX1 (OMAP310) V1\";\n> mc->init = sx1_init_v1;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"ti925t\");\n> }\n> \n> static const TypeInfo sx1_machine_v1_type = {\n> diff --git a/hw/arm/palm.c b/hw/arm/palm.c\n> index 64cf8ca..862f048 100644\n> --- a/hw/arm/palm.c\n> +++ b/hw/arm/palm.c\n> @@ -29,6 +29,7 @@\n> #include \"hw/devices.h\"\n> #include \"hw/loader.h\"\n> #include \"exec/address-spaces.h\"\n> +#include \"cpu.h\"\n> \n> static uint32_t static_readb(void *opaque, hwaddr offset)\n> {\n> @@ -195,7 +196,6 @@ static struct arm_boot_info palmte_binfo = {\n> \n> static void palmte_init(MachineState *machine)\n> {\n> - const char *cpu_model = machine->cpu_model;\n> const char *kernel_filename = machine->kernel_filename;\n> const char *kernel_cmdline = machine->kernel_cmdline;\n> const char *initrd_filename = machine->initrd_filename;\n> @@ -211,7 +211,7 @@ static void palmte_init(MachineState *machine)\n> MemoryRegion *flash = g_new(MemoryRegion, 1);\n> MemoryRegion *cs = g_new(MemoryRegion, 4);\n> \n> - mpu = omap310_mpu_init(address_space_mem, sdram_size, cpu_model);\n> + mpu = omap310_mpu_init(address_space_mem, sdram_size, machine->cpu_type);\n> \n> /* External Flash (EMIFS) */\n> memory_region_init_ram(flash, NULL, \"palmte.flash\", flash_size,\n> @@ -274,6 +274,7 @@ static void palmte_machine_init(MachineClass *mc)\n> {\n> mc->desc = \"Palm Tungsten|E aka. Cheetah PDA (OMAP310)\";\n> mc->init = palmte_init;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"ti925t\");\n> }\n> \n> DEFINE_MACHINE(\"cheetah\", palmte_machine_init)\n> diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c\n> index c16657d..79b317a 100644\n> --- a/hw/arm/pxa2xx.c\n> +++ b/hw/arm/pxa2xx.c\n> @@ -2052,21 +2052,19 @@ static void pxa2xx_reset(void *opaque, int line, int level)\n> \n> /* Initialise a PXA270 integrated chip (ARM based core). */\n> PXA2xxState *pxa270_init(MemoryRegion *address_space,\n> - unsigned int sdram_size, const char *revision)\n> + unsigned int sdram_size, const char *cpu_type)\n> {\n> PXA2xxState *s;\n> int i;\n> DriveInfo *dinfo;\n> s = g_new0(PXA2xxState, 1);\n> \n> - if (revision && strncmp(revision, \"pxa27\", 5)) {\n> + if (strncmp(cpu_type, ARM_CPU_TYPE_NAME(\"pxa27\"), 5)) {\n\nWhy are you using ARM_CPU_TYPE_NAME here, if you are only\nchecking if cpu_type starts with \"pxa27\"?\n\nI suggest adding a TODO here noting that we implement this using\neither a TYPE_ARM_PXA27 subclass (so we can use\nobject_class_dynamic_cast()), or a ARMCPUClass field to identify\nif the CPU is pxa27.\n\n> fprintf(stderr, \"Machine requires a PXA27x processor.\\n\");\n> exit(1);\n> }\n\nThis would be another use case for a generic CPU model validation\nmechanism in MachineClass.\n\n\n> - if (!revision)\n> - revision = \"pxa270\";\n> \n> - s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, revision));\n> + s->cpu = ARM_CPU(cpu_create(cpu_type));\n> s->reset = qemu_allocate_irq(pxa2xx_reset, s, 0);\n> \n> /* SDRAM & Internal Memory Storage */\n> @@ -2192,7 +2190,7 @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)\n> \n> s = g_new0(PXA2xxState, 1);\n> \n> - s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, \"pxa255\"));\n> + s->cpu = ARM_CPU(cpu_create(ARM_CPU_TYPE_NAME(\"pxa255\")));\n> s->reset = qemu_allocate_irq(pxa2xx_reset, s, 0);\n> \n> /* SDRAM & Internal Memory Storage */\n> diff --git a/hw/arm/realview.c b/hw/arm/realview.c\n> index 76ff557..38e3278 100644\n> --- a/hw/arm/realview.c\n> +++ b/hw/arm/realview.c\n> @@ -55,7 +55,6 @@ static void realview_init(MachineState *machine,\n> {\n> ARMCPU *cpu = NULL;\n> CPUARMState *env;\n> - ObjectClass *cpu_oc;\n> MemoryRegion *sysmem = get_system_memory();\n> MemoryRegion *ram_lo;\n> MemoryRegion *ram_hi = g_new(MemoryRegion, 1);\n> @@ -96,14 +95,8 @@ static void realview_init(MachineState *machine,\n> break;\n> }\n> \n> - cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, machine->cpu_model);\n> - if (!cpu_oc) {\n> - fprintf(stderr, \"Unable to find CPU definition\\n\");\n> - exit(1);\n> - }\n> -\n> for (n = 0; n < smp_cpus; n++) {\n> - Object *cpuobj = object_new(object_class_get_name(cpu_oc));\n> + Object *cpuobj = object_new(machine->cpu_type);\n> \n> /* By default A9,A15 and ARM1176 CPUs have EL3 enabled. This board\n> * does not currently support EL3 so the CPU EL3 property is disabled\n> @@ -359,33 +352,21 @@ static void realview_init(MachineState *machine,\n> \n> static void realview_eb_init(MachineState *machine)\n> {\n> - if (!machine->cpu_model) {\n> - machine->cpu_model = \"arm926\";\n> - }\n> realview_init(machine, BOARD_EB);\n> }\n> \n> static void realview_eb_mpcore_init(MachineState *machine)\n> {\n> - if (!machine->cpu_model) {\n> - machine->cpu_model = \"arm11mpcore\";\n> - }\n> realview_init(machine, BOARD_EB_MPCORE);\n> }\n> \n> static void realview_pb_a8_init(MachineState *machine)\n> {\n> - if (!machine->cpu_model) {\n> - machine->cpu_model = \"cortex-a8\";\n> - }\n> realview_init(machine, BOARD_PB_A8);\n> }\n> \n> static void realview_pbx_a9_init(MachineState *machine)\n> {\n> - if (!machine->cpu_model) {\n> - machine->cpu_model = \"cortex-a9\";\n> - }\n> realview_init(machine, BOARD_PBX_A9);\n> }\n> \n> @@ -396,6 +377,7 @@ static void realview_eb_class_init(ObjectClass *oc, void *data)\n> mc->desc = \"ARM RealView Emulation Baseboard (ARM926EJ-S)\";\n> mc->init = realview_eb_init;\n> mc->block_default_type = IF_SCSI;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"arm926\");\n> }\n> \n> static const TypeInfo realview_eb_type = {\n> @@ -412,6 +394,7 @@ static void realview_eb_mpcore_class_init(ObjectClass *oc, void *data)\n> mc->init = realview_eb_mpcore_init;\n> mc->block_default_type = IF_SCSI;\n> mc->max_cpus = 4;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"arm11mpcore\");\n> }\n> \n> static const TypeInfo realview_eb_mpcore_type = {\n> @@ -426,6 +409,7 @@ static void realview_pb_a8_class_init(ObjectClass *oc, void *data)\n> \n> mc->desc = \"ARM RealView Platform Baseboard for Cortex-A8\";\n> mc->init = realview_pb_a8_init;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"cortex-a8\");\n> }\n> \n> static const TypeInfo realview_pb_a8_type = {\n> @@ -441,6 +425,7 @@ static void realview_pbx_a9_class_init(ObjectClass *oc, void *data)\n> mc->desc = \"ARM RealView Platform Baseboard Explore for Cortex-A9\";\n> mc->init = realview_pbx_a9_init;\n> mc->max_cpus = 4;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"cortex-a9\");\n> }\n> \n> static const TypeInfo realview_pbx_a9_type = {\n> diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c\n> index 7f588ce..b6ddb7c 100644\n> --- a/hw/arm/spitz.c\n> +++ b/hw/arm/spitz.c\n> @@ -30,6 +30,7 @@\n> #include \"hw/sysbus.h\"\n> #include \"exec/address-spaces.h\"\n> #include \"sysemu/sysemu.h\"\n> +#include \"cpu.h\"\n> \n> #undef REG_FMT\n> #define REG_FMT\t\t\t\"0x%02lx\"\n> @@ -909,13 +910,10 @@ static void spitz_common_init(MachineState *machine,\n> DeviceState *scp0, *scp1 = NULL;\n> MemoryRegion *address_space_mem = get_system_memory();\n> MemoryRegion *rom = g_new(MemoryRegion, 1);\n> - const char *cpu_model = machine->cpu_model;\n> -\n> - if (!cpu_model)\n> - cpu_model = (model == terrier) ? \"pxa270-c5\" : \"pxa270-c0\";\n> \n\nNice to see this go away.\n\n\n> /* Setup CPU & memory */\n> - mpu = pxa270_init(address_space_mem, spitz_binfo.ram_size, cpu_model);\n> + mpu = pxa270_init(address_space_mem, spitz_binfo.ram_size,\n> + machine->cpu_type);\n> \n> sl_flash_register(mpu, (model == spitz) ? FLASH_128M : FLASH_1024M);\n> \n> @@ -983,6 +981,7 @@ static void akitapda_class_init(ObjectClass *oc, void *data)\n> \n> mc->desc = \"Sharp SL-C1000 (Akita) PDA (PXA270)\";\n> mc->init = akita_init;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"pxa270-c0\");\n> }\n> \n> static const TypeInfo akitapda_type = {\n> @@ -998,6 +997,7 @@ static void spitzpda_class_init(ObjectClass *oc, void *data)\n> mc->desc = \"Sharp SL-C3000 (Spitz) PDA (PXA270)\";\n> mc->init = spitz_init;\n> mc->block_default_type = IF_IDE;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"pxa270-c0\");\n> }\n> \n> static const TypeInfo spitzpda_type = {\n> @@ -1013,6 +1013,7 @@ static void borzoipda_class_init(ObjectClass *oc, void *data)\n> mc->desc = \"Sharp SL-C3100 (Borzoi) PDA (PXA270)\";\n> mc->init = borzoi_init;\n> mc->block_default_type = IF_IDE;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"pxa270-c0\");\n> }\n> \n> static const TypeInfo borzoipda_type = {\n> @@ -1028,6 +1029,7 @@ static void terrierpda_class_init(ObjectClass *oc, void *data)\n> mc->desc = \"Sharp SL-C3200 (Terrier) PDA (PXA270)\";\n> mc->init = terrier_init;\n> mc->block_default_type = IF_IDE;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"pxa270-c5\");\n> }\n> \n> static const TypeInfo terrierpda_type = {\n> diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c\n> index 408c1a1..c8fa9da 100644\n> --- a/hw/arm/stellaris.c\n> +++ b/hw/arm/stellaris.c\n> @@ -22,6 +22,7 @@\n> #include \"sysemu/sysemu.h\"\n> #include \"hw/char/pl011.h\"\n> #include \"hw/misc/unimp.h\"\n> +#include \"cpu.h\"\n> \n> #define GPIO_A 0\n> #define GPIO_B 1\n> @@ -1225,8 +1226,7 @@ static stellaris_board_info stellaris_boards[] = {\n> }\n> };\n> \n> -static void stellaris_init(const char *kernel_filename, const char *cpu_model,\n> - stellaris_board_info *board)\n> +static void stellaris_init(MachineState *ms, stellaris_board_info *board)\n> {\n> static const int uart_irq[] = {5, 6, 33, 34};\n> static const int timer_irq[] = {19, 21, 23, 35};\n> @@ -1298,7 +1298,7 @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model,\n> memory_region_add_subregion(system_memory, 0x20000000, sram);\n> \n> nvic = armv7m_init(system_memory, flash_size, NUM_IRQ_LINES,\n> - kernel_filename, cpu_model);\n> + ms->kernel_filename, ms->cpu_type);\n> \n> qdev_connect_gpio_out_named(nvic, \"SYSRESETREQ\", 0,\n> qemu_allocate_irq(&do_sys_reset, NULL, 0));\n> @@ -1435,16 +1435,12 @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model,\n> /* FIXME: Figure out how to generate these from stellaris_boards. */\n> static void lm3s811evb_init(MachineState *machine)\n> {\n> - const char *cpu_model = machine->cpu_model;\n> - const char *kernel_filename = machine->kernel_filename;\n> - stellaris_init(kernel_filename, cpu_model, &stellaris_boards[0]);\n> + stellaris_init(machine, &stellaris_boards[0]);\n> }\n> \n> static void lm3s6965evb_init(MachineState *machine)\n> {\n> - const char *cpu_model = machine->cpu_model;\n> - const char *kernel_filename = machine->kernel_filename;\n> - stellaris_init(kernel_filename, cpu_model, &stellaris_boards[1]);\n> + stellaris_init(machine, &stellaris_boards[1]);\n> }\n> \n> static void lm3s811evb_class_init(ObjectClass *oc, void *data)\n> @@ -1453,6 +1449,7 @@ static void lm3s811evb_class_init(ObjectClass *oc, void *data)\n> \n> mc->desc = \"Stellaris LM3S811EVB\";\n> mc->init = lm3s811evb_init;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"cortex-m3\");\n> }\n> \n> static const TypeInfo lm3s811evb_type = {\n> @@ -1467,6 +1464,7 @@ static void lm3s6965evb_class_init(ObjectClass *oc, void *data)\n> \n> mc->desc = \"Stellaris LM3S6965EVB\";\n> mc->init = lm3s6965evb_init;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"cortex-m3\");\n> }\n> \n> static const TypeInfo lm3s6965evb_type = {\n> diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c\n> index f61e735..1cd6374 100644\n> --- a/hw/arm/stm32f205_soc.c\n> +++ b/hw/arm/stm32f205_soc.c\n> @@ -112,7 +112,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)\n> \n> armv7m = DEVICE(&s->armv7m);\n> qdev_prop_set_uint32(armv7m, \"num-irq\", 96);\n> - qdev_prop_set_string(armv7m, \"cpu-model\", s->cpu_model);\n> + qdev_prop_set_string(armv7m, \"cpu-type\", s->cpu_type);\n> object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),\n> \"memory\", &error_abort);\n> object_property_set_bool(OBJECT(&s->armv7m), true, \"realized\", &err);\n> @@ -200,7 +200,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)\n> }\n> \n> static Property stm32f205_soc_properties[] = {\n> - DEFINE_PROP_STRING(\"cpu-model\", STM32F205State, cpu_model),\n> + DEFINE_PROP_STRING(\"cpu-type\", STM32F205State, cpu_type),\n\nSame as armv7m: are we 100% sure users are not setting this\nmanually?\n\n\n> DEFINE_PROP_END_OF_LIST(),\n> };\n> \n> diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c\n> index c1145dd..3d1a231 100644\n> --- a/hw/arm/strongarm.c\n> +++ b/hw/arm/strongarm.c\n> @@ -1581,23 +1581,19 @@ static const TypeInfo strongarm_ssp_info = {\n> \n> /* Main CPU functions */\n> StrongARMState *sa1110_init(MemoryRegion *sysmem,\n> - unsigned int sdram_size, const char *rev)\n> + unsigned int sdram_size, const char *cpu_type)\n> {\n> StrongARMState *s;\n> int i;\n> \n> s = g_new0(StrongARMState, 1);\n> \n> - if (!rev) {\n> - rev = \"sa1110-b5\";\n> - }\n> -\n> - if (strncmp(rev, \"sa1110\", 6)) {\n> + if (strncmp(cpu_type, \"sa1110\", 6)) {\n> error_report(\"Machine requires a SA1110 processor.\");\n> exit(1);\n\nSame suggestion as on pxa270_init(): adding a TODO here noting\nthat we implement this using either object_class_dynamic_cast(),\nor a ARMCPUClass field to identify if the CPU is sa1110.\n\n\n\n> }\n> \n> - s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, rev));\n> + s->cpu = ARM_CPU(cpu_create(cpu_type));\n> \n> memory_region_allocate_system_memory(&s->sdram, NULL, \"strongarm.sdram\",\n> sdram_size);\n> diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c\n> index 8b757ff..75631f6 100644\n> --- a/hw/arm/tosa.c\n> +++ b/hw/arm/tosa.c\n> @@ -219,7 +219,6 @@ static struct arm_boot_info tosa_binfo = {\n> \n> static void tosa_init(MachineState *machine)\n> {\n> - const char *cpu_model = machine->cpu_model;\n> const char *kernel_filename = machine->kernel_filename;\n> const char *kernel_cmdline = machine->kernel_cmdline;\n> const char *initrd_filename = machine->initrd_filename;\n> @@ -229,9 +228,6 @@ static void tosa_init(MachineState *machine)\n> TC6393xbState *tmio;\n> DeviceState *scp0, *scp1;\n> \n> - if (!cpu_model)\n> - cpu_model = \"pxa255\";\n> -\n\nDon't we need to set mc->default_cpu_type at\ntosapda_machine_init() to replace this?\n\n\n> mpu = pxa255_init(address_space_mem, tosa_binfo.ram_size);\n> \n> memory_region_init_ram(rom, NULL, \"tosa.rom\", TOSA_ROM, &error_fatal);\n> diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c\n> index b0e9f5b..ffda0ba 100644\n> --- a/hw/arm/versatilepb.c\n> +++ b/hw/arm/versatilepb.c\n> @@ -181,7 +181,6 @@ static struct arm_boot_info versatile_binfo;\n> \n> static void versatile_init(MachineState *machine, int board_id)\n> {\n> - ObjectClass *cpu_oc;\n> Object *cpuobj;\n> ARMCPU *cpu;\n> MemoryRegion *sysmem = get_system_memory();\n> @@ -207,17 +206,7 @@ static void versatile_init(MachineState *machine, int board_id)\n> exit(1);\n> }\n> \n> - if (!machine->cpu_model) {\n> - machine->cpu_model = \"arm926\";\n> - }\n> -\n> - cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, machine->cpu_model);\n> - if (!cpu_oc) {\n> - fprintf(stderr, \"Unable to find CPU definition\\n\");\n> - exit(1);\n> - }\n> -\n> - cpuobj = object_new(object_class_get_name(cpu_oc));\n> + cpuobj = object_new(machine->cpu_type);\n> \n> /* By default ARM1176 CPUs have EL3 enabled. This board does not\n> * currently support EL3 so the CPU EL3 property is disabled before\n> @@ -403,6 +392,7 @@ static void versatilepb_class_init(ObjectClass *oc, void *data)\n> mc->desc = \"ARM Versatile/PB (ARM926EJ-S)\";\n> mc->init = vpb_init;\n> mc->block_default_type = IF_SCSI;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"arm926\");\n> }\n> \n> static const TypeInfo versatilepb_type = {\n> @@ -418,6 +408,7 @@ static void versatileab_class_init(ObjectClass *oc, void *data)\n> mc->desc = \"ARM Versatile/AB (ARM926EJ-S)\";\n> mc->init = vab_init;\n> mc->block_default_type = IF_SCSI;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"arm926\");\n> }\n> \n> static const TypeInfo versatileab_type = {\n> diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c\n> index 528c65d..4fdeda2 100644\n> --- a/hw/arm/vexpress.c\n> +++ b/hw/arm/vexpress.c\n> @@ -184,7 +184,7 @@ typedef struct {\n> \n> typedef void DBoardInitFn(const VexpressMachineState *machine,\n> ram_addr_t ram_size,\n> - const char *cpu_model,\n> + const char *cpu_type,\n> qemu_irq *pic);\n> \n> struct VEDBoardInfo {\n> @@ -200,22 +200,16 @@ struct VEDBoardInfo {\n> DBoardInitFn *init;\n> };\n> \n> -static void init_cpus(const char *cpu_model, const char *privdev,\n> +static void init_cpus(const char *cpu_type, const char *privdev,\n> hwaddr periphbase, qemu_irq *pic, bool secure)\n> {\n> - ObjectClass *cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);\n> DeviceState *dev;\n> SysBusDevice *busdev;\n> int n;\n> \n> - if (!cpu_oc) {\n> - fprintf(stderr, \"Unable to find CPU definition\\n\");\n> - exit(1);\n> - }\n> -\n> /* Create the actual CPUs */\n> for (n = 0; n < smp_cpus; n++) {\n> - Object *cpuobj = object_new(object_class_get_name(cpu_oc));\n> + Object *cpuobj = object_new(cpu_type);\n> \n> if (!secure) {\n> object_property_set_bool(cpuobj, false, \"has_el3\", NULL);\n> @@ -260,7 +254,7 @@ static void init_cpus(const char *cpu_model, const char *privdev,\n> \n> static void a9_daughterboard_init(const VexpressMachineState *vms,\n> ram_addr_t ram_size,\n> - const char *cpu_model,\n> + const char *cpu_type,\n> qemu_irq *pic)\n> {\n> MemoryRegion *sysmem = get_system_memory();\n> @@ -268,10 +262,6 @@ static void a9_daughterboard_init(const VexpressMachineState *vms,\n> MemoryRegion *lowram = g_new(MemoryRegion, 1);\n> ram_addr_t low_ram_size;\n> \n> - if (!cpu_model) {\n> - cpu_model = \"cortex-a9\";\n> - }\n> -\n> if (ram_size > 0x40000000) {\n> /* 1GB is the maximum the address space permits */\n> fprintf(stderr, \"vexpress-a9: cannot model more than 1GB RAM\\n\");\n> @@ -293,7 +283,7 @@ static void a9_daughterboard_init(const VexpressMachineState *vms,\n> memory_region_add_subregion(sysmem, 0x60000000, ram);\n> \n> /* 0x1e000000 A9MPCore (SCU) private memory region */\n> - init_cpus(cpu_model, \"a9mpcore_priv\", 0x1e000000, pic, vms->secure);\n> + init_cpus(cpu_type, \"a9mpcore_priv\", 0x1e000000, pic, vms->secure);\n> \n> /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */\n> \n> @@ -349,17 +339,13 @@ static VEDBoardInfo a9_daughterboard = {\n> \n> static void a15_daughterboard_init(const VexpressMachineState *vms,\n> ram_addr_t ram_size,\n> - const char *cpu_model,\n> + const char *cpu_type,\n> qemu_irq *pic)\n> {\n> MemoryRegion *sysmem = get_system_memory();\n> MemoryRegion *ram = g_new(MemoryRegion, 1);\n> MemoryRegion *sram = g_new(MemoryRegion, 1);\n> \n> - if (!cpu_model) {\n> - cpu_model = \"cortex-a15\";\n> - }\n> -\n> {\n> /* We have to use a separate 64 bit variable here to avoid the gcc\n> * \"comparison is always false due to limited range of data type\"\n> @@ -378,7 +364,7 @@ static void a15_daughterboard_init(const VexpressMachineState *vms,\n> memory_region_add_subregion(sysmem, 0x80000000, ram);\n> \n> /* 0x2c000000 A15MPCore private memory region (GIC) */\n> - init_cpus(cpu_model, \"a15mpcore_priv\", 0x2c000000, pic, vms->secure);\n> + init_cpus(cpu_type, \"a15mpcore_priv\", 0x2c000000, pic, vms->secure);\n> \n> /* A15 daughterboard peripherals: */\n> \n> @@ -558,7 +544,7 @@ static void vexpress_common_init(MachineState *machine)\n> const hwaddr *map = daughterboard->motherboard_map;\n> int i;\n> \n> - daughterboard->init(vms, machine->ram_size, machine->cpu_model, pic);\n> + daughterboard->init(vms, machine->ram_size, machine->cpu_type, pic);\n> \n> /*\n> * If a bios file was provided, attempt to map it into memory\n> @@ -758,6 +744,7 @@ static void vexpress_a9_class_init(ObjectClass *oc, void *data)\n> VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc);\n> \n> mc->desc = \"ARM Versatile Express for Cortex-A9\";\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"cortex-a9\");\n> \n> vmc->daughterboard = &a9_daughterboard;\n> }\n> @@ -768,6 +755,7 @@ static void vexpress_a15_class_init(ObjectClass *oc, void *data)\n> VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc);\n> \n> mc->desc = \"ARM Versatile Express for Cortex-A15\";\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"cortex-a15\");\n> \n> vmc->daughterboard = &a15_daughterboard;\n> }\n> diff --git a/hw/arm/virt.c b/hw/arm/virt.c\n> index 6b7a0fe..c68cf08 100644\n> --- a/hw/arm/virt.c\n> +++ b/hw/arm/virt.c\n> @@ -163,13 +163,13 @@ static const int a15irqmap[] = {\n> };\n> \n> static const char *valid_cpus[] = {\n> - \"cortex-a15\",\n> - \"cortex-a53\",\n> - \"cortex-a57\",\n> - \"host\",\n> + ARM_CPU_TYPE_NAME(\"cortex-a15\"),\n> + ARM_CPU_TYPE_NAME(\"cortex-a53\"),\n> + ARM_CPU_TYPE_NAME(\"cortex-a57\"),\n> + ARM_CPU_TYPE_NAME(\"host\"),\n> };\n\nI think this is the 4th case where machine code validates the CPU\ntype. It looks like a generic MachineClass::valid_cpu_types[]\nfield will be very useful.\n\n\n> \n> -static bool cpuname_valid(const char *cpu)\n> +static bool cpu_type_valid(const char *cpu)\n> {\n> int i;\n> \n> @@ -1250,18 +1250,8 @@ static void machvirt_init(MachineState *machine)\n> MemoryRegion *secure_sysmem = NULL;\n> int n, virt_max_cpus;\n> MemoryRegion *ram = g_new(MemoryRegion, 1);\n> - const char *cpu_model = machine->cpu_model;\n> - char **cpustr;\n> - ObjectClass *oc;\n> - const char *typename;\n> - CPUClass *cc;\n> - Error *err = NULL;\n> bool firmware_loaded = bios_name || drive_get(IF_PFLASH, 0, 0);\n> \n> - if (!cpu_model) {\n> - cpu_model = \"cortex-a15\";\n> - }\n> -\n> /* We can probe only here because during property set\n> * KVM is not available yet\n> */\n> @@ -1278,11 +1268,8 @@ static void machvirt_init(MachineState *machine)\n> }\n> }\n> \n> - /* Separate the actual CPU model name from any appended features */\n> - cpustr = g_strsplit(cpu_model, \",\", 2);\n> -\n> - if (!cpuname_valid(cpustr[0])) {\n> - error_report(\"mach-virt: CPU %s not supported\", cpustr[0]);\n> + if (!cpu_type_valid(machine->cpu_type)) {\n> + error_report(\"mach-virt: CPU type %s not supported\", machine->cpu_type);\n> exit(1);\n> }\n\nNice.\n\n> \n> @@ -1352,22 +1339,6 @@ static void machvirt_init(MachineState *machine)\n> \n> create_fdt(vms);\n> \n> - oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]);\n> - if (!oc) {\n> - error_report(\"Unable to find CPU definition\");\n> - exit(1);\n> - }\n> - typename = object_class_get_name(oc);\n> -\n> - /* convert -smp CPU options specified by the user into global props */\n> - cc = CPU_CLASS(oc);\n> - cc->parse_features(typename, cpustr[1], &err);\n> - g_strfreev(cpustr);\n> - if (err) {\n> - error_report_err(err);\n> - exit(1);\n> - }\n> -\n\nNice.\n\n> possible_cpus = mc->possible_cpu_arch_ids(machine);\n> for (n = 0; n < possible_cpus->len; n++) {\n> Object *cpuobj;\n> @@ -1377,7 +1348,7 @@ static void machvirt_init(MachineState *machine)\n> break;\n> }\n> \n> - cpuobj = object_new(typename);\n> + cpuobj = object_new(machine->cpu_type);\n> object_property_set_int(cpuobj, possible_cpus->cpus[n].arch_id,\n> \"mp-affinity\", NULL);\n> \n> @@ -1622,6 +1593,7 @@ static void virt_machine_class_init(ObjectClass *oc, void *data)\n> mc->minimum_page_bits = 12;\n> mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;\n> mc->cpu_index_to_instance_props = virt_cpu_index_to_props;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"cortex-a15\");\n> }\n> \n> static const TypeInfo virt_machine_info = {\n> diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c\n> index 6b11a75..4efca78 100644\n> --- a/hw/arm/xilinx_zynq.c\n> +++ b/hw/arm/xilinx_zynq.c\n> @@ -156,11 +156,9 @@ static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq,\n> static void zynq_init(MachineState *machine)\n> {\n> ram_addr_t ram_size = machine->ram_size;\n> - const char *cpu_model = machine->cpu_model;\n> const char *kernel_filename = machine->kernel_filename;\n> const char *kernel_cmdline = machine->kernel_cmdline;\n> const char *initrd_filename = machine->initrd_filename;\n> - ObjectClass *cpu_oc;\n> ARMCPU *cpu;\n> MemoryRegion *address_space_mem = get_system_memory();\n> MemoryRegion *ext_ram = g_new(MemoryRegion, 1);\n> @@ -172,12 +170,7 @@ static void zynq_init(MachineState *machine)\n> qemu_irq pic[64];\n> int n;\n> \n> - if (!cpu_model) {\n> - cpu_model = \"cortex-a9\";\n> - }\n> - cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);\n> -\n> - cpu = ARM_CPU(object_new(object_class_get_name(cpu_oc)));\n> + cpu = ARM_CPU(object_new(machine->cpu_type));\n> \n> /* By default A9 CPUs have EL3 enabled. This board does not\n> * currently support EL3 so the CPU EL3 property is disabled before\n> @@ -324,6 +317,7 @@ static void zynq_machine_init(MachineClass *mc)\n> mc->init = zynq_init;\n> mc->max_cpus = 1;\n> mc->no_sdcard = 1;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"cortex-a9\");\n> }\n> \n> DEFINE_MACHINE(\"xilinx-zynq-a9\", zynq_machine_init)\n> diff --git a/hw/arm/z2.c b/hw/arm/z2.c\n> index 1607cbd..f306407 100644\n> --- a/hw/arm/z2.c\n> +++ b/hw/arm/z2.c\n> @@ -26,6 +26,7 @@\n> #include \"audio/audio.h\"\n> #include \"exec/address-spaces.h\"\n> #include \"sysemu/qtest.h\"\n> +#include \"cpu.h\"\n> \n> #ifdef DEBUG_Z2\n> #define DPRINTF(fmt, ...) \\\n> @@ -296,7 +297,6 @@ static const TypeInfo aer915_info = {\n> \n> static void z2_init(MachineState *machine)\n> {\n> - const char *cpu_model = machine->cpu_model;\n> const char *kernel_filename = machine->kernel_filename;\n> const char *kernel_cmdline = machine->kernel_cmdline;\n> const char *initrd_filename = machine->initrd_filename;\n> @@ -309,12 +309,8 @@ static void z2_init(MachineState *machine)\n> I2CBus *bus;\n> DeviceState *wm;\n> \n> - if (!cpu_model) {\n> - cpu_model = \"pxa270-c5\";\n> - }\n> -\n> /* Setup CPU & memory */\n> - mpu = pxa270_init(address_space_mem, z2_binfo.ram_size, cpu_model);\n> + mpu = pxa270_init(address_space_mem, z2_binfo.ram_size, machine->cpu_type);\n> \n> #ifdef TARGET_WORDS_BIGENDIAN\n> be = 1;\n> @@ -370,6 +366,7 @@ static void z2_machine_init(MachineClass *mc)\n> {\n> mc->desc = \"Zipit Z2 (PXA27x)\";\n> mc->init = z2_init;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"pxa270-c5\");\n> }\n> \n> DEFINE_MACHINE(\"z2\", z2_machine_init)\n> diff --git a/target/arm/cpu.c b/target/arm/cpu.c\n> index 05c038b..feeeeb2 100644\n> --- a/target/arm/cpu.c\n> +++ b/target/arm/cpu.c\n> @@ -867,7 +867,7 @@ static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)\n> }\n> \n> cpuname = g_strsplit(cpu_model, \",\", 1);\n> - typename = g_strdup_printf(\"%s-\" TYPE_ARM_CPU, cpuname[0]);\n> + typename = g_strdup_printf(\"%s\" ARM_CPU_TYPE_SUFFIX, cpuname[0]);\n\nWhat about doing the same we do in x86 and s390:\n\n g_strdup_printf(ARM_CPU_TYPE_NAME(\"%s\"), cpuname[0]);\n\n> oc = object_class_by_name(typename);\n> g_strfreev(cpuname);\n> g_free(typename);\n> -- \n> 2.7.4\n> \n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<1504533662-198084-7-git-send-email-imammedo@redhat.com>","X-Fnord":"you can see the fnord","User-Agent":"Mutt/1.8.3 (2017-05-23)","X-Scanned-By":"MIMEDefang 2.79 on 10.5.11.16","X-Greylist":"Sender IP whitelisted, not delayed by milter-greylist-4.5.16\n\t(mx1.redhat.com [10.5.110.26]);\n\tTue, 05 Sep 2017 21:31:55 +0000 (UTC)","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]","X-Received-From":"209.132.183.28","Subject":"Re: [Qemu-devel] [PATCH 6/6] arm: drop intermadiate cpu_model ->\n\tcpu type parsing and use cpu type directly","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Peter Maydell ,\n\tAndrew Jones , \n\tRob Herring , Igor Mitsyanko ,\n\tAlistair Francis , qemu-devel@nongnu.org,\n\tqemu-arm@nongnu.org, Jan Kiszka ,\n\t\"Edgar E. Iglesias\" ,\n\tRichard Henderson ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1763683,"web_url":"http://patchwork.ozlabs.org/comment/1763683/","msgid":"","list_archive_url":null,"date":"2017-09-05T21:47:52","subject":"Re: [Qemu-devel] [PATCH 6/6] arm: drop intermadiate cpu_model ->\n\tcpu type parsing and use cpu type directly","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/people/64571/","name":"Alistair Francis","email":"alistair23@gmail.com"},"content":"On Tue, Sep 5, 2017 at 2:31 PM, Eduardo Habkost wrote:\n> On Mon, Sep 04, 2017 at 04:01:02PM +0200, Igor Mammedov wrote:\n>> there are 2 use cases to deal with:\n>> 1: fixed CPU models per board/soc\n>> 2: boards with user configurable cpu_model and fallback to\n>> default cpu_model if user hasn't specified one explicitly\n>>\n>> For the 1st\n>> drop intermediate cpu_model parsing and use const cpu type\n>> directly, which replaces:\n>> typename = object_class_get_name(\n>> cpu_class_by_name(TYPE_ARM_CPU, cpu_model))\n>> object_new(typename)\n>> with\n>> object_new(FOO_CPU_TYPE_NAME)\n>> or\n>> cpu_generic_init(BASE_CPU_TYPE, \"my cpu model\")\n>> with\n>> cpu_create(FOO_CPU_TYPE_NAME)\n>>\n>> as result 1st use case doesn't have to invoke not necessary\n>> translation and not needed code is removed.\n>>\n>> For the 2nd\n>> 1: set default cpu type with MachineClass::default_cpu_type and\n>> 2: use generic cpu_model parsing that done before machine_init()\n>> is run and:\n>> 2.1: drop custom cpu_model parsing where pattern is:\n>> typename = object_class_get_name(\n>> cpu_class_by_name(TYPE_ARM_CPU, cpu_model))\n>> [parse_features(typename, cpu_model, &err) ]\n>>\n>> 2.2: or replace cpu_generic_init() which does what\n>> 2.1 does + create_cpu(typename) with just\n>> create_cpu(machine->cpu_type)\n>> as result cpu_name -> cpu_type translation is done using\n>> generic machine code one including parsing optional features\n>> if supported/present (removes a bunch of duplicated cpu_model\n>> parsing code) and default cpu type is defined in an uniform way\n>> within machine_class_init callbacks instead of adhoc places\n>> in boadr's machine_init code.\n>>\n>> Signed-off-by: Igor Mammedov \n>> ---\n>> CC: Peter Maydell \n>> CC: Igor Mitsyanko \n>> CC: Rob Herring \n>> CC: Andrzej Zaborowski \n>> CC: Jan Kiszka \n>> CC: Alistair Francis \n>> CC: \"Edgar E. Iglesias\" \n>> CC: qemu-arm@nongnu.org\n>> ---\n>> include/hw/arm/armv7m.h | 2 +-\n>> include/hw/arm/aspeed_soc.h | 2 +-\n>> include/hw/arm/stm32f205_soc.h | 2 +-\n>> target/arm/cpu.h | 3 +++\n>> hw/arm/armv7m.c | 40 +++++-------------------------------\n>> hw/arm/aspeed_soc.c | 13 +++++-------\n>> hw/arm/collie.c | 10 +++------\n>> hw/arm/exynos4210.c | 6 +-----\n>> hw/arm/gumstix.c | 5 +++--\n>> hw/arm/highbank.c | 10 ++++-----\n>> hw/arm/integratorcp.c | 30 ++-------------------------\n>> hw/arm/mainstone.c | 9 ++++-----\n>> hw/arm/mps2.c | 17 +++++++---------\n>> hw/arm/musicpal.c | 7 ++-----\n>> hw/arm/netduino2.c | 2 +-\n>> hw/arm/nseries.c | 4 +++-\n>> hw/arm/omap1.c | 7 ++-----\n>> hw/arm/omap2.c | 4 ++--\n>> hw/arm/omap_sx1.c | 5 ++++-\n>> hw/arm/palm.c | 5 +++--\n>> hw/arm/pxa2xx.c | 10 ++++-----\n>> hw/arm/realview.c | 25 +++++------------------\n>> hw/arm/spitz.c | 12 ++++++-----\n>> hw/arm/stellaris.c | 16 +++++++--------\n>> hw/arm/stm32f205_soc.c | 4 ++--\n>> hw/arm/strongarm.c | 10 +++------\n>> hw/arm/tosa.c | 4 ----\n>> hw/arm/versatilepb.c | 15 +++-----------\n>> hw/arm/vexpress.c | 32 +++++++++--------------------\n>> hw/arm/virt.c | 46 +++++++++---------------------------------\n>> hw/arm/xilinx_zynq.c | 10 ++-------\n>> hw/arm/z2.c | 9 +++------\n>> target/arm/cpu.c | 2 +-\n>> 33 files changed, 114 insertions(+), 264 deletions(-)\n>>\n>> diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h\n>> index a9b3f2a..8496743 100644\n>> --- a/include/hw/arm/armv7m.h\n>> +++ b/include/hw/arm/armv7m.h\n>> @@ -55,7 +55,7 @@ typedef struct ARMv7MState {\n>> MemoryRegion container;\n>>\n>> /* Properties */\n>> - char *cpu_model;\n>> + char *cpu_type;\n>> /* MemoryRegion the board provides to us (with its devices, RAM, etc) */\n>> MemoryRegion *board_memory;\n>> } ARMv7MState;\n>> diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h\n>> index 0b88baa..f26914a 100644\n>> --- a/include/hw/arm/aspeed_soc.h\n>> +++ b/include/hw/arm/aspeed_soc.h\n>> @@ -49,7 +49,7 @@ typedef struct AspeedSoCState {\n>>\n>> typedef struct AspeedSoCInfo {\n>> const char *name;\n>> - const char *cpu_model;\n>> + const char *cpu_type;\n>> uint32_t silicon_rev;\n>> hwaddr sdram_base;\n>> uint64_t sram_size;\n>> diff --git a/include/hw/arm/stm32f205_soc.h b/include/hw/arm/stm32f205_soc.h\n>> index e2dce11..922a733 100644\n>> --- a/include/hw/arm/stm32f205_soc.h\n>> +++ b/include/hw/arm/stm32f205_soc.h\n>> @@ -52,7 +52,7 @@ typedef struct STM32F205State {\n>> SysBusDevice parent_obj;\n>> /*< public >*/\n>>\n>> - char *cpu_model;\n>> + char *cpu_type;\n>>\n>> ARMv7MState armv7m;\n>>\n>> diff --git a/target/arm/cpu.h b/target/arm/cpu.h\n>> index 5932ef1..3e1ba19 100644\n>> --- a/target/arm/cpu.h\n>> +++ b/target/arm/cpu.h\n>> @@ -2002,6 +2002,9 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,\n>>\n>> #define cpu_init(cpu_model) cpu_generic_init(TYPE_ARM_CPU, cpu_model)\n>>\n>> +#define ARM_CPU_TYPE_SUFFIX \"-\" TYPE_ARM_CPU\n>> +#define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX)\n>> +\n>> #define cpu_signal_handler cpu_arm_signal_handler\n>> #define cpu_list arm_cpu_list\n>>\n>> diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c\n>> index c8a11f2..9c45f26 100644\n>> --- a/hw/arm/armv7m.c\n>> +++ b/hw/arm/armv7m.c\n>> @@ -163,10 +163,6 @@ static void armv7m_realize(DeviceState *dev, Error **errp)\n>> SysBusDevice *sbd;\n>> Error *err = NULL;\n>> int i;\n>> - char **cpustr;\n>> - ObjectClass *oc;\n>> - const char *typename;\n>> - CPUClass *cc;\n>>\n>> if (!s->board_memory) {\n>> error_setg(errp, \"memory property was not set\");\n>> @@ -175,29 +171,7 @@ static void armv7m_realize(DeviceState *dev, Error **errp)\n>>\n>> memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1);\n>>\n>> - cpustr = g_strsplit(s->cpu_model, \",\", 2);\n>> -\n>> - oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]);\n>> - if (!oc) {\n>> - error_setg(errp, \"Unknown CPU model %s\", cpustr[0]);\n>> - g_strfreev(cpustr);\n>> - return;\n>> - }\n>> -\n>> - cc = CPU_CLASS(oc);\n>> - typename = object_class_get_name(oc);\n>> - cc->parse_features(typename, cpustr[1], &err);\n>> - g_strfreev(cpustr);\n>> - if (err) {\n>> - error_propagate(errp, err);\n>> - return;\n>> - }\n>> -\n>> - s->cpu = ARM_CPU(object_new(typename));\n>> - if (!s->cpu) {\n>> - error_setg(errp, \"Unknown CPU model %s\", s->cpu_model);\n>> - return;\n>> - }\n>> + s->cpu = ARM_CPU(object_new(s->cpu_type));\n>\n> Nice.\n>\n>>\n>> object_property_set_link(OBJECT(s->cpu), OBJECT(&s->container), \"memory\",\n>> &error_abort);\n>> @@ -253,7 +227,7 @@ static void armv7m_realize(DeviceState *dev, Error **errp)\n>> }\n>>\n>> static Property armv7m_properties[] = {\n>> - DEFINE_PROP_STRING(\"cpu-model\", ARMv7MState, cpu_model),\n>> + DEFINE_PROP_STRING(\"cpu-type\", ARMv7MState, cpu_type),\n>\n> Are we 100% sure the cpu-model property is never manually set by\n> users?\n>\n>\n>> DEFINE_PROP_END_OF_LIST(),\n>> };\n>>\n>> @@ -285,20 +259,16 @@ static void armv7m_reset(void *opaque)\n>> Returns the ARMv7M device. */\n>>\n>> DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,\n>> - const char *kernel_filename, const char *cpu_model)\n>> + const char *kernel_filename, const char *cpu_type)\n>> {\n>> DeviceState *armv7m;\n>>\n>> - if (cpu_model == NULL) {\n>> - cpu_model = \"cortex-m3\";\n>> - }\n>> -\n>\n> I was going to suggest doing the default_cpu_type stuff in a\n> separate patch, but it might require touching those lines twice.\n> So I guess this is OK.\n>\n>\n>> armv7m = qdev_create(NULL, \"armv7m\");\n>> qdev_prop_set_uint32(armv7m, \"num-irq\", num_irq);\n>> - qdev_prop_set_string(armv7m, \"cpu-model\", cpu_model);\n>> + qdev_prop_set_string(armv7m, \"cpu-type\", cpu_type);\n>> object_property_set_link(OBJECT(armv7m), OBJECT(get_system_memory()),\n>> \"memory\", &error_abort);\n>> - /* This will exit with an error if the user passed us a bad cpu_model */\n>> + /* This will exit with an error if the user passed us a bad cpu_type */\n>> qdev_init_nofail(armv7m);\n>>\n>> armv7m_load_kernel(ARM_CPU(first_cpu), kernel_filename, mem_size);\n>> diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c\n>> index 5529024..cd7bb94 100644\n>> --- a/hw/arm/aspeed_soc.c\n>> +++ b/hw/arm/aspeed_soc.c\n>> @@ -54,7 +54,7 @@ static const char *aspeed_soc_ast2500_typenames[] = {\n>> static const AspeedSoCInfo aspeed_socs[] = {\n>> {\n>> .name = \"ast2400-a0\",\n>> - .cpu_model = \"arm926\",\n>> + .cpu_type = ARM_CPU_TYPE_NAME(\"arm926\"),\n>> .silicon_rev = AST2400_A0_SILICON_REV,\n>> .sdram_base = AST2400_SDRAM_BASE,\n>> .sram_size = 0x8000,\n>> @@ -65,7 +65,7 @@ static const AspeedSoCInfo aspeed_socs[] = {\n>> .wdts_num = 2,\n>> }, {\n>> .name = \"ast2400-a1\",\n>> - .cpu_model = \"arm926\",\n>> + .cpu_type = ARM_CPU_TYPE_NAME(\"arm926\"),\n>> .silicon_rev = AST2400_A1_SILICON_REV,\n>> .sdram_base = AST2400_SDRAM_BASE,\n>> .sram_size = 0x8000,\n>> @@ -76,7 +76,7 @@ static const AspeedSoCInfo aspeed_socs[] = {\n>> .wdts_num = 2,\n>> }, {\n>> .name = \"ast2400\",\n>> - .cpu_model = \"arm926\",\n>> + .cpu_type = ARM_CPU_TYPE_NAME(\"arm926\"),\n>> .silicon_rev = AST2400_A0_SILICON_REV,\n>> .sdram_base = AST2400_SDRAM_BASE,\n>> .sram_size = 0x8000,\n>> @@ -87,7 +87,7 @@ static const AspeedSoCInfo aspeed_socs[] = {\n>> .wdts_num = 2,\n>> }, {\n>> .name = \"ast2500-a1\",\n>> - .cpu_model = \"arm1176\",\n>> + .cpu_type = ARM_CPU_TYPE_NAME(\"arm1176\"),\n>> .silicon_rev = AST2500_A1_SILICON_REV,\n>> .sdram_base = AST2500_SDRAM_BASE,\n>> .sram_size = 0x9000,\n>> @@ -128,13 +128,10 @@ static void aspeed_soc_init(Object *obj)\n>> {\n>> AspeedSoCState *s = ASPEED_SOC(obj);\n>> AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);\n>> - char *cpu_typename;\n>> int i;\n>>\n>> - cpu_typename = g_strdup_printf(\"%s-\" TYPE_ARM_CPU, sc->info->cpu_model);\n>> - object_initialize(&s->cpu, sizeof(s->cpu), cpu_typename);\n>> + object_initialize(&s->cpu, sizeof(s->cpu), sc->info->cpu_type);\n>> object_property_add_child(obj, \"cpu\", OBJECT(&s->cpu), NULL);\n>> - g_free(cpu_typename);\n>>\n>\n> Nice.\n>\n>> object_initialize(&s->vic, sizeof(s->vic), TYPE_ASPEED_VIC);\n>> object_property_add_child(obj, \"vic\", OBJECT(&s->vic), NULL);\n>> diff --git a/hw/arm/collie.c b/hw/arm/collie.c\n>> index 2e69531..f043cd8 100644\n>> --- a/hw/arm/collie.c\n>> +++ b/hw/arm/collie.c\n>> @@ -18,7 +18,7 @@\n>> #include \"hw/block/flash.h\"\n>> #include \"sysemu/block-backend.h\"\n>> #include \"exec/address-spaces.h\"\n>> -#include \"qom/cpu.h\"\n>> +#include \"cpu.h\"\n>>\n>> static struct arm_boot_info collie_binfo = {\n>> .loader_start = SA_SDCS0,\n>> @@ -27,7 +27,6 @@ static struct arm_boot_info collie_binfo = {\n>>\n>> static void collie_init(MachineState *machine)\n>> {\n>> - const char *cpu_model = machine->cpu_model;\n>> const char *kernel_filename = machine->kernel_filename;\n>> const char *kernel_cmdline = machine->kernel_cmdline;\n>> const char *initrd_filename = machine->initrd_filename;\n>> @@ -35,11 +34,7 @@ static void collie_init(MachineState *machine)\n>> DriveInfo *dinfo;\n>> MemoryRegion *sysmem = get_system_memory();\n>>\n>> - if (!cpu_model) {\n>> - cpu_model = \"sa1110\";\n>> - }\n>> -\n>> - s = sa1110_init(sysmem, collie_binfo.ram_size, cpu_model);\n>> + s = sa1110_init(sysmem, collie_binfo.ram_size, machine->cpu_type);\n>>\n>> dinfo = drive_get(IF_PFLASH, 0, 0);\n>> pflash_cfi01_register(SA_CS0, NULL, \"collie.fl1\", 0x02000000,\n>> @@ -64,6 +59,7 @@ static void collie_machine_init(MachineClass *mc)\n>> {\n>> mc->desc = \"Sharp SL-5500 (Collie) PDA (SA-1110)\";\n>> mc->init = collie_init;\n>> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"sa1110\");\n>> }\n>>\n>> DEFINE_MACHINE(\"collie\", collie_machine_init)\n>> diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c\n>> index f9e79f3..81f12e3 100644\n>> --- a/hw/arm/exynos4210.c\n>> +++ b/hw/arm/exynos4210.c\n>> @@ -169,15 +169,11 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem)\n>> Exynos4210State *s = g_new(Exynos4210State, 1);\n>> qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];\n>> SysBusDevice *busdev;\n>> - ObjectClass *cpu_oc;\n>> DeviceState *dev;\n>> int i, n;\n>>\n>> - cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, \"cortex-a9\");\n>> - assert(cpu_oc);\n>> -\n>> for (n = 0; n < EXYNOS4210_NCPUS; n++) {\n>> - Object *cpuobj = object_new(object_class_get_name(cpu_oc));\n>> + Object *cpuobj = object_new(ARM_CPU_TYPE_NAME(\"cortex-a9\"));\n>>\n>> /* By default A9 CPUs have EL3 enabled. This board does not currently\n>> * support EL3 so the CPU EL3 property is disabled before realization.\n>> diff --git a/hw/arm/gumstix.c b/hw/arm/gumstix.c\n>> index d59d9ba..2b66bb7 100644\n>> --- a/hw/arm/gumstix.c\n>> +++ b/hw/arm/gumstix.c\n>> @@ -44,6 +44,7 @@\n>> #include \"sysemu/block-backend.h\"\n>> #include \"exec/address-spaces.h\"\n>> #include \"sysemu/qtest.h\"\n>> +#include \"cpu.h\"\n>>\n>> static const int sector_len = 128 * 1024;\n>>\n>> @@ -86,7 +87,6 @@ static void connex_init(MachineState *machine)\n>>\n>> static void verdex_init(MachineState *machine)\n>> {\n>> - const char *cpu_model = machine->cpu_model;\n>> PXA2xxState *cpu;\n>> DriveInfo *dinfo;\n>> int be;\n>> @@ -95,7 +95,7 @@ static void verdex_init(MachineState *machine)\n>> uint32_t verdex_rom = 0x02000000;\n>> uint32_t verdex_ram = 0x10000000;\n>>\n>> - cpu = pxa270_init(address_space_mem, verdex_ram, cpu_model ?: \"pxa270-c0\");\n>> + cpu = pxa270_init(address_space_mem, verdex_ram, machine->cpu_type);\n>>\n>> dinfo = drive_get(IF_PFLASH, 0, 0);\n>> if (!dinfo && !qtest_enabled()) {\n>> @@ -142,6 +142,7 @@ static void verdex_class_init(ObjectClass *oc, void *data)\n>>\n>> mc->desc = \"Gumstix Verdex (PXA270)\";\n>> mc->init = verdex_init;\n>> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"pxa270-c0\");\n>> }\n>>\n>> static const TypeInfo verdex_type = {\n>> diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c\n>> index 20e60f1..0d7190a 100644\n>> --- a/hw/arm/highbank.c\n>> +++ b/hw/arm/highbank.c\n>> @@ -219,7 +219,6 @@ enum cxmachines {\n>> static void calxeda_init(MachineState *machine, enum cxmachines machine_id)\n>> {\n>> ram_addr_t ram_size = machine->ram_size;\n>> - const char *cpu_model = machine->cpu_model;\n>> const char *kernel_filename = machine->kernel_filename;\n>> const char *kernel_cmdline = machine->kernel_cmdline;\n>> const char *initrd_filename = machine->initrd_filename;\n>> @@ -236,19 +235,20 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id)\n>>\n>> switch (machine_id) {\n>> case CALXEDA_HIGHBANK:\n>> - cpu_model = \"cortex-a9\";\n>> + machine->cpu_type = ARM_CPU_TYPE_NAME(\"cortex-a9\");\n>> break;\n>> case CALXEDA_MIDWAY:\n>> - cpu_model = \"cortex-a15\";\n>> + machine->cpu_type = ARM_CPU_TYPE_NAME(\"cortex-a15\");\n>> break;\n>> + default:\n>> + assert(0);\n>> }\n>\n> Why not delete this switch statement completely and set\n> default_cpu_type at midway_class_init() and\n> highbank_class_init()?\n>\n>\n>>\n>> for (n = 0; n < smp_cpus; n++) {\n>> - ObjectClass *oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);\n>> Object *cpuobj;\n>> ARMCPU *cpu;\n>>\n>> - cpuobj = object_new(object_class_get_name(oc));\n>> + cpuobj = object_new(machine->cpu_type);\n>> cpu = ARM_CPU(cpuobj);\n>>\n>> object_property_set_int(cpuobj, QEMU_PSCI_CONDUIT_SMC,\n>> diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c\n>> index d9530ed..44d247e 100644\n>> --- a/hw/arm/integratorcp.c\n>> +++ b/hw/arm/integratorcp.c\n>> @@ -572,46 +572,19 @@ static struct arm_boot_info integrator_binfo = {\n>> static void integratorcp_init(MachineState *machine)\n>> {\n>> ram_addr_t ram_size = machine->ram_size;\n>> - const char *cpu_model = machine->cpu_model;\n>> const char *kernel_filename = machine->kernel_filename;\n>> const char *kernel_cmdline = machine->kernel_cmdline;\n>> const char *initrd_filename = machine->initrd_filename;\n>> - char **cpustr;\n>> - ObjectClass *cpu_oc;\n>> - CPUClass *cc;\n>> Object *cpuobj;\n>> ARMCPU *cpu;\n>> - const char *typename;\n>> MemoryRegion *address_space_mem = get_system_memory();\n>> MemoryRegion *ram = g_new(MemoryRegion, 1);\n>> MemoryRegion *ram_alias = g_new(MemoryRegion, 1);\n>> qemu_irq pic[32];\n>> DeviceState *dev, *sic, *icp;\n>> int i;\n>> - Error *err = NULL;\n>>\n>> - if (!cpu_model) {\n>> - cpu_model = \"arm926\";\n>> - }\n>> -\n>> - cpustr = g_strsplit(cpu_model, \",\", 2);\n>> -\n>> - cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]);\n>> - if (!cpu_oc) {\n>> - fprintf(stderr, \"Unable to find CPU definition\\n\");\n>> - exit(1);\n>> - }\n>> - typename = object_class_get_name(cpu_oc);\n>> -\n>> - cc = CPU_CLASS(cpu_oc);\n>> - cc->parse_features(typename, cpustr[1], &err);\n>> - g_strfreev(cpustr);\n>> - if (err) {\n>> - error_report_err(err);\n>> - exit(1);\n>> - }\n>> -\n>> - cpuobj = object_new(typename);\n>> + cpuobj = object_new(machine->cpu_type);\n>\n> Nice.\n>\n>>\n>> /* By default ARM1176 CPUs have EL3 enabled. This board does not\n>> * currently support EL3 so the CPU EL3 property is disabled before\n>> @@ -681,6 +654,7 @@ static void integratorcp_machine_init(MachineClass *mc)\n>> {\n>> mc->desc = \"ARM Integrator/CP (ARM926EJ-S)\";\n>> mc->init = integratorcp_init;\n>> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"arm926\");\n>> }\n>>\n>> DEFINE_MACHINE(\"integratorcp\", integratorcp_machine_init)\n>> diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c\n>> index fb268e6..2b13d30 100644\n>> --- a/hw/arm/mainstone.c\n>> +++ b/hw/arm/mainstone.c\n>> @@ -24,6 +24,7 @@\n>> #include \"hw/sysbus.h\"\n>> #include \"exec/address-spaces.h\"\n>> #include \"sysemu/qtest.h\"\n>> +#include \"cpu.h\"\n>>\n>> /* Device addresses */\n>> #define MST_FPGA_PHYS 0x08000000\n>> @@ -121,13 +122,10 @@ static void mainstone_common_init(MemoryRegion *address_space_mem,\n>> int i;\n>> int be;\n>> MemoryRegion *rom = g_new(MemoryRegion, 1);\n>> - const char *cpu_model = machine->cpu_model;\n>> -\n>> - if (!cpu_model)\n>> - cpu_model = \"pxa270-c5\";\n>>\n>> /* Setup CPU & memory */\n>> - mpu = pxa270_init(address_space_mem, mainstone_binfo.ram_size, cpu_model);\n>> + mpu = pxa270_init(address_space_mem, mainstone_binfo.ram_size,\n>> + machine->cpu_type);\n>> memory_region_init_ram(rom, NULL, \"mainstone.rom\", MAINSTONE_ROM,\n>> &error_fatal);\n>> memory_region_set_readonly(rom, true);\n>> @@ -196,6 +194,7 @@ static void mainstone2_machine_init(MachineClass *mc)\n>> {\n>> mc->desc = \"Mainstone II (PXA27x)\";\n>> mc->init = mainstone_init;\n>> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"pxa270-c5\");\n>> }\n>>\n>> DEFINE_MACHINE(\"mainstone\", mainstone2_machine_init)\n>> diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c\n>> index abb0ab6..aeaad80 100644\n>> --- a/hw/arm/mps2.c\n>> +++ b/hw/arm/mps2.c\n>> @@ -46,7 +46,6 @@ typedef enum MPS2FPGAType {\n>> typedef struct {\n>> MachineClass parent;\n>> MPS2FPGAType fpga_type;\n>> - const char *cpu_model;\n>> uint32_t scc_id;\n>> } MPS2MachineClass;\n>>\n>> @@ -107,14 +106,12 @@ static void mps2_common_init(MachineState *machine)\n>> MPS2MachineState *mms = MPS2_MACHINE(machine);\n>> MPS2MachineClass *mmc = MPS2_MACHINE_GET_CLASS(machine);\n>> MemoryRegion *system_memory = get_system_memory();\n>> + MachineClass *mc = MACHINE_GET_CLASS(machine);\n>> DeviceState *armv7m, *sccdev;\n>>\n>> - if (!machine->cpu_model) {\n>> - machine->cpu_model = mmc->cpu_model;\n>> - }\n>> -\n>> - if (strcmp(machine->cpu_model, mmc->cpu_model) != 0) {\n>> - error_report(\"This board can only be used with CPU %s\", mmc->cpu_model);\n>> + if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {\n>> + error_report(\"This board can only be used with CPU %s\",\n>> + mc->default_cpu_type);\n>\n> Suggestion for later: a generic mechanism to let the machine\n> class validate the CPU type this way. Maybe a\n> MachineClass::configurable_cpu_type=false field?\n>\n>\n>> exit(1);\n>> }\n>>\n>> @@ -188,7 +185,7 @@ static void mps2_common_init(MachineState *machine)\n>> default:\n>> g_assert_not_reached();\n>> }\n>> - qdev_prop_set_string(armv7m, \"cpu-model\", machine->cpu_model);\n>> + qdev_prop_set_string(armv7m, \"cpu-type\", machine->cpu_type);\n>> object_property_set_link(OBJECT(&mms->armv7m), OBJECT(system_memory),\n>> \"memory\", &error_abort);\n>> object_property_set_bool(OBJECT(&mms->armv7m), true, \"realized\",\n>> @@ -339,7 +336,7 @@ static void mps2_an385_class_init(ObjectClass *oc, void *data)\n>>\n>> mc->desc = \"ARM MPS2 with AN385 FPGA image for Cortex-M3\";\n>> mmc->fpga_type = FPGA_AN385;\n>> - mmc->cpu_model = \"cortex-m3\";\n>> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"cortex-m3\");\n>> mmc->scc_id = 0x41040000 | (385 << 4);\n>> }\n>>\n>> @@ -350,7 +347,7 @@ static void mps2_an511_class_init(ObjectClass *oc, void *data)\n>>\n>> mc->desc = \"ARM MPS2 with AN511 DesignStart FPGA image for Cortex-M3\";\n>> mmc->fpga_type = FPGA_AN511;\n>> - mmc->cpu_model = \"cortex-m3\";\n>> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"cortex-m3\");\n>> mmc->scc_id = 0x4104000 | (511 << 4);\n>> }\n>>\n>> diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c\n>> index 64c8e09..9b2000d 100644\n>> --- a/hw/arm/musicpal.c\n>> +++ b/hw/arm/musicpal.c\n>> @@ -1570,7 +1570,6 @@ static struct arm_boot_info musicpal_binfo = {\n>>\n>> static void musicpal_init(MachineState *machine)\n>> {\n>> - const char *cpu_model = machine->cpu_model;\n>> const char *kernel_filename = machine->kernel_filename;\n>> const char *kernel_cmdline = machine->kernel_cmdline;\n>> const char *initrd_filename = machine->initrd_filename;\n>> @@ -1590,10 +1589,7 @@ static void musicpal_init(MachineState *machine)\n>> MemoryRegion *ram = g_new(MemoryRegion, 1);\n>> MemoryRegion *sram = g_new(MemoryRegion, 1);\n>>\n>> - if (!cpu_model) {\n>> - cpu_model = \"arm926\";\n>> - }\n>> - cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model));\n>> + cpu = ARM_CPU(cpu_create(machine->cpu_type));\n>>\n>> /* For now we use a fixed - the original - RAM size */\n>> memory_region_allocate_system_memory(ram, NULL, \"musicpal.ram\",\n>> @@ -1714,6 +1710,7 @@ static void musicpal_machine_init(MachineClass *mc)\n>> {\n>> mc->desc = \"Marvell 88w8618 / MusicPal (ARM926EJ-S)\";\n>> mc->init = musicpal_init;\n>> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"arm926\");\n>> }\n>>\n>> DEFINE_MACHINE(\"musicpal\", musicpal_machine_init)\n>> diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c\n>> index 3cfe332..4790824 100644\n>> --- a/hw/arm/netduino2.c\n>> +++ b/hw/arm/netduino2.c\n>> @@ -34,7 +34,7 @@ static void netduino2_init(MachineState *machine)\n>> DeviceState *dev;\n>>\n>> dev = qdev_create(NULL, TYPE_STM32F205_SOC);\n>> - qdev_prop_set_string(dev, \"cpu-model\", \"cortex-m3\");\n>> + qdev_prop_set_string(dev, \"cpu-type\", ARM_CPU_TYPE_NAME(\"cortex-m3\"));\n>> object_property_set_bool(OBJECT(dev), true, \"realized\", &error_fatal);\n>>\n>> armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,\n>> diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c\n>> index 503a3b6..b41850e 100644\n>> --- a/hw/arm/nseries.c\n>> +++ b/hw/arm/nseries.c\n>> @@ -1310,7 +1310,7 @@ static void n8x0_init(MachineState *machine,\n>> struct n800_s *s = (struct n800_s *) g_malloc0(sizeof(*s));\n>> int sdram_size = binfo->ram_size;\n>>\n>> - s->mpu = omap2420_mpu_init(sysmem, sdram_size, machine->cpu_model);\n>> + s->mpu = omap2420_mpu_init(sysmem, sdram_size, machine->cpu_type);\n>>\n>> /* Setup peripherals\n>> *\n>> @@ -1425,6 +1425,7 @@ static void n800_class_init(ObjectClass *oc, void *data)\n>> mc->desc = \"Nokia N800 tablet aka. RX-34 (OMAP2420)\";\n>> mc->init = n800_init;\n>> mc->default_boot_order = \"\";\n>> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"arm1136-r2\");\n>> }\n>>\n>> static const TypeInfo n800_type = {\n>> @@ -1440,6 +1441,7 @@ static void n810_class_init(ObjectClass *oc, void *data)\n>> mc->desc = \"Nokia N810 tablet aka. RX-44 (OMAP2420)\";\n>> mc->init = n810_init;\n>> mc->default_boot_order = \"\";\n>> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"arm1136-r2\");\n>> }\n>>\n>> static const TypeInfo n810_type = {\n>> diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c\n>> index 04e65ce..b3e7625 100644\n>> --- a/hw/arm/omap1.c\n>> +++ b/hw/arm/omap1.c\n>> @@ -3850,7 +3850,7 @@ static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s,\n>>\n>> struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,\n>> unsigned long sdram_size,\n>> - const char *core)\n>> + const char *cpu_type)\n>> {\n>> int i;\n>> struct omap_mpu_state_s *s = g_new0(struct omap_mpu_state_s, 1);\n>> @@ -3858,12 +3858,9 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,\n>> DriveInfo *dinfo;\n>> SysBusDevice *busdev;\n>>\n>> - if (!core)\n>> - core = \"ti925t\";\n>> -\n>> /* Core */\n>> s->mpu_model = omap310;\n>> - s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, core));\n>> + s->cpu = ARM_CPU(cpu_create(cpu_type));\n>> s->sdram_size = sdram_size;\n>> s->sram_size = OMAP15XX_SRAM_SIZE;\n>>\n>> diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c\n>> index 5821477..3f6076e 100644\n>> --- a/hw/arm/omap2.c\n>> +++ b/hw/arm/omap2.c\n>> @@ -2250,7 +2250,7 @@ static const struct dma_irq_map omap2_dma_irq_map[] = {\n>>\n>> struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,\n>> unsigned long sdram_size,\n>> - const char *core)\n>> + const char *cpu_type)\n>> {\n>> struct omap_mpu_state_s *s = g_new0(struct omap_mpu_state_s, 1);\n>> qemu_irq dma_irqs[4];\n>> @@ -2261,7 +2261,7 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,\n>>\n>> /* Core */\n>> s->mpu_model = omap2420;\n>> - s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, core ?: \"arm1136-r2\"));\n>> + s->cpu = ARM_CPU(cpu_create(cpu_type));\n>> s->sdram_size = sdram_size;\n>> s->sram_size = OMAP242X_SRAM_SIZE;\n>>\n>> diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c\n>> index 9809106..1236ec1 100644\n>> --- a/hw/arm/omap_sx1.c\n>> +++ b/hw/arm/omap_sx1.c\n>> @@ -36,6 +36,7 @@\n>> #include \"sysemu/block-backend.h\"\n>> #include \"sysemu/qtest.h\"\n>> #include \"exec/address-spaces.h\"\n>> +#include \"cpu.h\"\n>>\n>> /*****************************************************************************/\n>> /* Siemens SX1 Cellphone V1 */\n>> @@ -120,7 +121,7 @@ static void sx1_init(MachineState *machine, const int version)\n>> }\n>>\n>> mpu = omap310_mpu_init(address_space, sx1_binfo.ram_size,\n>> - machine->cpu_model);\n>> + machine->cpu_type);\n>>\n>> /* External Flash (EMIFS) */\n>> memory_region_init_ram(flash, NULL, \"omap_sx1.flash0-0\", flash_size,\n>> @@ -223,6 +224,7 @@ static void sx1_machine_v2_class_init(ObjectClass *oc, void *data)\n>>\n>> mc->desc = \"Siemens SX1 (OMAP310) V2\";\n>> mc->init = sx1_init_v2;\n>> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"ti925t\");\n>> }\n>>\n>> static const TypeInfo sx1_machine_v2_type = {\n>> @@ -237,6 +239,7 @@ static void sx1_machine_v1_class_init(ObjectClass *oc, void *data)\n>>\n>> mc->desc = \"Siemens SX1 (OMAP310) V1\";\n>> mc->init = sx1_init_v1;\n>> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"ti925t\");\n>> }\n>>\n>> static const TypeInfo sx1_machine_v1_type = {\n>> diff --git a/hw/arm/palm.c b/hw/arm/palm.c\n>> index 64cf8ca..862f048 100644\n>> --- a/hw/arm/palm.c\n>> +++ b/hw/arm/palm.c\n>> @@ -29,6 +29,7 @@\n>> #include \"hw/devices.h\"\n>> #include \"hw/loader.h\"\n>> #include \"exec/address-spaces.h\"\n>> +#include \"cpu.h\"\n>>\n>> static uint32_t static_readb(void *opaque, hwaddr offset)\n>> {\n>> @@ -195,7 +196,6 @@ static struct arm_boot_info palmte_binfo = {\n>>\n>> static void palmte_init(MachineState *machine)\n>> {\n>> - const char *cpu_model = machine->cpu_model;\n>> const char *kernel_filename = machine->kernel_filename;\n>> const char *kernel_cmdline = machine->kernel_cmdline;\n>> const char *initrd_filename = machine->initrd_filename;\n>> @@ -211,7 +211,7 @@ static void palmte_init(MachineState *machine)\n>> MemoryRegion *flash = g_new(MemoryRegion, 1);\n>> MemoryRegion *cs = g_new(MemoryRegion, 4);\n>>\n>> - mpu = omap310_mpu_init(address_space_mem, sdram_size, cpu_model);\n>> + mpu = omap310_mpu_init(address_space_mem, sdram_size, machine->cpu_type);\n>>\n>> /* External Flash (EMIFS) */\n>> memory_region_init_ram(flash, NULL, \"palmte.flash\", flash_size,\n>> @@ -274,6 +274,7 @@ static void palmte_machine_init(MachineClass *mc)\n>> {\n>> mc->desc = \"Palm Tungsten|E aka. Cheetah PDA (OMAP310)\";\n>> mc->init = palmte_init;\n>> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"ti925t\");\n>> }\n>>\n>> DEFINE_MACHINE(\"cheetah\", palmte_machine_init)\n>> diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c\n>> index c16657d..79b317a 100644\n>> --- a/hw/arm/pxa2xx.c\n>> +++ b/hw/arm/pxa2xx.c\n>> @@ -2052,21 +2052,19 @@ static void pxa2xx_reset(void *opaque, int line, int level)\n>>\n>> /* Initialise a PXA270 integrated chip (ARM based core). */\n>> PXA2xxState *pxa270_init(MemoryRegion *address_space,\n>> - unsigned int sdram_size, const char *revision)\n>> + unsigned int sdram_size, const char *cpu_type)\n>> {\n>> PXA2xxState *s;\n>> int i;\n>> DriveInfo *dinfo;\n>> s = g_new0(PXA2xxState, 1);\n>>\n>> - if (revision && strncmp(revision, \"pxa27\", 5)) {\n>> + if (strncmp(cpu_type, ARM_CPU_TYPE_NAME(\"pxa27\"), 5)) {\n>\n> Why are you using ARM_CPU_TYPE_NAME here, if you are only\n> checking if cpu_type starts with \"pxa27\"?\n>\n> I suggest adding a TODO here noting that we implement this using\n> either a TYPE_ARM_PXA27 subclass (so we can use\n> object_class_dynamic_cast()), or a ARMCPUClass field to identify\n> if the CPU is pxa27.\n>\n>> fprintf(stderr, \"Machine requires a PXA27x processor.\\n\");\n>> exit(1);\n>> }\n>\n> This would be another use case for a generic CPU model validation\n> mechanism in MachineClass.\n>\n>\n>> - if (!revision)\n>> - revision = \"pxa270\";\n>>\n>> - s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, revision));\n>> + s->cpu = ARM_CPU(cpu_create(cpu_type));\n>> s->reset = qemu_allocate_irq(pxa2xx_reset, s, 0);\n>>\n>> /* SDRAM & Internal Memory Storage */\n>> @@ -2192,7 +2190,7 @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)\n>>\n>> s = g_new0(PXA2xxState, 1);\n>>\n>> - s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, \"pxa255\"));\n>> + s->cpu = ARM_CPU(cpu_create(ARM_CPU_TYPE_NAME(\"pxa255\")));\n>> s->reset = qemu_allocate_irq(pxa2xx_reset, s, 0);\n>>\n>> /* SDRAM & Internal Memory Storage */\n>> diff --git a/hw/arm/realview.c b/hw/arm/realview.c\n>> index 76ff557..38e3278 100644\n>> --- a/hw/arm/realview.c\n>> +++ b/hw/arm/realview.c\n>> @@ -55,7 +55,6 @@ static void realview_init(MachineState *machine,\n>> {\n>> ARMCPU *cpu = NULL;\n>> CPUARMState *env;\n>> - ObjectClass *cpu_oc;\n>> MemoryRegion *sysmem = get_system_memory();\n>> MemoryRegion *ram_lo;\n>> MemoryRegion *ram_hi = g_new(MemoryRegion, 1);\n>> @@ -96,14 +95,8 @@ static void realview_init(MachineState *machine,\n>> break;\n>> }\n>>\n>> - cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, machine->cpu_model);\n>> - if (!cpu_oc) {\n>> - fprintf(stderr, \"Unable to find CPU definition\\n\");\n>> - exit(1);\n>> - }\n>> -\n>> for (n = 0; n < smp_cpus; n++) {\n>> - Object *cpuobj = object_new(object_class_get_name(cpu_oc));\n>> + Object *cpuobj = object_new(machine->cpu_type);\n>>\n>> /* By default A9,A15 and ARM1176 CPUs have EL3 enabled. This board\n>> * does not currently support EL3 so the CPU EL3 property is disabled\n>> @@ -359,33 +352,21 @@ static void realview_init(MachineState *machine,\n>>\n>> static void realview_eb_init(MachineState *machine)\n>> {\n>> - if (!machine->cpu_model) {\n>> - machine->cpu_model = \"arm926\";\n>> - }\n>> realview_init(machine, BOARD_EB);\n>> }\n>>\n>> static void realview_eb_mpcore_init(MachineState *machine)\n>> {\n>> - if (!machine->cpu_model) {\n>> - machine->cpu_model = \"arm11mpcore\";\n>> - }\n>> realview_init(machine, BOARD_EB_MPCORE);\n>> }\n>>\n>> static void realview_pb_a8_init(MachineState *machine)\n>> {\n>> - if (!machine->cpu_model) {\n>> - machine->cpu_model = \"cortex-a8\";\n>> - }\n>> realview_init(machine, BOARD_PB_A8);\n>> }\n>>\n>> static void realview_pbx_a9_init(MachineState *machine)\n>> {\n>> - if (!machine->cpu_model) {\n>> - machine->cpu_model = \"cortex-a9\";\n>> - }\n>> realview_init(machine, BOARD_PBX_A9);\n>> }\n>>\n>> @@ -396,6 +377,7 @@ static void realview_eb_class_init(ObjectClass *oc, void *data)\n>> mc->desc = \"ARM RealView Emulation Baseboard (ARM926EJ-S)\";\n>> mc->init = realview_eb_init;\n>> mc->block_default_type = IF_SCSI;\n>> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"arm926\");\n>> }\n>>\n>> static const TypeInfo realview_eb_type = {\n>> @@ -412,6 +394,7 @@ static void realview_eb_mpcore_class_init(ObjectClass *oc, void *data)\n>> mc->init = realview_eb_mpcore_init;\n>> mc->block_default_type = IF_SCSI;\n>> mc->max_cpus = 4;\n>> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"arm11mpcore\");\n>> }\n>>\n>> static const TypeInfo realview_eb_mpcore_type = {\n>> @@ -426,6 +409,7 @@ static void realview_pb_a8_class_init(ObjectClass *oc, void *data)\n>>\n>> mc->desc = \"ARM RealView Platform Baseboard for Cortex-A8\";\n>> mc->init = realview_pb_a8_init;\n>> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"cortex-a8\");\n>> }\n>>\n>> static const TypeInfo realview_pb_a8_type = {\n>> @@ -441,6 +425,7 @@ static void realview_pbx_a9_class_init(ObjectClass *oc, void *data)\n>> mc->desc = \"ARM RealView Platform Baseboard Explore for Cortex-A9\";\n>> mc->init = realview_pbx_a9_init;\n>> mc->max_cpus = 4;\n>> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"cortex-a9\");\n>> }\n>>\n>> static const TypeInfo realview_pbx_a9_type = {\n>> diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c\n>> index 7f588ce..b6ddb7c 100644\n>> --- a/hw/arm/spitz.c\n>> +++ b/hw/arm/spitz.c\n>> @@ -30,6 +30,7 @@\n>> #include \"hw/sysbus.h\"\n>> #include \"exec/address-spaces.h\"\n>> #include \"sysemu/sysemu.h\"\n>> +#include \"cpu.h\"\n>>\n>> #undef REG_FMT\n>> #define REG_FMT \"0x%02lx\"\n>> @@ -909,13 +910,10 @@ static void spitz_common_init(MachineState *machine,\n>> DeviceState *scp0, *scp1 = NULL;\n>> MemoryRegion *address_space_mem = get_system_memory();\n>> MemoryRegion *rom = g_new(MemoryRegion, 1);\n>> - const char *cpu_model = machine->cpu_model;\n>> -\n>> - if (!cpu_model)\n>> - cpu_model = (model == terrier) ? \"pxa270-c5\" : \"pxa270-c0\";\n>>\n>\n> Nice to see this go away.\n>\n>\n>> /* Setup CPU & memory */\n>> - mpu = pxa270_init(address_space_mem, spitz_binfo.ram_size, cpu_model);\n>> + mpu = pxa270_init(address_space_mem, spitz_binfo.ram_size,\n>> + machine->cpu_type);\n>>\n>> sl_flash_register(mpu, (model == spitz) ? FLASH_128M : FLASH_1024M);\n>>\n>> @@ -983,6 +981,7 @@ static void akitapda_class_init(ObjectClass *oc, void *data)\n>>\n>> mc->desc = \"Sharp SL-C1000 (Akita) PDA (PXA270)\";\n>> mc->init = akita_init;\n>> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"pxa270-c0\");\n>> }\n>>\n>> static const TypeInfo akitapda_type = {\n>> @@ -998,6 +997,7 @@ static void spitzpda_class_init(ObjectClass *oc, void *data)\n>> mc->desc = \"Sharp SL-C3000 (Spitz) PDA (PXA270)\";\n>> mc->init = spitz_init;\n>> mc->block_default_type = IF_IDE;\n>> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"pxa270-c0\");\n>> }\n>>\n>> static const TypeInfo spitzpda_type = {\n>> @@ -1013,6 +1013,7 @@ static void borzoipda_class_init(ObjectClass *oc, void *data)\n>> mc->desc = \"Sharp SL-C3100 (Borzoi) PDA (PXA270)\";\n>> mc->init = borzoi_init;\n>> mc->block_default_type = IF_IDE;\n>> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"pxa270-c0\");\n>> }\n>>\n>> static const TypeInfo borzoipda_type = {\n>> @@ -1028,6 +1029,7 @@ static void terrierpda_class_init(ObjectClass *oc, void *data)\n>> mc->desc = \"Sharp SL-C3200 (Terrier) PDA (PXA270)\";\n>> mc->init = terrier_init;\n>> mc->block_default_type = IF_IDE;\n>> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"pxa270-c5\");\n>> }\n>>\n>> static const TypeInfo terrierpda_type = {\n>> diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c\n>> index 408c1a1..c8fa9da 100644\n>> --- a/hw/arm/stellaris.c\n>> +++ b/hw/arm/stellaris.c\n>> @@ -22,6 +22,7 @@\n>> #include \"sysemu/sysemu.h\"\n>> #include \"hw/char/pl011.h\"\n>> #include \"hw/misc/unimp.h\"\n>> +#include \"cpu.h\"\n>>\n>> #define GPIO_A 0\n>> #define GPIO_B 1\n>> @@ -1225,8 +1226,7 @@ static stellaris_board_info stellaris_boards[] = {\n>> }\n>> };\n>>\n>> -static void stellaris_init(const char *kernel_filename, const char *cpu_model,\n>> - stellaris_board_info *board)\n>> +static void stellaris_init(MachineState *ms, stellaris_board_info *board)\n>> {\n>> static const int uart_irq[] = {5, 6, 33, 34};\n>> static const int timer_irq[] = {19, 21, 23, 35};\n>> @@ -1298,7 +1298,7 @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model,\n>> memory_region_add_subregion(system_memory, 0x20000000, sram);\n>>\n>> nvic = armv7m_init(system_memory, flash_size, NUM_IRQ_LINES,\n>> - kernel_filename, cpu_model);\n>> + ms->kernel_filename, ms->cpu_type);\n>>\n>> qdev_connect_gpio_out_named(nvic, \"SYSRESETREQ\", 0,\n>> qemu_allocate_irq(&do_sys_reset, NULL, 0));\n>> @@ -1435,16 +1435,12 @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model,\n>> /* FIXME: Figure out how to generate these from stellaris_boards. */\n>> static void lm3s811evb_init(MachineState *machine)\n>> {\n>> - const char *cpu_model = machine->cpu_model;\n>> - const char *kernel_filename = machine->kernel_filename;\n>> - stellaris_init(kernel_filename, cpu_model, &stellaris_boards[0]);\n>> + stellaris_init(machine, &stellaris_boards[0]);\n>> }\n>>\n>> static void lm3s6965evb_init(MachineState *machine)\n>> {\n>> - const char *cpu_model = machine->cpu_model;\n>> - const char *kernel_filename = machine->kernel_filename;\n>> - stellaris_init(kernel_filename, cpu_model, &stellaris_boards[1]);\n>> + stellaris_init(machine, &stellaris_boards[1]);\n>> }\n>>\n>> static void lm3s811evb_class_init(ObjectClass *oc, void *data)\n>> @@ -1453,6 +1449,7 @@ static void lm3s811evb_class_init(ObjectClass *oc, void *data)\n>>\n>>\n\n...\n\n>>\n>> static const TypeInfo lm3s6965evb_type = {\n>> diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c\n>> index f61e735..1cd6374 100644\n>> --- a/hw/arm/stm32f205_soc.c\n>> +++ b/hw/arm/stm32f205_soc.c\n>> @@ -112,7 +112,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)\n>>\n>> armv7m = DEVICE(&s->armv7m);\n>> qdev_prop_set_uint32(armv7m, \"num-irq\", 96);\n>> - qdev_prop_set_string(armv7m, \"cpu-model\", s->cpu_model);\n>> + qdev_prop_set_string(armv7m, \"cpu-type\", s->cpu_type);\n>> object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),\n>> \"memory\", &error_abort);\n>> object_property_set_bool(OBJECT(&s->armv7m), true, \"realized\", &err);\n>> @@ -200,7 +200,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)\n>> }\n>>\n>> static Property stm32f205_soc_properties[] = {\n>> - DEFINE_PROP_STRING(\"cpu-model\", STM32F205State, cpu_model),\n>> + DEFINE_PROP_STRING(\"cpu-type\", STM32F205State, cpu_type),\n>\n> Same as armv7m: are we 100% sure users are not setting this\n> manually?\n\nIn an embedded board like this it really doesn't make sense to let the\nuser overwrite the CPU. The SoC will take it as an option, but the\nboard (which creates the SoC) just blindly always uses the same CPU.\nThat feature is more for QOMificatoion then any real reason though.\n\nIn saying that I think a warning if the user tries to set the CPU\nwould make sense. I know that this issues comes up in other ARM boards\n(Zynq-7000 has the same issue as well) so maybe a machine property\nsaying that the board doesn't accept custom CPUs would be a good idea.\n\nOverall I think this patch is moving in the right direction though and\nthis CPU option being ignored existed before this series.\n\nThanks,\nAlistair\n\n\n>\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"dWhMbjvk\"; dkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xn0jG56Hlz9s7f\n\tfor ;\n\tWed, 6 Sep 2017 07:49:05 +1000 (AEST)","from localhost ([::1]:33307 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dpLiQ-0007L5-IQ\n\tfor incoming@patchwork.ozlabs.org; Tue, 05 Sep 2017 17:49:02 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:37793)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1dpLhx-0007KY-Di\n\tfor qemu-devel@nongnu.org; Tue, 05 Sep 2017 17:48:41 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1dpLhp-0001zu-7k\n\tfor qemu-devel@nongnu.org; Tue, 05 Sep 2017 17:48:33 -0400","from mail-wr0-x244.google.com ([2a00:1450:400c:c0c::244]:33914)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from )\n\tid 1dpLho-0001yt-Oq; Tue, 05 Sep 2017 17:48:25 -0400","by mail-wr0-x244.google.com with SMTP id k20so567876wre.1;\n\tTue, 05 Sep 2017 14:48:24 -0700 (PDT)","by 10.28.191.130 with HTTP; Tue, 5 Sep 2017 14:47:52 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=mime-version:in-reply-to:references:from:date:message-id:subject:to\n\t:cc; bh=y7G9zO7SSJm5qFMf9yvjSTlaz9aeuL3OQ1AXQFOcvSE=;\n\tb=dWhMbjvkHMhk73wmsWARD8bjXH94aNbp6yil1e/e+RANGq6dR1Go85UGV2A/prKMaM\n\tnGFAFRKr1F5NcvWxTmj5BgGNdGnzAX+vsK6KDvQ9slF9XH+8vwRd98sRkM7yme5eq5S1\n\tEOVgbHJ4IhsumJlTw6WVss15e/LcnUUr9l8sz+nTwsp5YoEVdQnK4feHEWGaMkuzDDtX\n\tWJ3kDjyOaVjzk62m3bdqizM+QAsHZ4gTs6mXvcFbNlrMvaaVAticoYybEmUju8FR5Ln3\n\t0BsfIcVonakp/lnjTjZVavH3w/rD72XT/8eQLh0xlBWtwIrJbwezdWuzgVxaO2xyDb81\n\trV0A==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:mime-version:in-reply-to:references:from:date\n\t:message-id:subject:to:cc;\n\tbh=y7G9zO7SSJm5qFMf9yvjSTlaz9aeuL3OQ1AXQFOcvSE=;\n\tb=N7NnMaBknS9mRannJ5FdHpnRT0ngQl6kbp8MW2PdZBlsAqgkoXUvKNCjLIubcFw9HZ\n\tWwZS6KXNCM7AmRzg+ZqeG56Ac+egqm6JOPCEzbBojKHugvSYRx9gcShDh9QLNrkBtcqP\n\tfz9UN28TIwM0J7W92nLlJeFVlEBi3SW0zggm4HRDY65myILD97GIktVSM81P9rm0nAiY\n\tBgDPtAHTAYybH/TMy0xDbCqKBA1bE6+dYYezlb1ksk44gIQA93KFxbLSHhyRa+bHl6nZ\n\tOSXyOYIYt1P2xYsUntYub2Ytg2fhpK0skAV8UaY9r8RHnOxXSf+a6byi+0W4Rm0NQ/0f\n\tchFA==","X-Gm-Message-State":"AHPjjUgjOZQHeDHS2UJzDZmN7dXbxlhxCAyiZqUnHqhsdphcXroKZmRL\n\tZQ4/9IBhnOkuqfFbAukNMUES85g30Q==","X-Google-Smtp-Source":"ADKCNb4TWkhYAGpYGmb1YeZeb47EukavPs4vqkuQ6UCikSwDAsfrV5gOxMIrQCLTkxmC7dPIa8E1OQJ4tIiSORZBYog=","X-Received":"by 10.223.175.100 with SMTP id z91mr265998wrc.177.1504648103280; \n\tTue, 05 Sep 2017 14:48:23 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"<20170905213152.GG17184@localhost.localdomain>","References":"<1504533662-198084-1-git-send-email-imammedo@redhat.com>\n\t<1504533662-198084-7-git-send-email-imammedo@redhat.com>\n\t<20170905213152.GG17184@localhost.localdomain>","From":"Alistair Francis ","Date":"Tue, 5 Sep 2017 14:47:52 -0700","Message-ID":"","To":"Eduardo Habkost ","Content-Type":"text/plain; charset=\"UTF-8\"","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2a00:1450:400c:c0c::244","Subject":"Re: [Qemu-devel] [PATCH 6/6] arm: drop intermadiate cpu_model ->\n\tcpu type parsing and use cpu type directly","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Rob Herring , Andrew Jones ,\n\tPeter Maydell ,\n\tIgor Mitsyanko ,\n\tAlistair Francis ,\n\t\"qemu-devel@nongnu.org Developers\" ,\n\tqemu-arm , Jan Kiszka ,\n\t\"Edgar E. Iglesias\" ,\n\tIgor Mammedov , Richard Henderson ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1763699,"web_url":"http://patchwork.ozlabs.org/comment/1763699/","msgid":"<20170905221226.GZ7570@localhost.localdomain>","list_archive_url":null,"date":"2017-09-05T22:12:26","subject":"Re: [Qemu-devel] [PATCH 6/6] arm: drop intermadiate cpu_model ->\n\tcpu type parsing and use cpu type directly","submitter":{"id":195,"url":"http://patchwork.ozlabs.org/api/people/195/","name":"Eduardo Habkost","email":"ehabkost@redhat.com"},"content":"On Tue, Sep 05, 2017 at 02:47:52PM -0700, Alistair Francis wrote:\n> On Tue, Sep 5, 2017 at 2:31 PM, Eduardo Habkost wrote:\n[...]\n> >> diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c\n> >> index f61e735..1cd6374 100644\n> >> --- a/hw/arm/stm32f205_soc.c\n> >> +++ b/hw/arm/stm32f205_soc.c\n> >> @@ -112,7 +112,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)\n> >>\n> >> armv7m = DEVICE(&s->armv7m);\n> >> qdev_prop_set_uint32(armv7m, \"num-irq\", 96);\n> >> - qdev_prop_set_string(armv7m, \"cpu-model\", s->cpu_model);\n> >> + qdev_prop_set_string(armv7m, \"cpu-type\", s->cpu_type);\n> >> object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),\n> >> \"memory\", &error_abort);\n> >> object_property_set_bool(OBJECT(&s->armv7m), true, \"realized\", &err);\n> >> @@ -200,7 +200,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)\n> >> }\n> >>\n> >> static Property stm32f205_soc_properties[] = {\n> >> - DEFINE_PROP_STRING(\"cpu-model\", STM32F205State, cpu_model),\n> >> + DEFINE_PROP_STRING(\"cpu-type\", STM32F205State, cpu_type),\n> >\n> > Same as armv7m: are we 100% sure users are not setting this\n> > manually?\n> \n> In an embedded board like this it really doesn't make sense to let the\n> user overwrite the CPU. The SoC will take it as an option, but the\n> board (which creates the SoC) just blindly always uses the same CPU.\n> That feature is more for QOMificatoion then any real reason though.\n> \n\nI'm not talking about -cpu (no user-visible change in the\nhandling of -cpu should result from this patch), but about\npossible cases where the user set the \"cpu-model\" property using\nanother mechanism, like -global. Probably it's impossible for an\nuser to override the property successfully, but I would like to\nbe sure.\n\n\n> In saying that I think a warning if the user tries to set the CPU\n> would make sense. I know that this issues comes up in other ARM boards\n> (Zynq-7000 has the same issue as well) so maybe a machine property\n> saying that the board doesn't accept custom CPUs would be a good idea.\n\nYeah, there are multiple cases in this patch where boards are\nvalidating the CPU model, but not all boards do that. A generic\nMachineClass::valid_cpu_types[] field would be useful.\n\n> \n> Overall I think this patch is moving in the right direction though and\n> this CPU option being ignored existed before this series.\n\nI agree this is going on the right direction. However, I don't\nsee any board that ignore the CPU option: all of them seem to use\ncpu_model when creating the CPUs, already.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ext-mx01.extmail.prod.ext.phx2.redhat.com;\n\tdmarc=none (p=none dis=none) header.from=redhat.com","ext-mx01.extmail.prod.ext.phx2.redhat.com;\n\tspf=fail smtp.mailfrom=ehabkost@redhat.com"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xn1FK1TNxz9s83\n\tfor ;\n\tWed, 6 Sep 2017 08:13:24 +1000 (AEST)","from localhost ([::1]:33376 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dpM5x-00008N-Ka\n\tfor incoming@patchwork.ozlabs.org; Tue, 05 Sep 2017 18:13:21 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:46501)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1dpM5S-00007q-I5\n\tfor qemu-devel@nongnu.org; Tue, 05 Sep 2017 18:12:55 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1dpM5H-00089k-M9\n\tfor qemu-devel@nongnu.org; Tue, 05 Sep 2017 18:12:44 -0400","from mx1.redhat.com ([209.132.183.28]:56672)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1dpM57-000856-Mp; Tue, 05 Sep 2017 18:12:29 -0400","from smtp.corp.redhat.com\n\t(int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby mx1.redhat.com (Postfix) with ESMTPS id 8575E7F6BA;\n\tTue, 5 Sep 2017 22:12:28 +0000 (UTC)","from localhost (ovpn-116-45.gru2.redhat.com [10.97.116.45])\n\tby smtp.corp.redhat.com (Postfix) with ESMTP id ECEA5619CB;\n\tTue, 5 Sep 2017 22:12:27 +0000 (UTC)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mx1.redhat.com 8575E7F6BA","Date":"Tue, 5 Sep 2017 19:12:26 -0300","From":"Eduardo Habkost ","To":"Alistair Francis ","Message-ID":"<20170905221226.GZ7570@localhost.localdomain>","References":"<1504533662-198084-1-git-send-email-imammedo@redhat.com>\n\t<1504533662-198084-7-git-send-email-imammedo@redhat.com>\n\t<20170905213152.GG17184@localhost.localdomain>\n\t","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"","X-Fnord":"you can see the fnord","User-Agent":"Mutt/1.8.3 (2017-05-23)","X-Scanned-By":"MIMEDefang 2.79 on 10.5.11.12","X-Greylist":"Sender IP whitelisted, not delayed by milter-greylist-4.5.16\n\t(mx1.redhat.com [10.5.110.25]);\n\tTue, 05 Sep 2017 22:12:28 +0000 (UTC)","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]","X-Received-From":"209.132.183.28","Subject":"Re: [Qemu-devel] [PATCH 6/6] arm: drop intermadiate cpu_model ->\n\tcpu type parsing and use cpu type directly","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Rob Herring , Andrew Jones ,\n\tPeter Maydell ,\n\tIgor Mitsyanko ,\n\tAlistair Francis ,\n\t\"qemu-devel@nongnu.org Developers\" ,\n\tqemu-arm , Jan Kiszka ,\n\t\"Edgar E. Iglesias\" ,\n\tIgor Mammedov , Richard Henderson ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1763717,"web_url":"http://patchwork.ozlabs.org/comment/1763717/","msgid":"","list_archive_url":null,"date":"2017-09-05T22:46:07","subject":"Re: [Qemu-devel] [PATCH 6/6] arm: drop intermadiate cpu_model ->\n\tcpu type parsing and use cpu type directly","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/people/64571/","name":"Alistair Francis","email":"alistair23@gmail.com"},"content":"On Tue, Sep 5, 2017 at 3:12 PM, Eduardo Habkost wrote:\n> On Tue, Sep 05, 2017 at 02:47:52PM -0700, Alistair Francis wrote:\n>> On Tue, Sep 5, 2017 at 2:31 PM, Eduardo Habkost wrote:\n> [...]\n>> >> diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c\n>> >> index f61e735..1cd6374 100644\n>> >> --- a/hw/arm/stm32f205_soc.c\n>> >> +++ b/hw/arm/stm32f205_soc.c\n>> >> @@ -112,7 +112,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)\n>> >>\n>> >> armv7m = DEVICE(&s->armv7m);\n>> >> qdev_prop_set_uint32(armv7m, \"num-irq\", 96);\n>> >> - qdev_prop_set_string(armv7m, \"cpu-model\", s->cpu_model);\n>> >> + qdev_prop_set_string(armv7m, \"cpu-type\", s->cpu_type);\n>> >> object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),\n>> >> \"memory\", &error_abort);\n>> >> object_property_set_bool(OBJECT(&s->armv7m), true, \"realized\", &err);\n>> >> @@ -200,7 +200,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)\n>> >> }\n>> >>\n>> >> static Property stm32f205_soc_properties[] = {\n>> >> - DEFINE_PROP_STRING(\"cpu-model\", STM32F205State, cpu_model),\n>> >> + DEFINE_PROP_STRING(\"cpu-type\", STM32F205State, cpu_type),\n>> >\n>> > Same as armv7m: are we 100% sure users are not setting this\n>> > manually?\n>>\n>> In an embedded board like this it really doesn't make sense to let the\n>> user overwrite the CPU. The SoC will take it as an option, but the\n>> board (which creates the SoC) just blindly always uses the same CPU.\n>> That feature is more for QOMificatoion then any real reason though.\n>>\n>\n> I'm not talking about -cpu (no user-visible change in the\n> handling of -cpu should result from this patch), but about\n> possible cases where the user set the \"cpu-model\" property using\n> another mechanism, like -global. Probably it's impossible for an\n> user to override the property successfully, but I would like to\n> be sure.\n\nAh, that is trickier.\n\nI guess that is possible to do, but the object setting logic should\nhandle the error gracefully and inform the user of the error.\n\n>\n>\n>> In saying that I think a warning if the user tries to set the CPU\n>> would make sense. I know that this issues comes up in other ARM boards\n>> (Zynq-7000 has the same issue as well) so maybe a machine property\n>> saying that the board doesn't accept custom CPUs would be a good idea.\n>\n> Yeah, there are multiple cases in this patch where boards are\n> validating the CPU model, but not all boards do that. A generic\n> MachineClass::valid_cpu_types[] field would be useful.\n>\n>>\n>> Overall I think this patch is moving in the right direction though and\n>> this CPU option being ignored existed before this series.\n>\n> I agree this is going on the right direction. However, I don't\n> see any board that ignore the CPU option: all of them seem to use\n> cpu_model when creating the CPUs, already.\n\nThe Netduino2 will ignore any CPU options and always use a Cortex-m3.\nI was wrong about Zynq-7000 though, it does respect the -cpu option.\n\nThanks,\nAlistair\n\n>\n> --\n> Eduardo","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"rEkykBJL\"; dkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xn20l1q9Rz9sRm\n\tfor ;\n\tWed, 6 Sep 2017 08:47:35 +1000 (AEST)","from localhost ([::1]:33431 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dpMd3-0008An-Cj\n\tfor incoming@patchwork.ozlabs.org; Tue, 05 Sep 2017 18:47:33 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:58649)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1dpMcG-000888-RE\n\tfor qemu-devel@nongnu.org; Tue, 05 Sep 2017 18:46:49 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1dpMcC-0000St-2M\n\tfor qemu-devel@nongnu.org; Tue, 05 Sep 2017 18:46:44 -0400","from mail-wm0-x241.google.com ([2a00:1450:400c:c09::241]:37070)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from )\n\tid 1dpMcB-0000SD-Qe; Tue, 05 Sep 2017 18:46:39 -0400","by mail-wm0-x241.google.com with SMTP id f4so1547766wmh.4;\n\tTue, 05 Sep 2017 15:46:39 -0700 (PDT)","by 10.28.191.130 with HTTP; Tue, 5 Sep 2017 15:46:07 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=mime-version:in-reply-to:references:from:date:message-id:subject:to\n\t:cc; bh=PS1GBt5xcNZRGt/Lby26+iIpROCk/DHeENsq9976e+Q=;\n\tb=rEkykBJLLJHhkAnqFU4ULxz5pAItp3KPapTs6/4lLU2u21JoXW+Rg0NGxs6XWhbvdr\n\tkRaBAPqq3/Xc81D9zPRfz05YoJeLfZiRc5rBvqqSCW29LGA+IzM0FekffzOgiOnIvUxB\n\tB8oujAIGxM6KVPbngpOY4OHITIC1ACSEwYhrjXcqGdWXza3N+BXCLPdYAQsRRaEXrGsi\n\t8KVaDNGQhKnqY63tF8z3rU9n6MjN4isQmLBsuutJuLsnwUnauBzmOnl36jPkHixuB5ky\n\tdW3HIm/WTLTjrTQ2SS0Rb4vZbg9NaH9l7L8SiUU4Dzv71Jl+kueQT2gRZFLxuKSrGL3P\n\txxCA==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:mime-version:in-reply-to:references:from:date\n\t:message-id:subject:to:cc;\n\tbh=PS1GBt5xcNZRGt/Lby26+iIpROCk/DHeENsq9976e+Q=;\n\tb=bEJJwg3SwmUhdMmaTer28QZsm/+/++RHUv0NEjxNdfw3xKsKPX87uLF8fkZVS7nnFa\n\tWX2WhHlTyo+3tgF87hDP6KMNH9mp9s0NkRXqMwAbEBA0uqYRIxRptQDvcs1AzQKuXKWt\n\tD2BJTjBZO0QdAMGmzW27VbDmMEm+xmUTRhGGp5UVzdMTO8L+Z0Sb1SSnW+95SdbWzN/P\n\tkHh2ATdazGwOgLcRt+66k/o4m+J60gFzJWONuYmk+Ma7MJxG6ABsXrGAwS8VY0tYvODZ\n\ttqBWpHyuDHUyTTvRXapXWszq3YaqDSjPnxyuyY1FBNEK7bY2wrgf+i4tOzlZ+NmtMa7m\n\t1OYQ==","X-Gm-Message-State":"AHPjjUg3IOD38xoJHAFInWW7wrQlPnAnP5Jq1lpqxqbN3n2pBhssV0qF\n\toQ6H/9DydwvrxdbLrw+Yf6CjUTGZ/A==","X-Google-Smtp-Source":"ADKCNb6jjDtyLIdwSYq68RkY7W+Yrb3zHWJShGFSC1WLBalxZezhGBd4RjZfIgo0g9jdFrAcukrY2OACwPlVC7anry4=","X-Received":"by 10.28.196.202 with SMTP id u193mr276403wmf.120.1504651598467; \n\tTue, 05 Sep 2017 15:46:38 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"<20170905221226.GZ7570@localhost.localdomain>","References":"<1504533662-198084-1-git-send-email-imammedo@redhat.com>\n\t<1504533662-198084-7-git-send-email-imammedo@redhat.com>\n\t<20170905213152.GG17184@localhost.localdomain>\n\t\n\t<20170905221226.GZ7570@localhost.localdomain>","From":"Alistair Francis ","Date":"Tue, 5 Sep 2017 15:46:07 -0700","Message-ID":"","To":"Eduardo Habkost ","Content-Type":"text/plain; charset=\"UTF-8\"","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2a00:1450:400c:c09::241","Subject":"Re: [Qemu-devel] [PATCH 6/6] arm: drop intermadiate cpu_model ->\n\tcpu type parsing and use cpu type directly","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Rob Herring , Andrew Jones ,\n\tPeter Maydell ,\n\tIgor Mitsyanko ,\n\tAlistair Francis ,\n\t\"qemu-devel@nongnu.org Developers\" ,\n\tqemu-arm , Jan Kiszka ,\n\t\"Edgar E. Iglesias\" ,\n\tIgor Mammedov , Richard Henderson ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1763735,"web_url":"http://patchwork.ozlabs.org/comment/1763735/","msgid":"","list_archive_url":null,"date":"2017-09-06T00:16:09","subject":"Re: [Qemu-devel] [PATCH 6/6] arm: drop intermadiate cpu_model ->\n\tcpu type parsing and use cpu type directly","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/people/64571/","name":"Alistair Francis","email":"alistair23@gmail.com"},"content":"On Tue, Sep 5, 2017 at 3:46 PM, Alistair Francis wrote:\n> On Tue, Sep 5, 2017 at 3:12 PM, Eduardo Habkost wrote:\n>> On Tue, Sep 05, 2017 at 02:47:52PM -0700, Alistair Francis wrote:\n>>> On Tue, Sep 5, 2017 at 2:31 PM, Eduardo Habkost wrote:\n>> [...]\n>>> >> diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c\n>>> >> index f61e735..1cd6374 100644\n>>> >> --- a/hw/arm/stm32f205_soc.c\n>>> >> +++ b/hw/arm/stm32f205_soc.c\n>>> >> @@ -112,7 +112,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)\n>>> >>\n>>> >> armv7m = DEVICE(&s->armv7m);\n>>> >> qdev_prop_set_uint32(armv7m, \"num-irq\", 96);\n>>> >> - qdev_prop_set_string(armv7m, \"cpu-model\", s->cpu_model);\n>>> >> + qdev_prop_set_string(armv7m, \"cpu-type\", s->cpu_type);\n>>> >> object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),\n>>> >> \"memory\", &error_abort);\n>>> >> object_property_set_bool(OBJECT(&s->armv7m), true, \"realized\", &err);\n>>> >> @@ -200,7 +200,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)\n>>> >> }\n>>> >>\n>>> >> static Property stm32f205_soc_properties[] = {\n>>> >> - DEFINE_PROP_STRING(\"cpu-model\", STM32F205State, cpu_model),\n>>> >> + DEFINE_PROP_STRING(\"cpu-type\", STM32F205State, cpu_type),\n>>> >\n>>> > Same as armv7m: are we 100% sure users are not setting this\n>>> > manually?\n>>>\n>>> In an embedded board like this it really doesn't make sense to let the\n>>> user overwrite the CPU. The SoC will take it as an option, but the\n>>> board (which creates the SoC) just blindly always uses the same CPU.\n>>> That feature is more for QOMificatoion then any real reason though.\n>>>\n>>\n>> I'm not talking about -cpu (no user-visible change in the\n>> handling of -cpu should result from this patch), but about\n>> possible cases where the user set the \"cpu-model\" property using\n>> another mechanism, like -global. Probably it's impossible for an\n>> user to override the property successfully, but I would like to\n>> be sure.\n>\n> Ah, that is trickier.\n>\n> I guess that is possible to do, but the object setting logic should\n> handle the error gracefully and inform the user of the error.\n>\n>>\n>>\n>>> In saying that I think a warning if the user tries to set the CPU\n>>> would make sense. I know that this issues comes up in other ARM boards\n>>> (Zynq-7000 has the same issue as well) so maybe a machine property\n>>> saying that the board doesn't accept custom CPUs would be a good idea.\n>>\n>> Yeah, there are multiple cases in this patch where boards are\n>> validating the CPU model, but not all boards do that. A generic\n>> MachineClass::valid_cpu_types[] field would be useful.\n\nI just sent a RFC out that does this, let me know what you think.\n\nThe cover letter is called: \"Add a valid_cpu_types property\"\n\nThanks,\nAlistair\n\n>>\n>>>\n>>> Overall I think this patch is moving in the right direction though and\n>>> this CPU option being ignored existed before this series.\n>>\n>> I agree this is going on the right direction. However, I don't\n>> see any board that ignore the CPU option: all of them seem to use\n>> cpu_model when creating the CPUs, already.\n>\n> The Netduino2 will ignore any CPU options and always use a Cortex-m3.\n> I was wrong about Zynq-7000 though, it does respect the -cpu option.\n>\n> Thanks,\n> Alistair\n>\n>>\n>> --\n>> Eduardo","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"BMK32VYB\"; dkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xn4256vjKz9t2y\n\tfor ;\n\tWed, 6 Sep 2017 10:18:53 +1000 (AEST)","from localhost ([::1]:33617 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dpO3Q-0000ly-2Z\n\tfor incoming@patchwork.ozlabs.org; Tue, 05 Sep 2017 20:18:52 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:49266)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1dpO1O-0007sg-4U\n\tfor qemu-devel@nongnu.org; Tue, 05 Sep 2017 20:16:52 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1dpO1J-0000ik-Bt\n\tfor qemu-devel@nongnu.org; Tue, 05 Sep 2017 20:16:46 -0400","from mail-wm0-x22d.google.com ([2a00:1450:400c:c09::22d]:36617)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from )\n\tid 1dpO1J-0000ho-4h; Tue, 05 Sep 2017 20:16:41 -0400","by mail-wm0-x22d.google.com with SMTP id i145so24401201wmf.1;\n\tTue, 05 Sep 2017 17:16:41 -0700 (PDT)","by 10.28.191.130 with HTTP; Tue, 5 Sep 2017 17:16:09 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=mime-version:in-reply-to:references:from:date:message-id:subject:to\n\t:cc; bh=+U5jhKTdK6gyCjbjpktaBeH6RLJCs42ukWE5sLh8ag0=;\n\tb=BMK32VYBarJUjj+9mPblmHRwL5lGtIJD1M+pHB1i79ajs8T0xzzqrfuL5Tlg2FuLQ1\n\t0iwU62w6LHYUicu50Dk0SMEev3ionrrij4pJ28U3NA7VipBEQkln5lvuhDpr+i9Q1Bf0\n\tto0OEh7lhiKVNCAAE3c8E1tWbDH1Pm8Uask/4kCHMHlie9vQbYS5Q7lCRc8Tx8nVn2Gk\n\tyLbMSInizA+Tq52cZuYltZLtPfLGD7tcR65UEBuO+brBxU3fBTsFeqJBn42U9EOXjk/V\n\t7S2ApF78BvZQOzoJqBkl0GumT60MajVg6zTVa2uZxSkZDoicASNOaPoJDrS2X2drS8iA\n\tBreg==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:mime-version:in-reply-to:references:from:date\n\t:message-id:subject:to:cc;\n\tbh=+U5jhKTdK6gyCjbjpktaBeH6RLJCs42ukWE5sLh8ag0=;\n\tb=h9M7JMKXQkHq4p++Y0xS4APQIBElAPliZO4vr1A7geOhvxL8j1FFDILKCcirMLEilt\n\t3uD0iwwSjh7x0WE7u/elavt+aeZS3va49ochhon2kK+J13ij4EBvh5fiU3jguI0sZfdu\n\tK7lxPCy37MHlKuT4Pi9WNn94ic7UJ82hh02raGHx/untccpVasW32S843KtzNAo7mGkx\n\trZYnGrUFAp1l8bFYbCbrkyXxsLl+qtW56eYVunyoq2h7rY9oZR5u3ZctFhlueDwlY+VQ\n\tY486wvbZlRXGx5h/wUtsRJaCxg6ktGxov2pG3U5dfSlICvQxn5AEXF57y0eKN9Di3pLy\n\tJnow==","X-Gm-Message-State":"AHPjjUgTZ7rPKruwWDnnGraeXkxEGbC1aXlzGdtX98Entveb6xrWtLiy\n\tHEgodxH6Z1yKTiQDsKPbXk4pGRZMdg==","X-Google-Smtp-Source":"ADKCNb5NKufNNyPodGhg9ualjHV0rCjx2W7C2vPKiSIDNKNmwEqn1VMcWtBXf1b40sZ5Bqa/A48wDIBQAi6ZvU8Hz9Y=","X-Received":"by 10.28.65.8 with SMTP id o8mr345204wma.146.1504657000027; Tue,\n\t05 Sep 2017 17:16:40 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"","References":"<1504533662-198084-1-git-send-email-imammedo@redhat.com>\n\t<1504533662-198084-7-git-send-email-imammedo@redhat.com>\n\t<20170905213152.GG17184@localhost.localdomain>\n\t\n\t<20170905221226.GZ7570@localhost.localdomain>\n\t","From":"Alistair Francis ","Date":"Tue, 5 Sep 2017 17:16:09 -0700","Message-ID":"","To":"Eduardo Habkost ","Content-Type":"text/plain; charset=\"UTF-8\"","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2a00:1450:400c:c09::22d","Subject":"Re: [Qemu-devel] [PATCH 6/6] arm: drop intermadiate cpu_model ->\n\tcpu type parsing and use cpu type directly","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Rob Herring , Andrew Jones ,\n\tPeter Maydell ,\n\tIgor Mitsyanko ,\n\tAlistair Francis ,\n\t\"qemu-devel@nongnu.org Developers\" ,\n\tqemu-arm , Jan Kiszka ,\n\t\"Edgar E. Iglesias\" ,\n\tIgor Mammedov , Richard Henderson ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1765859,"web_url":"http://patchwork.ozlabs.org/comment/1765859/","msgid":"<20170909203014.GG7570@localhost.localdomain>","list_archive_url":null,"date":"2017-09-09T20:30:14","subject":"Re: [Qemu-devel] [PATCH 6/6] arm: drop intermadiate cpu_model ->\n\tcpu type parsing and use cpu type directly","submitter":{"id":195,"url":"http://patchwork.ozlabs.org/api/people/195/","name":"Eduardo Habkost","email":"ehabkost@redhat.com"},"content":"On Tue, Sep 05, 2017 at 03:46:07PM -0700, Alistair Francis wrote:\n> On Tue, Sep 5, 2017 at 3:12 PM, Eduardo Habkost wrote:\n> > On Tue, Sep 05, 2017 at 02:47:52PM -0700, Alistair Francis wrote:\n> >> On Tue, Sep 5, 2017 at 2:31 PM, Eduardo Habkost wrote:\n> > [...]\n> >> >> diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c\n> >> >> index f61e735..1cd6374 100644\n> >> >> --- a/hw/arm/stm32f205_soc.c\n> >> >> +++ b/hw/arm/stm32f205_soc.c\n> >> >> @@ -112,7 +112,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)\n> >> >>\n> >> >> armv7m = DEVICE(&s->armv7m);\n> >> >> qdev_prop_set_uint32(armv7m, \"num-irq\", 96);\n> >> >> - qdev_prop_set_string(armv7m, \"cpu-model\", s->cpu_model);\n> >> >> + qdev_prop_set_string(armv7m, \"cpu-type\", s->cpu_type);\n> >> >> object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),\n> >> >> \"memory\", &error_abort);\n> >> >> object_property_set_bool(OBJECT(&s->armv7m), true, \"realized\", &err);\n> >> >> @@ -200,7 +200,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)\n> >> >> }\n> >> >>\n> >> >> static Property stm32f205_soc_properties[] = {\n> >> >> - DEFINE_PROP_STRING(\"cpu-model\", STM32F205State, cpu_model),\n> >> >> + DEFINE_PROP_STRING(\"cpu-type\", STM32F205State, cpu_type),\n> >> >\n> >> > Same as armv7m: are we 100% sure users are not setting this\n> >> > manually?\n> >>\n> >> In an embedded board like this it really doesn't make sense to let the\n> >> user overwrite the CPU. The SoC will take it as an option, but the\n> >> board (which creates the SoC) just blindly always uses the same CPU.\n> >> That feature is more for QOMificatoion then any real reason though.\n> >>\n> >\n> > I'm not talking about -cpu (no user-visible change in the\n> > handling of -cpu should result from this patch), but about\n> > possible cases where the user set the \"cpu-model\" property using\n> > another mechanism, like -global. Probably it's impossible for an\n> > user to override the property successfully, but I would like to\n> > be sure.\n> \n> Ah, that is trickier.\n> \n> I guess that is possible to do, but the object setting logic should\n> handle the error gracefully and inform the user of the error.\n\nAfter looking at the code more closely, I think we can be 100%\nsure the user doesn't rely on the property, because:\n\n* TYPE_ARMV7M and TYPE_STM32F205_SOC are both sysbus devices\n with user_creatable=false, so the user can't instantiate them\n directly;\n* The only places where those objects are realized inside the\n code are:\n * mps2_common_init()\n * netduino2_init()\n * stm32f205_soc_realize()\n * armv7m_init()\n Those functions always set the \"cpu-model\" property immediately\n before realize.\n\nThis means any value set by the user (e.g. using -global) would\nbe always overwritten before realize.\n\nHowever, I have a suggestion for Igor: making a separate patch\nthat renames the existing property to \"x-cpu-model\", and using\n\"x-cpu-type\" in this series. This way we will explicitly\ndocument the fact that the property is not a stable\nuser/management interface.\n\n> \n> >\n> >\n> >> In saying that I think a warning if the user tries to set the CPU\n> >> would make sense. I know that this issues comes up in other ARM boards\n> >> (Zynq-7000 has the same issue as well) so maybe a machine property\n> >> saying that the board doesn't accept custom CPUs would be a good idea.\n> >\n> > Yeah, there are multiple cases in this patch where boards are\n> > validating the CPU model, but not all boards do that. A generic\n> > MachineClass::valid_cpu_types[] field would be useful.\n> >\n> >>\n> >> Overall I think this patch is moving in the right direction though and\n> >> this CPU option being ignored existed before this series.\n> >\n> > I agree this is going on the right direction. However, I don't\n> > see any board that ignore the CPU option: all of them seem to use\n> > cpu_model when creating the CPUs, already.\n> \n> The Netduino2 will ignore any CPU options and always use a Cortex-m3.\n> I was wrong about Zynq-7000 though, it does respect the -cpu option.\n> \n> Thanks,\n> Alistair\n> \n> >\n> > --\n> > Eduardo","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ext-mx06.extmail.prod.ext.phx2.redhat.com;\n\tdmarc=none (p=none dis=none) header.from=redhat.com","ext-mx06.extmail.prod.ext.phx2.redhat.com;\n\tspf=fail smtp.mailfrom=ehabkost@redhat.com"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xqQnb4hKdz9s06\n\tfor ;\n\tSun, 10 Sep 2017 06:31:13 +1000 (AEST)","from localhost ([::1]:50802 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dqmPF-00012r-VD\n\tfor incoming@patchwork.ozlabs.org; Sat, 09 Sep 2017 16:31:10 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:45000)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1dqmOc-00010h-1y\n\tfor qemu-devel@nongnu.org; Sat, 09 Sep 2017 16:30:31 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1dqmOa-0000wC-V5\n\tfor qemu-devel@nongnu.org; Sat, 09 Sep 2017 16:30:30 -0400","from mx1.redhat.com ([209.132.183.28]:42864)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1dqmOW-0000pc-8O; Sat, 09 Sep 2017 16:30:24 -0400","from smtp.corp.redhat.com\n\t(int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby mx1.redhat.com (Postfix) with ESMTPS id C18AD356D6;\n\tSat, 9 Sep 2017 20:30:17 +0000 (UTC)","from localhost (ovpn-116-45.gru2.redhat.com [10.97.116.45])\n\tby smtp.corp.redhat.com (Postfix) with ESMTP id C377960F8C;\n\tSat, 9 Sep 2017 20:30:15 +0000 (UTC)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mx1.redhat.com C18AD356D6","Date":"Sat, 9 Sep 2017 17:30:14 -0300","From":"Eduardo Habkost ","To":"Alistair Francis ","Message-ID":"<20170909203014.GG7570@localhost.localdomain>","References":"<1504533662-198084-1-git-send-email-imammedo@redhat.com>\n\t<1504533662-198084-7-git-send-email-imammedo@redhat.com>\n\t<20170905213152.GG17184@localhost.localdomain>\n\t\n\t<20170905221226.GZ7570@localhost.localdomain>\n\t","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"","X-Fnord":"you can see the fnord","User-Agent":"Mutt/1.8.3 (2017-05-23)","X-Scanned-By":"MIMEDefang 2.79 on 10.5.11.12","X-Greylist":"Sender IP whitelisted, not delayed by milter-greylist-4.5.16\n\t(mx1.redhat.com [10.5.110.30]);\n\tSat, 09 Sep 2017 20:30:23 +0000 (UTC)","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]","X-Received-From":"209.132.183.28","Subject":"Re: [Qemu-devel] [PATCH 6/6] arm: drop intermadiate cpu_model ->\n\tcpu type parsing and use cpu type directly","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Rob Herring , Andrew Jones ,\n\tPeter Maydell ,\n\tIgor Mitsyanko ,\n\tAlistair Francis ,\n\t\"qemu-devel@nongnu.org Developers\" ,\n\tqemu-arm , Jan Kiszka ,\n\t\"Edgar E. Iglesias\" ,\n\tIgor Mammedov , Richard Henderson ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1765881,"web_url":"http://patchwork.ozlabs.org/comment/1765881/","msgid":"","list_archive_url":null,"date":"2017-09-09T22:41:55","subject":"Re: [Qemu-devel] [PATCH 6/6] arm: drop intermadiate cpu_model ->\n\tcpu type parsing and use cpu type directly","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/people/5111/","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"content":"On 9 September 2017 at 21:30, Eduardo Habkost wrote:\n> However, I have a suggestion for Igor: making a separate patch\n> that renames the existing property to \"x-cpu-model\", and using\n> \"x-cpu-type\" in this series. This way we will explicitly\n> document the fact that the property is not a stable\n> user/management interface.\n\nWe have lots and lots of properties on non-user-instantiated\ndevices that aren't intended as user level configurable\nthings...\n\nthanks\n-- PMM","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"AZJwNha/\"; dkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xqTjN3h1Lz9s83\n\tfor ;\n\tSun, 10 Sep 2017 08:42:44 +1000 (AEST)","from localhost ([::1]:51083 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dqoSW-00026x-EU\n\tfor incoming@patchwork.ozlabs.org; Sat, 09 Sep 2017 18:42:40 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:37578)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1dqoSB-00025Y-0N\n\tfor qemu-devel@nongnu.org; Sat, 09 Sep 2017 18:42:19 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1dqoSA-0008WC-9A\n\tfor qemu-devel@nongnu.org; Sat, 09 Sep 2017 18:42:19 -0400","from mail-wm0-x230.google.com ([2a00:1450:400c:c09::230]:44523)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from )\n\tid 1dqoSA-0008Vh-38\n\tfor qemu-devel@nongnu.org; Sat, 09 Sep 2017 18:42:18 -0400","by mail-wm0-x230.google.com with SMTP id 137so13487298wmj.1\n\tfor ; Sat, 09 Sep 2017 15:42:17 -0700 (PDT)","by 10.223.139.215 with HTTP; Sat, 9 Sep 2017 15:41:55 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=mime-version:in-reply-to:references:from:date:message-id:subject:to\n\t:cc; bh=Em10Am+QWQYxdO5XUy2UgvoUiH2226A4ZMrbX00AocE=;\n\tb=AZJwNha/OXI2+DG59z4+R/61ecemL2ioCjqsHLqtq9U9OB2Nyr9DaWSkjCB8ZdB7a7\n\tEgpqTksoEZ5/BLaVQnrGYYVpBXst4RTaiXCNGeHPftat2oRIG/b6O8qe78Va+wygi2Ev\n\tIWcJiHsjn1V38ptPMhZB10ngqYIe+H7Kj7PGk=","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:mime-version:in-reply-to:references:from:date\n\t:message-id:subject:to:cc;\n\tbh=Em10Am+QWQYxdO5XUy2UgvoUiH2226A4ZMrbX00AocE=;\n\tb=pymlN+94W9gJ6QW2qX+tNjHouajYMCZmrIjnZa3H690kT4rF6q3zTgBvIpP71BMA+h\n\tU9lk6FHmchPQD4HvWoFWt9OVKqPjZivRhgckcAVmxKxFo1JDH566sC04uM6tkRcoBrGt\n\tak9nr93Mo9v9aB7aE8fLVbN5Pnxm7Dy6jRorOjhG/1uOBJRkleFTVkWEItQ6lZH9QFnO\n\trpj3tvdJYSdad/azTwICLgQMD+3YJhYN8S4Yjw45ITNcPQFIVarOuNQjypr5/iepzM5F\n\tMRJRT3SKwNbOO25JZ82uo3aOmm2BSxUokzjIlb20d2PAU0TDv5570gRiEqHUZQlCx+xz\n\ticnw==","X-Gm-Message-State":"AHPjjUjCUmJB7QW7PLi1xv4JIekWn78ClBwNKGeNEqOvCiMU8Wl/VWo7\n\tIz9fWieascz7Mck7rjFsDThh2AhZCrdgWUlWWNRMRw==","X-Google-Smtp-Source":"AOwi7QCiu0DUqHbcA0Rt6QaEl7/bXGmZHCMD9zT4QUOTNTcfokgjCbSUrlZ7GSw31OWWH+UZrlqmA5m4H2jUuXTOkl0=","X-Received":"by 10.28.43.129 with SMTP id r123mr1428847wmr.101.1504996936609; \n\tSat, 09 Sep 2017 15:42:16 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"<20170909203014.GG7570@localhost.localdomain>","References":"<1504533662-198084-1-git-send-email-imammedo@redhat.com>\n\t<1504533662-198084-7-git-send-email-imammedo@redhat.com>\n\t<20170905213152.GG17184@localhost.localdomain>\n\t\n\t<20170905221226.GZ7570@localhost.localdomain>\n\t\n\t<20170909203014.GG7570@localhost.localdomain>","From":"Peter Maydell ","Date":"Sat, 9 Sep 2017 23:41:55 +0100","Message-ID":"","To":"Eduardo Habkost ","Content-Type":"text/plain; charset=\"UTF-8\"","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2a00:1450:400c:c09::230","Subject":"Re: [Qemu-devel] [PATCH 6/6] arm: drop intermadiate cpu_model ->\n\tcpu type parsing and use cpu type directly","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Rob Herring , Andrew Jones ,\n\tIgor Mitsyanko ,\n\tAlistair Francis ,\n\t\"Edgar E. Iglesias\" ,\n\t\"qemu-devel@nongnu.org Developers\" ,\n\tqemu-arm , Jan Kiszka ,\n\tIgor Mammedov ,\n\tAlistair Francis ,\n\tRichard Henderson ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1765884,"web_url":"http://patchwork.ozlabs.org/comment/1765884/","msgid":"<20170909232232.GM7570@localhost.localdomain>","list_archive_url":null,"date":"2017-09-09T23:22:33","subject":"Re: [Qemu-devel] [PATCH 6/6] arm: drop intermadiate cpu_model ->\n\tcpu type parsing and use cpu type directly","submitter":{"id":195,"url":"http://patchwork.ozlabs.org/api/people/195/","name":"Eduardo Habkost","email":"ehabkost@redhat.com"},"content":"On Sat, Sep 09, 2017 at 11:41:55PM +0100, Peter Maydell wrote:\n> On 9 September 2017 at 21:30, Eduardo Habkost wrote:\n> > However, I have a suggestion for Igor: making a separate patch\n> > that renames the existing property to \"x-cpu-model\", and using\n> > \"x-cpu-type\" in this series. This way we will explicitly\n> > document the fact that the property is not a stable\n> > user/management interface.\n> \n> We have lots and lots of properties on non-user-instantiated\n> devices that aren't intended as user level configurable\n> things...\n\nWell, we need to deal with them somehow, otherwise we have no\nsimple way to know if removing/renaming a property is really safe\nor not.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ext-mx03.extmail.prod.ext.phx2.redhat.com;\n\tdmarc=none (p=none dis=none) header.from=redhat.com","ext-mx03.extmail.prod.ext.phx2.redhat.com;\n\tspf=fail smtp.mailfrom=ehabkost@redhat.com"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xqVcD72vBz9s7M\n\tfor ;\n\tSun, 10 Sep 2017 09:23:22 +1000 (AEST)","from localhost ([::1]:51149 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dqp5r-0000S3-3Y\n\tfor incoming@patchwork.ozlabs.org; Sat, 09 Sep 2017 19:23:19 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:45381)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1dqp5H-0000On-RB\n\tfor qemu-devel@nongnu.org; Sat, 09 Sep 2017 19:22:44 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1dqp5H-0008Ec-0v\n\tfor qemu-devel@nongnu.org; Sat, 09 Sep 2017 19:22:43 -0400","from mx1.redhat.com ([209.132.183.28]:42694)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1dqp5B-0008Bp-Op; Sat, 09 Sep 2017 19:22:37 -0400","from smtp.corp.redhat.com\n\t(int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby mx1.redhat.com (Postfix) with ESMTPS id 30A1883F3D;\n\tSat, 9 Sep 2017 23:22:36 +0000 (UTC)","from localhost (ovpn-116-45.gru2.redhat.com [10.97.116.45])\n\tby smtp.corp.redhat.com (Postfix) with ESMTP id 995F35D9C0;\n\tSat, 9 Sep 2017 23:22:34 +0000 (UTC)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mx1.redhat.com 30A1883F3D","Date":"Sat, 9 Sep 2017 20:22:33 -0300","From":"Eduardo Habkost ","To":"Peter Maydell ","Message-ID":"<20170909232232.GM7570@localhost.localdomain>","References":"<1504533662-198084-1-git-send-email-imammedo@redhat.com>\n\t<1504533662-198084-7-git-send-email-imammedo@redhat.com>\n\t<20170905213152.GG17184@localhost.localdomain>\n\t\n\t<20170905221226.GZ7570@localhost.localdomain>\n\t\n\t<20170909203014.GG7570@localhost.localdomain>\n\t","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"","X-Fnord":"you can see the fnord","User-Agent":"Mutt/1.8.3 (2017-05-23)","X-Scanned-By":"MIMEDefang 2.79 on 10.5.11.14","X-Greylist":"Sender IP whitelisted, not delayed by milter-greylist-4.5.16\n\t(mx1.redhat.com [10.5.110.27]);\n\tSat, 09 Sep 2017 23:22:36 +0000 (UTC)","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]","X-Received-From":"209.132.183.28","Subject":"Re: [Qemu-devel] [PATCH 6/6] arm: drop intermadiate cpu_model ->\n\tcpu type parsing and use cpu type directly","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Rob Herring , Andrew Jones ,\n\tIgor Mitsyanko ,\n\tAlistair Francis ,\n\t\"Edgar E. Iglesias\" ,\n\t\"qemu-devel@nongnu.org Developers\" ,\n\tqemu-arm , Jan Kiszka ,\n\tIgor Mammedov ,\n\tAlistair Francis ,\n\tRichard Henderson ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1766848,"web_url":"http://patchwork.ozlabs.org/comment/1766848/","msgid":"<20170912122214.29f0840e@nial.brq.redhat.com>","list_archive_url":null,"date":"2017-09-12T10:22:14","subject":"Re: [Qemu-devel] [PATCH 6/6] arm: drop intermadiate cpu_model ->\n\tcpu type parsing and use cpu type directly","submitter":{"id":11305,"url":"http://patchwork.ozlabs.org/api/people/11305/","name":"Igor Mammedov","email":"imammedo@redhat.com"},"content":"On Sat, 9 Sep 2017 17:30:14 -0300\nEduardo Habkost wrote:\n\n> On Tue, Sep 05, 2017 at 03:46:07PM -0700, Alistair Francis wrote:\n> > On Tue, Sep 5, 2017 at 3:12 PM, Eduardo Habkost wrote: \n> > > On Tue, Sep 05, 2017 at 02:47:52PM -0700, Alistair Francis wrote: \n> > >> On Tue, Sep 5, 2017 at 2:31 PM, Eduardo Habkost wrote: \n> > > [...] \n> > >> >> diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c\n> > >> >> index f61e735..1cd6374 100644\n> > >> >> --- a/hw/arm/stm32f205_soc.c\n> > >> >> +++ b/hw/arm/stm32f205_soc.c\n> > >> >> @@ -112,7 +112,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)\n> > >> >>\n> > >> >> armv7m = DEVICE(&s->armv7m);\n> > >> >> qdev_prop_set_uint32(armv7m, \"num-irq\", 96);\n> > >> >> - qdev_prop_set_string(armv7m, \"cpu-model\", s->cpu_model);\n> > >> >> + qdev_prop_set_string(armv7m, \"cpu-type\", s->cpu_type);\n> > >> >> object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),\n> > >> >> \"memory\", &error_abort);\n> > >> >> object_property_set_bool(OBJECT(&s->armv7m), true, \"realized\", &err);\n> > >> >> @@ -200,7 +200,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)\n> > >> >> }\n> > >> >>\n> > >> >> static Property stm32f205_soc_properties[] = {\n> > >> >> - DEFINE_PROP_STRING(\"cpu-model\", STM32F205State, cpu_model),\n> > >> >> + DEFINE_PROP_STRING(\"cpu-type\", STM32F205State, cpu_type), \n> > >> >\n> > >> > Same as armv7m: are we 100% sure users are not setting this\n> > >> > manually? \n> > >>\n> > >> In an embedded board like this it really doesn't make sense to let the\n> > >> user overwrite the CPU. The SoC will take it as an option, but the\n> > >> board (which creates the SoC) just blindly always uses the same CPU.\n> > >> That feature is more for QOMificatoion then any real reason though.\n> > >> \n> > >\n> > > I'm not talking about -cpu (no user-visible change in the\n> > > handling of -cpu should result from this patch), but about\n> > > possible cases where the user set the \"cpu-model\" property using\n> > > another mechanism, like -global. Probably it's impossible for an\n> > > user to override the property successfully, but I would like to\n> > > be sure. \n> > \n> > Ah, that is trickier.\n> > \n> > I guess that is possible to do, but the object setting logic should\n> > handle the error gracefully and inform the user of the error. \n> \n> After looking at the code more closely, I think we can be 100%\n> sure the user doesn't rely on the property, because:\n> \n> * TYPE_ARMV7M and TYPE_STM32F205_SOC are both sysbus devices\n> with user_creatable=false, so the user can't instantiate them\n> directly;\n> * The only places where those objects are realized inside the\n> code are:\n> * mps2_common_init()\n> * netduino2_init()\n> * stm32f205_soc_realize()\n> * armv7m_init()\n> Those functions always set the \"cpu-model\" property immediately\n> before realize.\n> \n> This means any value set by the user (e.g. using -global) would\n> be always overwritten before realize.\n> \n> However, I have a suggestion for Igor: making a separate patch\n> that renames the existing property to \"x-cpu-model\", and using\n> \"x-cpu-type\" in this series. This way we will explicitly\n> document the fact that the property is not a stable\n> user/management interface.\nThere is no much point in renaming to \"x-cpu-model\" as it will be deleted\nright afterwards, I'd just delete \"cpu-model\" and use \"x-cpu-type\"\nin this patch. I'm not a fun of 'x-' prefix and would prefer a flag\nin property to mark it as internal. But it's out of scope of this series,\nso I don't care much about naming at the moment and will use \"x-cpu-type\"\nas you suggest.\n\n> \n> > \n> > >\n> > > \n> > >> In saying that I think a warning if the user tries to set the CPU\n> > >> would make sense. I know that this issues comes up in other ARM boards\n> > >> (Zynq-7000 has the same issue as well) so maybe a machine property\n> > >> saying that the board doesn't accept custom CPUs would be a good idea. \n> > >\n> > > Yeah, there are multiple cases in this patch where boards are\n> > > validating the CPU model, but not all boards do that. A generic\n> > > MachineClass::valid_cpu_types[] field would be useful.\n> > > \n> > >>\n> > >> Overall I think this patch is moving in the right direction though and\n> > >> this CPU option being ignored existed before this series. \n> > >\n> > > I agree this is going on the right direction. However, I don't\n> > > see any board that ignore the CPU option: all of them seem to use\n> > > cpu_model when creating the CPUs, already. \n> > \n> > The Netduino2 will ignore any CPU options and always use a Cortex-m3.\n> > I was wrong about Zynq-7000 though, it does respect the -cpu option.\n> > \n> > Thanks,\n> > Alistair\n> > \n> > >\n> > > --\n> > > Eduardo \n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ext-mx06.extmail.prod.ext.phx2.redhat.com;\n\tdmarc=none (p=none dis=none) header.from=redhat.com","ext-mx06.extmail.prod.ext.phx2.redhat.com;\n\tspf=fail smtp.mailfrom=imammedo@redhat.com"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xs18F6SFBz9sNV\n\tfor ;\n\tTue, 12 Sep 2017 20:22:53 +1000 (AEST)","from localhost ([::1]:34732 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1driLE-000467-1k\n\tfor incoming@patchwork.ozlabs.org; Tue, 12 Sep 2017 06:22:52 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:34009)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1driKo-00044q-Qo\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 06:22:28 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1driKn-0006HB-LO\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 06:22:26 -0400","from mx1.redhat.com ([209.132.183.28]:38080)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1driKh-00064h-CO; Tue, 12 Sep 2017 06:22:19 -0400","from smtp.corp.redhat.com\n\t(int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby mx1.redhat.com (Postfix) with ESMTPS id 4A68D356C9;\n\tTue, 12 Sep 2017 10:22:18 +0000 (UTC)","from nial.brq.redhat.com (unknown [10.43.2.209])\n\tby smtp.corp.redhat.com (Postfix) with ESMTP id 899556F9F9;\n\tTue, 12 Sep 2017 10:22:15 +0000 (UTC)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mx1.redhat.com 4A68D356C9","Date":"Tue, 12 Sep 2017 12:22:14 +0200","From":"Igor Mammedov ","To":"Eduardo Habkost ","Message-ID":"<20170912122214.29f0840e@nial.brq.redhat.com>","In-Reply-To":"<20170909203014.GG7570@localhost.localdomain>","References":"<1504533662-198084-1-git-send-email-imammedo@redhat.com>\n\t<1504533662-198084-7-git-send-email-imammedo@redhat.com>\n\t<20170905213152.GG17184@localhost.localdomain>\n\t\n\t<20170905221226.GZ7570@localhost.localdomain>\n\t\n\t<20170909203014.GG7570@localhost.localdomain>","MIME-Version":"1.0","Content-Type":"text/plain; charset=US-ASCII","Content-Transfer-Encoding":"7bit","X-Scanned-By":"MIMEDefang 2.79 on 10.5.11.15","X-Greylist":"Sender IP whitelisted, not delayed by milter-greylist-4.5.16\n\t(mx1.redhat.com [10.5.110.30]);\n\tTue, 12 Sep 2017 10:22:18 +0000 (UTC)","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]","X-Received-From":"209.132.183.28","Subject":"Re: [Qemu-devel] [PATCH 6/6] arm: drop intermadiate cpu_model ->\n\tcpu type parsing and use cpu type directly","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Rob Herring , Andrew Jones ,\n\tPeter Maydell ,\n\tIgor Mitsyanko ,\n\tAlistair Francis ,\n\t\"qemu-devel@nongnu.org Developers\" ,\n\tqemu-arm , Jan Kiszka ,\n\t\"Edgar E. Iglesias\" ,\n\tAlistair Francis ,\n\tRichard Henderson ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1766879,"web_url":"http://patchwork.ozlabs.org/comment/1766879/","msgid":"<20170912125307.5681ec0e@nial.brq.redhat.com>","list_archive_url":null,"date":"2017-09-12T10:53:07","subject":"Re: [Qemu-devel] [PATCH 6/6] arm: drop intermadiate cpu_model ->\n\tcpu type parsing and use cpu type directly","submitter":{"id":11305,"url":"http://patchwork.ozlabs.org/api/people/11305/","name":"Igor Mammedov","email":"imammedo@redhat.com"},"content":"On Tue, 5 Sep 2017 19:12:26 -0300\nEduardo Habkost wrote:\n\n> On Tue, Sep 05, 2017 at 02:47:52PM -0700, Alistair Francis wrote:\n> > On Tue, Sep 5, 2017 at 2:31 PM, Eduardo Habkost wrote: \n> [...]\n> > >> diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c\n> > >> index f61e735..1cd6374 100644\n> > >> --- a/hw/arm/stm32f205_soc.c\n> > >> +++ b/hw/arm/stm32f205_soc.c\n> > >> @@ -112,7 +112,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)\n> > >>\n> > >> armv7m = DEVICE(&s->armv7m);\n> > >> qdev_prop_set_uint32(armv7m, \"num-irq\", 96);\n> > >> - qdev_prop_set_string(armv7m, \"cpu-model\", s->cpu_model);\n> > >> + qdev_prop_set_string(armv7m, \"cpu-type\", s->cpu_type);\n> > >> object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),\n> > >> \"memory\", &error_abort);\n> > >> object_property_set_bool(OBJECT(&s->armv7m), true, \"realized\", &err);\n> > >> @@ -200,7 +200,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)\n> > >> }\n> > >>\n> > >> static Property stm32f205_soc_properties[] = {\n> > >> - DEFINE_PROP_STRING(\"cpu-model\", STM32F205State, cpu_model),\n> > >> + DEFINE_PROP_STRING(\"cpu-type\", STM32F205State, cpu_type), \n> > >\n> > > Same as armv7m: are we 100% sure users are not setting this\n> > > manually? \n> > \n> > In an embedded board like this it really doesn't make sense to let the\n> > user overwrite the CPU. The SoC will take it as an option, but the\n> > board (which creates the SoC) just blindly always uses the same CPU.\n> > That feature is more for QOMificatoion then any real reason though.\n> > \n> \n> I'm not talking about -cpu (no user-visible change in the\n> handling of -cpu should result from this patch), but about\n> possible cases where the user set the \"cpu-model\" property using\n> another mechanism, like -global. Probably it's impossible for an\n> user to override the property successfully, but I would like to\n> be sure.\n> \n> \n> > In saying that I think a warning if the user tries to set the CPU\n> > would make sense. I know that this issues comes up in other ARM boards\n> > (Zynq-7000 has the same issue as well) so maybe a machine property\n> > saying that the board doesn't accept custom CPUs would be a good idea.\nAgreed, it would be useful, however goal of the patch to drop\ncpu_generic_init() preferably without changing behavior\n\nso I'd leave extra stuff you mention upto board maintainers\nto fix up on top.\n\n\n> Yeah, there are multiple cases in this patch where boards are\n> validating the CPU model, but not all boards do that. A generic\n> MachineClass::valid_cpu_types[] field would be useful.\nso far I've met 3 use cases for valid_cpu_types\n * no check - just try to use whatever user provided\n * check for concrete cpu models (leaf classes)\n * check for super-class based in partial cpu_model match\n\nit is nice to have valid_cpu_types[] /I recall even trying out something similar/\nbut then series turns into mess where one tries to fix several things\nand on top of it in all targets, hence I've decided first to get rid of\nall cpu_model handling in boards and only then think about valid_cpus using cpu types.\n\nI'd gladly give up 'valid cpus' to someone else more interested in it,\nthere are other users beside of ARM boards for it.\n/seems Alistair is interested in it, at least in ARM part/\n\n\n> > Overall I think this patch is moving in the right direction though and\n> > this CPU option being ignored existed before this series. \n> \n> I agree this is going on the right direction. However, I don't\n> see any board that ignore the CPU option: all of them seem to use\n> cpu_model when creating the CPUs, already.\nin ARM case there are boards that use\n * '-cpu' provided model\n * '-cpu' provided model with valid cpu checks\n * 'hardcoded' cpu model ignoring '-cpu'/-global\n\nI've thought commit message sufficiently described current situation and changes.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ext-mx04.extmail.prod.ext.phx2.redhat.com;\n\tdmarc=none (p=none dis=none) header.from=redhat.com","ext-mx04.extmail.prod.ext.phx2.redhat.com;\n\tspf=fail smtp.mailfrom=imammedo@redhat.com"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xs1rB0h64z9s7g\n\tfor ;\n\tTue, 12 Sep 2017 20:54:02 +1000 (AEST)","from localhost ([::1]:34885 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dripM-0000fS-5S\n\tfor incoming@patchwork.ozlabs.org; Tue, 12 Sep 2017 06:54:00 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:43844)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1drioj-0000ci-Ex\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 06:53:22 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1drioi-0003Dt-Cu\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 06:53:21 -0400","from mx1.redhat.com ([209.132.183.28]:53646)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1driob-00039A-Hc; Tue, 12 Sep 2017 06:53:13 -0400","from smtp.corp.redhat.com\n\t(int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby mx1.redhat.com (Postfix) with ESMTPS id 49F2E8553E;\n\tTue, 12 Sep 2017 10:53:12 +0000 (UTC)","from nial.brq.redhat.com (unknown [10.43.2.209])\n\tby smtp.corp.redhat.com (Postfix) with ESMTP id 7DC6E6C92E;\n\tTue, 12 Sep 2017 10:53:08 +0000 (UTC)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mx1.redhat.com 49F2E8553E","Date":"Tue, 12 Sep 2017 12:53:07 +0200","From":"Igor Mammedov ","To":"Eduardo Habkost ","Message-ID":"<20170912125307.5681ec0e@nial.brq.redhat.com>","In-Reply-To":"<20170905221226.GZ7570@localhost.localdomain>","References":"<1504533662-198084-1-git-send-email-imammedo@redhat.com>\n\t<1504533662-198084-7-git-send-email-imammedo@redhat.com>\n\t<20170905213152.GG17184@localhost.localdomain>\n\t\n\t<20170905221226.GZ7570@localhost.localdomain>","MIME-Version":"1.0","Content-Type":"text/plain; charset=US-ASCII","Content-Transfer-Encoding":"7bit","X-Scanned-By":"MIMEDefang 2.79 on 10.5.11.14","X-Greylist":"Sender IP whitelisted, not delayed by milter-greylist-4.5.16\n\t(mx1.redhat.com [10.5.110.28]);\n\tTue, 12 Sep 2017 10:53:12 +0000 (UTC)","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]","X-Received-From":"209.132.183.28","Subject":"Re: [Qemu-devel] [PATCH 6/6] arm: drop intermadiate cpu_model ->\n\tcpu type parsing and use cpu type directly","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Rob Herring , Andrew Jones ,\n\tPeter Maydell ,\n\tIgor Mitsyanko ,\n\tAlistair Francis ,\n\t\"qemu-devel@nongnu.org Developers\" ,\n\tqemu-arm , Jan Kiszka ,\n\t\"Edgar E. Iglesias\" ,\n\tAlistair Francis ,\n\tRichard Henderson ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1766892,"web_url":"http://patchwork.ozlabs.org/comment/1766892/","msgid":"<20170912130235.2353dec3@nial.brq.redhat.com>","list_archive_url":null,"date":"2017-09-12T11:02:35","subject":"Re: [Qemu-devel] [PATCH 6/6] arm: drop intermadiate cpu_model ->\n\tcpu type parsing and use cpu type directly","submitter":{"id":11305,"url":"http://patchwork.ozlabs.org/api/people/11305/","name":"Igor Mammedov","email":"imammedo@redhat.com"},"content":"On Tue, 5 Sep 2017 14:47:52 -0700\nAlistair Francis wrote:\n\n> On Tue, Sep 5, 2017 at 2:31 PM, Eduardo Habkost wrote:\n> > On Mon, Sep 04, 2017 at 04:01:02PM +0200, Igor Mammedov wrote: \n> >> there are 2 use cases to deal with:\n> >> 1: fixed CPU models per board/soc\n> >> 2: boards with user configurable cpu_model and fallback to\n> >> default cpu_model if user hasn't specified one explicitly\n> >>\n> >> For the 1st\n> >> drop intermediate cpu_model parsing and use const cpu type\n> >> directly, which replaces:\n> >> typename = object_class_get_name(\n> >> cpu_class_by_name(TYPE_ARM_CPU, cpu_model))\n> >> object_new(typename)\n> >> with\n> >> object_new(FOO_CPU_TYPE_NAME)\n> >> or\n> >> cpu_generic_init(BASE_CPU_TYPE, \"my cpu model\")\n> >> with\n> >> cpu_create(FOO_CPU_TYPE_NAME)\n> >>\n> >> as result 1st use case doesn't have to invoke not necessary\n> >> translation and not needed code is removed.\n> >>\n> >> For the 2nd\n> >> 1: set default cpu type with MachineClass::default_cpu_type and\n> >> 2: use generic cpu_model parsing that done before machine_init()\n> >> is run and:\n> >> 2.1: drop custom cpu_model parsing where pattern is:\n> >> typename = object_class_get_name(\n> >> cpu_class_by_name(TYPE_ARM_CPU, cpu_model))\n> >> [parse_features(typename, cpu_model, &err) ]\n> >>\n> >> 2.2: or replace cpu_generic_init() which does what\n> >> 2.1 does + create_cpu(typename) with just\n> >> create_cpu(machine->cpu_type)\n> >> as result cpu_name -> cpu_type translation is done using\n> >> generic machine code one including parsing optional features\n> >> if supported/present (removes a bunch of duplicated cpu_model\n> >> parsing code) and default cpu type is defined in an uniform way\n> >> within machine_class_init callbacks instead of adhoc places\n> >> in boadr's machine_init code.\n> >>\n> >> Signed-off-by: Igor Mammedov \n> >> ---\n> >> CC: Peter Maydell \n> >> CC: Igor Mitsyanko \n> >> CC: Rob Herring \n> >> CC: Andrzej Zaborowski \n> >> CC: Jan Kiszka \n> >> CC: Alistair Francis \n> >> CC: \"Edgar E. Iglesias\" \n> >> CC: qemu-arm@nongnu.org\n> >> ---\n\n[...]\n\n> >>\n> >> static const TypeInfo lm3s6965evb_type = {\n> >> diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c\n> >> index f61e735..1cd6374 100644\n> >> --- a/hw/arm/stm32f205_soc.c\n> >> +++ b/hw/arm/stm32f205_soc.c\n> >> @@ -112,7 +112,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)\n> >>\n> >> armv7m = DEVICE(&s->armv7m);\n> >> qdev_prop_set_uint32(armv7m, \"num-irq\", 96);\n> >> - qdev_prop_set_string(armv7m, \"cpu-model\", s->cpu_model);\n> >> + qdev_prop_set_string(armv7m, \"cpu-type\", s->cpu_type);\n> >> object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),\n> >> \"memory\", &error_abort);\n> >> object_property_set_bool(OBJECT(&s->armv7m), true, \"realized\", &err);\n> >> @@ -200,7 +200,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)\n> >> }\n> >>\n> >> static Property stm32f205_soc_properties[] = {\n> >> - DEFINE_PROP_STRING(\"cpu-model\", STM32F205State, cpu_model),\n> >> + DEFINE_PROP_STRING(\"cpu-type\", STM32F205State, cpu_type), \n> >\n> > Same as armv7m: are we 100% sure users are not setting this\n> > manually? \n> \n> In an embedded board like this it really doesn't make sense to let the\n> user overwrite the CPU. The SoC will take it as an option, but the\n> board (which creates the SoC) just blindly always uses the same CPU.\n> That feature is more for QOMificatoion then any real reason though.\nIf SoC has fixed cpu type then I'd drop property.\nI'd leave it upto board maintainers to cleanup not really needed\nproperties and make soc with fixed cpu type where it makes sense.\n\n> In saying that I think a warning if the user tries to set the CPU\n> would make sense. I know that this issues comes up in other ARM boards\n> (Zynq-7000 has the same issue as well) so maybe a machine property\n> saying that the board doesn't accept custom CPUs would be a good idea.\n> \n> Overall I think this patch is moving in the right direction though and\n> this CPU option being ignored existed before this series.\nright, this series just removes cpu_generic_init()/cpu_model in boards\neverything else should be done as separate series.\n\n> \n> Thanks,\n> Alistair\n> \n> \n> >\n> > \n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ext-mx04.extmail.prod.ext.phx2.redhat.com;\n\tdmarc=none (p=none dis=none) header.from=redhat.com","ext-mx04.extmail.prod.ext.phx2.redhat.com;\n\tspf=fail smtp.mailfrom=imammedo@redhat.com"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xs2323XLCz9s82\n\tfor ;\n\tTue, 12 Sep 2017 21:03:24 +1000 (AEST)","from localhost ([::1]:34927 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1driyQ-0004UI-0M\n\tfor incoming@patchwork.ozlabs.org; Tue, 12 Sep 2017 07:03:22 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:47527)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1drixy-0004TR-7B\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 07:02:58 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1drixt-0001dA-9O\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 07:02:54 -0400","from mx1.redhat.com ([209.132.183.28]:40856)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1drixl-0001Yj-N4; Tue, 12 Sep 2017 07:02:41 -0400","from smtp.corp.redhat.com\n\t(int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby mx1.redhat.com (Postfix) with ESMTPS id D0C638553D;\n\tTue, 12 Sep 2017 11:02:39 +0000 (UTC)","from nial.brq.redhat.com (unknown [10.43.2.209])\n\tby smtp.corp.redhat.com (Postfix) with ESMTP id 36DD562662;\n\tTue, 12 Sep 2017 11:02:37 +0000 (UTC)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mx1.redhat.com D0C638553D","Date":"Tue, 12 Sep 2017 13:02:35 +0200","From":"Igor Mammedov ","To":"Alistair Francis ","Message-ID":"<20170912130235.2353dec3@nial.brq.redhat.com>","In-Reply-To":"","References":"<1504533662-198084-1-git-send-email-imammedo@redhat.com>\n\t<1504533662-198084-7-git-send-email-imammedo@redhat.com>\n\t<20170905213152.GG17184@localhost.localdomain>\n\t","MIME-Version":"1.0","Content-Type":"text/plain; charset=US-ASCII","Content-Transfer-Encoding":"7bit","X-Scanned-By":"MIMEDefang 2.79 on 10.5.11.15","X-Greylist":"Sender IP whitelisted, not delayed by milter-greylist-4.5.16\n\t(mx1.redhat.com [10.5.110.28]);\n\tTue, 12 Sep 2017 11:02:40 +0000 (UTC)","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]","X-Received-From":"209.132.183.28","Subject":"Re: [Qemu-devel] [PATCH 6/6] arm: drop intermadiate cpu_model ->\n\tcpu type parsing and use cpu type directly","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Rob Herring , Andrew Jones ,\n\tEduardo Habkost ,\n\tPeter Maydell ,\n\tIgor Mitsyanko ,\n\tAlistair Francis , \"qemu-devel@nongnu.org\n\tDevelopers\" , qemu-arm , \n\tJan Kiszka ,\n\t\"Edgar E. Iglesias\" ,\n\tRichard Henderson ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1766930,"web_url":"http://patchwork.ozlabs.org/comment/1766930/","msgid":"<20170912120138.GU7570@localhost.localdomain>","list_archive_url":null,"date":"2017-09-12T12:01:38","subject":"Re: [Qemu-devel] [PATCH 6/6] arm: drop intermadiate cpu_model ->\n\tcpu type parsing and use cpu type directly","submitter":{"id":195,"url":"http://patchwork.ozlabs.org/api/people/195/","name":"Eduardo Habkost","email":"ehabkost@redhat.com"},"content":"On Tue, Sep 12, 2017 at 12:22:14PM +0200, Igor Mammedov wrote:\n> On Sat, 9 Sep 2017 17:30:14 -0300\n> Eduardo Habkost wrote:\n> \n> > On Tue, Sep 05, 2017 at 03:46:07PM -0700, Alistair Francis wrote:\n> > > On Tue, Sep 5, 2017 at 3:12 PM, Eduardo Habkost wrote: \n> > > > On Tue, Sep 05, 2017 at 02:47:52PM -0700, Alistair Francis wrote: \n> > > >> On Tue, Sep 5, 2017 at 2:31 PM, Eduardo Habkost wrote: \n> > > > [...] \n> > > >> >> diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c\n> > > >> >> index f61e735..1cd6374 100644\n> > > >> >> --- a/hw/arm/stm32f205_soc.c\n> > > >> >> +++ b/hw/arm/stm32f205_soc.c\n> > > >> >> @@ -112,7 +112,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)\n> > > >> >>\n> > > >> >> armv7m = DEVICE(&s->armv7m);\n> > > >> >> qdev_prop_set_uint32(armv7m, \"num-irq\", 96);\n> > > >> >> - qdev_prop_set_string(armv7m, \"cpu-model\", s->cpu_model);\n> > > >> >> + qdev_prop_set_string(armv7m, \"cpu-type\", s->cpu_type);\n> > > >> >> object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),\n> > > >> >> \"memory\", &error_abort);\n> > > >> >> object_property_set_bool(OBJECT(&s->armv7m), true, \"realized\", &err);\n> > > >> >> @@ -200,7 +200,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)\n> > > >> >> }\n> > > >> >>\n> > > >> >> static Property stm32f205_soc_properties[] = {\n> > > >> >> - DEFINE_PROP_STRING(\"cpu-model\", STM32F205State, cpu_model),\n> > > >> >> + DEFINE_PROP_STRING(\"cpu-type\", STM32F205State, cpu_type), \n> > > >> >\n> > > >> > Same as armv7m: are we 100% sure users are not setting this\n> > > >> > manually? \n> > > >>\n> > > >> In an embedded board like this it really doesn't make sense to let the\n> > > >> user overwrite the CPU. The SoC will take it as an option, but the\n> > > >> board (which creates the SoC) just blindly always uses the same CPU.\n> > > >> That feature is more for QOMificatoion then any real reason though.\n> > > >> \n> > > >\n> > > > I'm not talking about -cpu (no user-visible change in the\n> > > > handling of -cpu should result from this patch), but about\n> > > > possible cases where the user set the \"cpu-model\" property using\n> > > > another mechanism, like -global. Probably it's impossible for an\n> > > > user to override the property successfully, but I would like to\n> > > > be sure. \n> > > \n> > > Ah, that is trickier.\n> > > \n> > > I guess that is possible to do, but the object setting logic should\n> > > handle the error gracefully and inform the user of the error. \n> > \n> > After looking at the code more closely, I think we can be 100%\n> > sure the user doesn't rely on the property, because:\n> > \n> > * TYPE_ARMV7M and TYPE_STM32F205_SOC are both sysbus devices\n> > with user_creatable=false, so the user can't instantiate them\n> > directly;\n> > * The only places where those objects are realized inside the\n> > code are:\n> > * mps2_common_init()\n> > * netduino2_init()\n> > * stm32f205_soc_realize()\n> > * armv7m_init()\n> > Those functions always set the \"cpu-model\" property immediately\n> > before realize.\n> > \n> > This means any value set by the user (e.g. using -global) would\n> > be always overwritten before realize.\n> > \n> > However, I have a suggestion for Igor: making a separate patch\n> > that renames the existing property to \"x-cpu-model\", and using\n> > \"x-cpu-type\" in this series. This way we will explicitly\n> > document the fact that the property is not a stable\n> > user/management interface.\n> There is no much point in renaming to \"x-cpu-model\" as it will be deleted\n> right afterwards, I'd just delete \"cpu-model\" and use \"x-cpu-type\"\n> in this patch. I'm not a fun of 'x-' prefix and would prefer a flag\n> in property to mark it as internal. But it's out of scope of this series,\n> so I don't care much about naming at the moment and will use \"x-cpu-type\"\n> as you suggest.\n\nPeter pointed out that this is the case with lots of properties\non non-user-creatable devices. So we can keep \"cpu-type\" for\nconsistency by now.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ext-mx01.extmail.prod.ext.phx2.redhat.com;\n\tdmarc=none (p=none dis=none) header.from=redhat.com","ext-mx01.extmail.prod.ext.phx2.redhat.com;\n\tspf=fail smtp.mailfrom=ehabkost@redhat.com"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xs3MZ0FVJz9t2Q\n\tfor ;\n\tTue, 12 Sep 2017 22:02:47 +1000 (AEST)","from localhost ([::1]:35400 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1drjtt-00043b-JY\n\tfor incoming@patchwork.ozlabs.org; Tue, 12 Sep 2017 08:02:45 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:36314)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1drjtS-0003td-Sf\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 08:02:23 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1drjtM-0005Rm-Qx\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 08:02:18 -0400","from mx1.redhat.com ([209.132.183.28]:58374)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1drjtG-0005Le-6w; Tue, 12 Sep 2017 08:02:06 -0400","from smtp.corp.redhat.com\n\t(int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby mx1.redhat.com (Postfix) with ESMTPS id 9F86F81E0F;\n\tTue, 12 Sep 2017 12:02:04 +0000 (UTC)","from localhost (ovpn-116-15.gru2.redhat.com [10.97.116.15])\n\tby smtp.corp.redhat.com (Postfix) with ESMTP id AEF7017DEB;\n\tTue, 12 Sep 2017 12:01:55 +0000 (UTC)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mx1.redhat.com 9F86F81E0F","Date":"Tue, 12 Sep 2017 09:01:38 -0300","From":"Eduardo Habkost ","To":"Igor Mammedov ","Message-ID":"<20170912120138.GU7570@localhost.localdomain>","References":"<1504533662-198084-1-git-send-email-imammedo@redhat.com>\n\t<1504533662-198084-7-git-send-email-imammedo@redhat.com>\n\t<20170905213152.GG17184@localhost.localdomain>\n\t\n\t<20170905221226.GZ7570@localhost.localdomain>\n\t\n\t<20170909203014.GG7570@localhost.localdomain>\n\t<20170912122214.29f0840e@nial.brq.redhat.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170912122214.29f0840e@nial.brq.redhat.com>","X-Fnord":"you can see the fnord","User-Agent":"Mutt/1.8.3 (2017-05-23)","X-Scanned-By":"MIMEDefang 2.79 on 10.5.11.13","X-Greylist":"Sender IP whitelisted, not delayed by milter-greylist-4.5.16\n\t(mx1.redhat.com [10.5.110.25]);\n\tTue, 12 Sep 2017 12:02:05 +0000 (UTC)","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]","X-Received-From":"209.132.183.28","Subject":"Re: [Qemu-devel] [PATCH 6/6] arm: drop intermadiate cpu_model ->\n\tcpu type parsing and use cpu type directly","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Rob Herring , Andrew Jones ,\n\tPeter Maydell ,\n\tIgor Mitsyanko ,\n\tAlistair Francis ,\n\t\"qemu-devel@nongnu.org Developers\" ,\n\tqemu-arm , Jan Kiszka ,\n\t\"Edgar E. Iglesias\" ,\n\tAlistair Francis ,\n\tRichard Henderson ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1766931,"web_url":"http://patchwork.ozlabs.org/comment/1766931/","msgid":"<20170912120427.GV7570@localhost.localdomain>","list_archive_url":null,"date":"2017-09-12T12:04:27","subject":"Re: [Qemu-devel] [PATCH 6/6] arm: drop intermadiate cpu_model ->\n\tcpu type parsing and use cpu type directly","submitter":{"id":195,"url":"http://patchwork.ozlabs.org/api/people/195/","name":"Eduardo Habkost","email":"ehabkost@redhat.com"},"content":"On Tue, Sep 12, 2017 at 01:02:35PM +0200, Igor Mammedov wrote:\n> On Tue, 5 Sep 2017 14:47:52 -0700\n> Alistair Francis wrote:\n> \n> > On Tue, Sep 5, 2017 at 2:31 PM, Eduardo Habkost wrote:\n> > > On Mon, Sep 04, 2017 at 04:01:02PM +0200, Igor Mammedov wrote: \n> > >> there are 2 use cases to deal with:\n> > >> 1: fixed CPU models per board/soc\n> > >> 2: boards with user configurable cpu_model and fallback to\n> > >> default cpu_model if user hasn't specified one explicitly\n> > >>\n> > >> For the 1st\n> > >> drop intermediate cpu_model parsing and use const cpu type\n> > >> directly, which replaces:\n> > >> typename = object_class_get_name(\n> > >> cpu_class_by_name(TYPE_ARM_CPU, cpu_model))\n> > >> object_new(typename)\n> > >> with\n> > >> object_new(FOO_CPU_TYPE_NAME)\n> > >> or\n> > >> cpu_generic_init(BASE_CPU_TYPE, \"my cpu model\")\n> > >> with\n> > >> cpu_create(FOO_CPU_TYPE_NAME)\n> > >>\n> > >> as result 1st use case doesn't have to invoke not necessary\n> > >> translation and not needed code is removed.\n> > >>\n> > >> For the 2nd\n> > >> 1: set default cpu type with MachineClass::default_cpu_type and\n> > >> 2: use generic cpu_model parsing that done before machine_init()\n> > >> is run and:\n> > >> 2.1: drop custom cpu_model parsing where pattern is:\n> > >> typename = object_class_get_name(\n> > >> cpu_class_by_name(TYPE_ARM_CPU, cpu_model))\n> > >> [parse_features(typename, cpu_model, &err) ]\n> > >>\n> > >> 2.2: or replace cpu_generic_init() which does what\n> > >> 2.1 does + create_cpu(typename) with just\n> > >> create_cpu(machine->cpu_type)\n> > >> as result cpu_name -> cpu_type translation is done using\n> > >> generic machine code one including parsing optional features\n> > >> if supported/present (removes a bunch of duplicated cpu_model\n> > >> parsing code) and default cpu type is defined in an uniform way\n> > >> within machine_class_init callbacks instead of adhoc places\n> > >> in boadr's machine_init code.\n> > >>\n> > >> Signed-off-by: Igor Mammedov \n> > >> ---\n> > >> CC: Peter Maydell \n> > >> CC: Igor Mitsyanko \n> > >> CC: Rob Herring \n> > >> CC: Andrzej Zaborowski \n> > >> CC: Jan Kiszka \n> > >> CC: Alistair Francis \n> > >> CC: \"Edgar E. Iglesias\" \n> > >> CC: qemu-arm@nongnu.org\n> > >> ---\n> \n> [...]\n> \n> > >>\n> > >> static const TypeInfo lm3s6965evb_type = {\n> > >> diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c\n> > >> index f61e735..1cd6374 100644\n> > >> --- a/hw/arm/stm32f205_soc.c\n> > >> +++ b/hw/arm/stm32f205_soc.c\n> > >> @@ -112,7 +112,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)\n> > >>\n> > >> armv7m = DEVICE(&s->armv7m);\n> > >> qdev_prop_set_uint32(armv7m, \"num-irq\", 96);\n> > >> - qdev_prop_set_string(armv7m, \"cpu-model\", s->cpu_model);\n> > >> + qdev_prop_set_string(armv7m, \"cpu-type\", s->cpu_type);\n> > >> object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),\n> > >> \"memory\", &error_abort);\n> > >> object_property_set_bool(OBJECT(&s->armv7m), true, \"realized\", &err);\n> > >> @@ -200,7 +200,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)\n> > >> }\n> > >>\n> > >> static Property stm32f205_soc_properties[] = {\n> > >> - DEFINE_PROP_STRING(\"cpu-model\", STM32F205State, cpu_model),\n> > >> + DEFINE_PROP_STRING(\"cpu-type\", STM32F205State, cpu_type), \n> > >\n> > > Same as armv7m: are we 100% sure users are not setting this\n> > > manually? \n> > \n> > In an embedded board like this it really doesn't make sense to let the\n> > user overwrite the CPU. The SoC will take it as an option, but the\n> > board (which creates the SoC) just blindly always uses the same CPU.\n> > That feature is more for QOMificatoion then any real reason though.\n> If SoC has fixed cpu type then I'd drop property.\n> I'd leave it upto board maintainers to cleanup not really needed\n> properties and make soc with fixed cpu type where it makes sense.\n> \n> > In saying that I think a warning if the user tries to set the CPU\n> > would make sense. I know that this issues comes up in other ARM boards\n> > (Zynq-7000 has the same issue as well) so maybe a machine property\n> > saying that the board doesn't accept custom CPUs would be a good idea.\n> > \n> > Overall I think this patch is moving in the right direction though and\n> > this CPU option being ignored existed before this series.\n> right, this series just removes cpu_generic_init()/cpu_model in boards\n> everything else should be done as separate series.\n\nAgreed. Except for actual bugs and opportunities to document\nthese cases in comments or commit messages, these things can be\ndone by other series.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ext-mx01.extmail.prod.ext.phx2.redhat.com;\n\tdmarc=none (p=none dis=none) header.from=redhat.com","ext-mx01.extmail.prod.ext.phx2.redhat.com;\n\tspf=fail smtp.mailfrom=ehabkost@redhat.com"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xs3QF12dlz9s7M\n\tfor ;\n\tTue, 12 Sep 2017 22:05:09 +1000 (AEST)","from localhost ([::1]:35411 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1drjwB-0004vG-Ag\n\tfor incoming@patchwork.ozlabs.org; Tue, 12 Sep 2017 08:05:07 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:37104)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1drjvh-0004oY-4Z\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 08:04:41 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1drjvf-0007nK-OI\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 08:04:37 -0400","from mx1.redhat.com ([209.132.183.28]:17387)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1drjvZ-0007h7-PE; Tue, 12 Sep 2017 08:04:29 -0400","from smtp.corp.redhat.com\n\t(int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby mx1.redhat.com (Postfix) with ESMTPS id BE20881E0E;\n\tTue, 12 Sep 2017 12:04:28 +0000 (UTC)","from localhost (ovpn-116-15.gru2.redhat.com [10.97.116.15])\n\tby smtp.corp.redhat.com (Postfix) with ESMTP id 3B1AF6F920;\n\tTue, 12 Sep 2017 12:04:28 +0000 (UTC)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mx1.redhat.com BE20881E0E","Date":"Tue, 12 Sep 2017 09:04:27 -0300","From":"Eduardo Habkost ","To":"Igor Mammedov ","Message-ID":"<20170912120427.GV7570@localhost.localdomain>","References":"<1504533662-198084-1-git-send-email-imammedo@redhat.com>\n\t<1504533662-198084-7-git-send-email-imammedo@redhat.com>\n\t<20170905213152.GG17184@localhost.localdomain>\n\t\n\t<20170912130235.2353dec3@nial.brq.redhat.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170912130235.2353dec3@nial.brq.redhat.com>","X-Fnord":"you can see the fnord","User-Agent":"Mutt/1.8.3 (2017-05-23)","X-Scanned-By":"MIMEDefang 2.79 on 10.5.11.11","X-Greylist":"Sender IP whitelisted, not delayed by milter-greylist-4.5.16\n\t(mx1.redhat.com [10.5.110.25]);\n\tTue, 12 Sep 2017 12:04:28 +0000 (UTC)","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]","X-Received-From":"209.132.183.28","Subject":"Re: [Qemu-devel] [PATCH 6/6] arm: drop intermadiate cpu_model ->\n\tcpu type parsing and use cpu type directly","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Peter Maydell ,\n\tAndrew Jones , \n\tRob Herring , Igor Mitsyanko ,\n\tAlistair Francis ,\n\t\"qemu-devel@nongnu.org Developers\" ,\n\tqemu-arm , Jan Kiszka ,\n\t\"Edgar E. Iglesias\" ,\n\tAlistair Francis ,\n\tRichard Henderson ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1766936,"web_url":"http://patchwork.ozlabs.org/comment/1766936/","msgid":"<20170912141159.22c63bce@nial.brq.redhat.com>","list_archive_url":null,"date":"2017-09-12T12:11:59","subject":"Re: [Qemu-devel] [PATCH 6/6] arm: drop intermadiate cpu_model ->\n\tcpu type parsing and use cpu type directly","submitter":{"id":11305,"url":"http://patchwork.ozlabs.org/api/people/11305/","name":"Igor Mammedov","email":"imammedo@redhat.com"},"content":"On Tue, 5 Sep 2017 18:31:52 -0300\nEduardo Habkost wrote:\n\n> On Mon, Sep 04, 2017 at 04:01:02PM +0200, Igor Mammedov wrote:\n> > there are 2 use cases to deal with:\n> > 1: fixed CPU models per board/soc\n> > 2: boards with user configurable cpu_model and fallback to\n> > default cpu_model if user hasn't specified one explicitly\n> > \n> > For the 1st\n> > drop intermediate cpu_model parsing and use const cpu type\n> > directly, which replaces:\n> > typename = object_class_get_name(\n> > cpu_class_by_name(TYPE_ARM_CPU, cpu_model))\n> > object_new(typename)\n> > with\n> > object_new(FOO_CPU_TYPE_NAME)\n> > or\n> > cpu_generic_init(BASE_CPU_TYPE, \"my cpu model\")\n> > with\n> > cpu_create(FOO_CPU_TYPE_NAME)\n> > \n> > as result 1st use case doesn't have to invoke not necessary\n> > translation and not needed code is removed.\n> > \n> > For the 2nd\n> > 1: set default cpu type with MachineClass::default_cpu_type and\n> > 2: use generic cpu_model parsing that done before machine_init()\n> > is run and:\n> > 2.1: drop custom cpu_model parsing where pattern is:\n> > typename = object_class_get_name(\n> > cpu_class_by_name(TYPE_ARM_CPU, cpu_model))\n> > [parse_features(typename, cpu_model, &err) ]\n> > \n> > 2.2: or replace cpu_generic_init() which does what\n> > 2.1 does + create_cpu(typename) with just\n> > create_cpu(machine->cpu_type)\n> > as result cpu_name -> cpu_type translation is done using\n> > generic machine code one including parsing optional features\n> > if supported/present (removes a bunch of duplicated cpu_model\n> > parsing code) and default cpu type is defined in an uniform way\n> > within machine_class_init callbacks instead of adhoc places\n> > in boadr's machine_init code.\n> > \n> > Signed-off-by: Igor Mammedov \n> > ---\n[...]\n\n> > @@ -285,20 +259,16 @@ static void armv7m_reset(void *opaque)\n> > Returns the ARMv7M device. */\n> > \n> > DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,\n> > - const char *kernel_filename, const char *cpu_model)\n> > + const char *kernel_filename, const char *cpu_type)\n> > {\n> > DeviceState *armv7m;\n> > \n> > - if (cpu_model == NULL) {\n> > - cpu_model = \"cortex-m3\";\n> > - }\n> > - \n> \n> I was going to suggest doing the default_cpu_type stuff in a\n> separate patch, but it might require touching those lines twice.\n> So I guess this is OK.\nI've have tried it, but yes it's more changes and there is also\nchicken/egg problem, cleanest way I've stopped at is to get rid of\ncpu_model fallback + cpu_generic_init() in one go.\n\n \n> > armv7m = qdev_create(NULL, \"armv7m\");\n> > qdev_prop_set_uint32(armv7m, \"num-irq\", num_irq);\n> > - qdev_prop_set_string(armv7m, \"cpu-model\", cpu_model);\n> > + qdev_prop_set_string(armv7m, \"cpu-type\", cpu_type);\n> > object_property_set_link(OBJECT(armv7m), OBJECT(get_system_memory()),\n> > \"memory\", &error_abort);\n> > - /* This will exit with an error if the user passed us a bad cpu_model */\n> > + /* This will exit with an error if the user passed us a bad cpu_type */\n> > qdev_init_nofail(armv7m);\n> > \n> > armv7m_load_kernel(ARM_CPU(first_cpu), kernel_filename, mem_size);\n[...]\n\n> > diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c\n> > index 20e60f1..0d7190a 100644\n> > --- a/hw/arm/highbank.c\n> > +++ b/hw/arm/highbank.c\n> > @@ -219,7 +219,6 @@ enum cxmachines {\n> > static void calxeda_init(MachineState *machine, enum cxmachines machine_id)\n> > {\n> > ram_addr_t ram_size = machine->ram_size;\n> > - const char *cpu_model = machine->cpu_model;\n> > const char *kernel_filename = machine->kernel_filename;\n> > const char *kernel_cmdline = machine->kernel_cmdline;\n> > const char *initrd_filename = machine->initrd_filename;\n> > @@ -236,19 +235,20 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id)\n> > \n> > switch (machine_id) {\n> > case CALXEDA_HIGHBANK:\n> > - cpu_model = \"cortex-a9\";\n> > + machine->cpu_type = ARM_CPU_TYPE_NAME(\"cortex-a9\");\n> > break;\n> > case CALXEDA_MIDWAY:\n> > - cpu_model = \"cortex-a15\";\n> > + machine->cpu_type = ARM_CPU_TYPE_NAME(\"cortex-a15\");\n> > break;\n> > + default:\n> > + assert(0);\n> > } \n> \n> Why not delete this switch statement completely and set\n> default_cpu_type at midway_class_init() and\n> highbank_class_init()?\nit would allow '-cpu foo' to take effect which isn't what current code does,\nas series doesn't add valid_cpus[] check at the same time.\n\nSo here we do pretty much strait-forward conversion from cpu_model\nto cpu_type and nothing else.\n\n> \n> \n> > \n> > for (n = 0; n < smp_cpus; n++) {\n> > - ObjectClass *oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);\n> > Object *cpuobj;\n> > ARMCPU *cpu;\n> > \n> > - cpuobj = object_new(object_class_get_name(oc));\n> > + cpuobj = object_new(machine->cpu_type);\n> > cpu = ARM_CPU(cpuobj);\n> > \n> > object_property_set_int(cpuobj, QEMU_PSCI_CONDUIT_SMC,\n[...]\n\n> > diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c\n> > index c16657d..79b317a 100644\n> > --- a/hw/arm/pxa2xx.c\n> > +++ b/hw/arm/pxa2xx.c\n> > @@ -2052,21 +2052,19 @@ static void pxa2xx_reset(void *opaque, int line, int level)\n> > \n> > /* Initialise a PXA270 integrated chip (ARM based core). */\n> > PXA2xxState *pxa270_init(MemoryRegion *address_space,\n> > - unsigned int sdram_size, const char *revision)\n> > + unsigned int sdram_size, const char *cpu_type)\n> > {\n> > PXA2xxState *s;\n> > int i;\n> > DriveInfo *dinfo;\n> > s = g_new0(PXA2xxState, 1);\n> > \n> > - if (revision && strncmp(revision, \"pxa27\", 5)) {\n> > + if (strncmp(cpu_type, ARM_CPU_TYPE_NAME(\"pxa27\"), 5)) { \n> \n> Why are you using ARM_CPU_TYPE_NAME here, if you are only\n> checking if cpu_type starts with \"pxa27\"?\nmainly to show that we are dealing with types here,\nI can leave plain \"pxa27\" if you prefer.\n\n\n> I suggest adding a TODO here noting that we implement this using\n> either a TYPE_ARM_PXA27 subclass (so we can use\n> object_class_dynamic_cast()), or a ARMCPUClass field to identify\n> if the CPU is pxa27.\ndynamic cast would be nice, but (\"pxa27\", 5) cover a range of cpu types\nstarting with this prefix, to use cast class structure should be reorganized\nto make all pxa27 based cpus have a common pxa27 ancestor.\nOr just use more verbose complete list of valid_cpus[]\n\nIt's out of scope of this patch including TODO comment,\nall boards should be audited anyways to make proper use of valid_cpus[]\nand adding not related TODO comments here doesn't seem right.\n\n\n> > fprintf(stderr, \"Machine requires a PXA27x processor.\\n\");\n> > exit(1);\n> > } \n> \n> This would be another use case for a generic CPU model validation\n> mechanism in MachineClass.\nyep, just applied to a range of cpus instead of typical leaf class.\n\n[...]\n\n> > diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c\n> > index c1145dd..3d1a231 100644\n> > --- a/hw/arm/strongarm.c\n> > +++ b/hw/arm/strongarm.c\n> > @@ -1581,23 +1581,19 @@ static const TypeInfo strongarm_ssp_info = {\n> > \n> > /* Main CPU functions */\n> > StrongARMState *sa1110_init(MemoryRegion *sysmem,\n> > - unsigned int sdram_size, const char *rev)\n> > + unsigned int sdram_size, const char *cpu_type)\n> > {\n> > StrongARMState *s;\n> > int i;\n> > \n> > s = g_new0(StrongARMState, 1);\n> > \n> > - if (!rev) {\n> > - rev = \"sa1110-b5\";\n> > - }\n> > -\n> > - if (strncmp(rev, \"sa1110\", 6)) {\n> > + if (strncmp(cpu_type, \"sa1110\", 6)) {\n> > error_report(\"Machine requires a SA1110 processor.\");\n> > exit(1); \n> \n> Same suggestion as on pxa270_init(): adding a TODO here noting\n> that we implement this using either object_class_dynamic_cast(),\n> or a ARMCPUClass field to identify if the CPU is sa1110.\nsame as pxa27, it's a case of range of cpus,\nTODO is orthogonal to patch topic, so I'd prefer not to add it here.\n\n> \n> \n> > }\n> > \n> > - s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, rev));\n> > + s->cpu = ARM_CPU(cpu_create(cpu_type));\n> > \n> > memory_region_allocate_system_memory(&s->sdram, NULL, \"strongarm.sdram\",\n> > sdram_size);\n> > diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c\n> > index 8b757ff..75631f6 100644\n> > --- a/hw/arm/tosa.c\n> > +++ b/hw/arm/tosa.c\n> > @@ -219,7 +219,6 @@ static struct arm_boot_info tosa_binfo = {\n> > \n> > static void tosa_init(MachineState *machine)\n> > {\n> > - const char *cpu_model = machine->cpu_model;\n> > const char *kernel_filename = machine->kernel_filename;\n> > const char *kernel_cmdline = machine->kernel_cmdline;\n> > const char *initrd_filename = machine->initrd_filename;\n> > @@ -229,9 +228,6 @@ static void tosa_init(MachineState *machine)\n> > TC6393xbState *tmio;\n> > DeviceState *scp0, *scp1;\n> > \n> > - if (!cpu_model)\n> > - cpu_model = \"pxa255\";\n> > - \n> \n> Don't we need to set mc->default_cpu_type at\n> tosapda_machine_init() to replace this?\nboard doesn't actually take user input and above remove code does nothing,\nlook into pxa255_init() where it uses hardcoded cpu model\n cpu_generic_init(TYPE_ARM_CPU, \"pxa255\")\n\nanother user connex_init() of pxa255_init() were already cleaned up\nor didn't have junk to begin with\n\n> > mpu = pxa255_init(address_space_mem, tosa_binfo.ram_size);\n> > \n> > memory_region_init_ram(rom, NULL, \"tosa.rom\", TOSA_ROM, &error_fatal);\n[...]\n\n> > diff --git a/target/arm/cpu.c b/target/arm/cpu.c\n> > index 05c038b..feeeeb2 100644\n> > --- a/target/arm/cpu.c\n> > +++ b/target/arm/cpu.c\n> > @@ -867,7 +867,7 @@ static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)\n> > }\n> > \n> > cpuname = g_strsplit(cpu_model, \",\", 1);\n> > - typename = g_strdup_printf(\"%s-\" TYPE_ARM_CPU, cpuname[0]);\n> > + typename = g_strdup_printf(\"%s\" ARM_CPU_TYPE_SUFFIX, cpuname[0]); \n> \n> What about doing the same we do in x86 and s390:\n> \n> g_strdup_printf(ARM_CPU_TYPE_NAME(\"%s\"), cpuname[0]);\nsure\n\n> \n> > oc = object_class_by_name(typename);\n> > g_strfreev(cpuname);\n> > g_free(typename);\n> > -- \n> > 2.7.4\n> > \n> > \n> \n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ext-mx03.extmail.prod.ext.phx2.redhat.com;\n\tdmarc=none (p=none dis=none) header.from=redhat.com","ext-mx03.extmail.prod.ext.phx2.redhat.com;\n\tspf=fail smtp.mailfrom=imammedo@redhat.com"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xs3bB0nN1z9s5L\n\tfor ;\n\tTue, 12 Sep 2017 22:12:52 +1000 (AEST)","from localhost ([::1]:35473 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1drk3d-0008I8-JR\n\tfor incoming@patchwork.ozlabs.org; Tue, 12 Sep 2017 08:12:49 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:40005)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1drk3D-0008Co-1H\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 08:12:29 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1drk38-0007cb-TT\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 08:12:22 -0400","from mx1.redhat.com ([209.132.183.28]:34332)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1drk2u-0007QW-VB; Tue, 12 Sep 2017 08:12:05 -0400","from smtp.corp.redhat.com\n\t(int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby mx1.redhat.com (Postfix) with ESMTPS id ED24083F3D;\n\tTue, 12 Sep 2017 12:12:03 +0000 (UTC)","from nial.brq.redhat.com (unknown [10.43.2.209])\n\tby smtp.corp.redhat.com (Postfix) with ESMTP id B84B66F9D3;\n\tTue, 12 Sep 2017 12:12:01 +0000 (UTC)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mx1.redhat.com ED24083F3D","Date":"Tue, 12 Sep 2017 14:11:59 +0200","From":"Igor Mammedov ","To":"Eduardo Habkost ","Message-ID":"<20170912141159.22c63bce@nial.brq.redhat.com>","In-Reply-To":"<20170905213152.GG17184@localhost.localdomain>","References":"<1504533662-198084-1-git-send-email-imammedo@redhat.com>\n\t<1504533662-198084-7-git-send-email-imammedo@redhat.com>\n\t<20170905213152.GG17184@localhost.localdomain>","MIME-Version":"1.0","Content-Type":"text/plain; charset=US-ASCII","Content-Transfer-Encoding":"7bit","X-Scanned-By":"MIMEDefang 2.79 on 10.5.11.15","X-Greylist":"Sender IP whitelisted, not delayed by milter-greylist-4.5.16\n\t(mx1.redhat.com [10.5.110.27]);\n\tTue, 12 Sep 2017 12:12:04 +0000 (UTC)","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]","X-Received-From":"209.132.183.28","Subject":"Re: [Qemu-devel] [PATCH 6/6] arm: drop intermadiate cpu_model ->\n\tcpu type parsing and use cpu type directly","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Peter Maydell ,\n\tAndrew Jones , \n\tRob Herring , Igor Mitsyanko ,\n\tAlistair Francis , qemu-devel@nongnu.org,\n\tqemu-arm@nongnu.org, Jan Kiszka ,\n\t\"Edgar E. Iglesias\" ,\n\tRichard Henderson ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1766996,"web_url":"http://patchwork.ozlabs.org/comment/1766996/","msgid":"<20170912125322.GW7570@localhost.localdomain>","list_archive_url":null,"date":"2017-09-12T12:53:22","subject":"Re: [Qemu-devel] [PATCH 6/6] arm: drop intermadiate cpu_model ->\n\tcpu type parsing and use cpu type directly","submitter":{"id":195,"url":"http://patchwork.ozlabs.org/api/people/195/","name":"Eduardo Habkost","email":"ehabkost@redhat.com"},"content":"On Tue, Sep 12, 2017 at 02:11:59PM +0200, Igor Mammedov wrote:\n> On Tue, 5 Sep 2017 18:31:52 -0300\n> Eduardo Habkost wrote:\n> \n> > On Mon, Sep 04, 2017 at 04:01:02PM +0200, Igor Mammedov wrote:\n> > > there are 2 use cases to deal with:\n> > > 1: fixed CPU models per board/soc\n> > > 2: boards with user configurable cpu_model and fallback to\n> > > default cpu_model if user hasn't specified one explicitly\n> > > \n> > > For the 1st\n> > > drop intermediate cpu_model parsing and use const cpu type\n> > > directly, which replaces:\n> > > typename = object_class_get_name(\n> > > cpu_class_by_name(TYPE_ARM_CPU, cpu_model))\n> > > object_new(typename)\n> > > with\n> > > object_new(FOO_CPU_TYPE_NAME)\n> > > or\n> > > cpu_generic_init(BASE_CPU_TYPE, \"my cpu model\")\n> > > with\n> > > cpu_create(FOO_CPU_TYPE_NAME)\n> > > \n> > > as result 1st use case doesn't have to invoke not necessary\n> > > translation and not needed code is removed.\n> > > \n> > > For the 2nd\n> > > 1: set default cpu type with MachineClass::default_cpu_type and\n> > > 2: use generic cpu_model parsing that done before machine_init()\n> > > is run and:\n> > > 2.1: drop custom cpu_model parsing where pattern is:\n> > > typename = object_class_get_name(\n> > > cpu_class_by_name(TYPE_ARM_CPU, cpu_model))\n> > > [parse_features(typename, cpu_model, &err) ]\n> > > \n> > > 2.2: or replace cpu_generic_init() which does what\n> > > 2.1 does + create_cpu(typename) with just\n> > > create_cpu(machine->cpu_type)\n> > > as result cpu_name -> cpu_type translation is done using\n> > > generic machine code one including parsing optional features\n> > > if supported/present (removes a bunch of duplicated cpu_model\n> > > parsing code) and default cpu type is defined in an uniform way\n> > > within machine_class_init callbacks instead of adhoc places\n> > > in boadr's machine_init code.\n> > > \n> > > Signed-off-by: Igor Mammedov \n> > > ---\n> [...]\n> \n> > > @@ -285,20 +259,16 @@ static void armv7m_reset(void *opaque)\n> > > Returns the ARMv7M device. */\n> > > \n> > > DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,\n> > > - const char *kernel_filename, const char *cpu_model)\n> > > + const char *kernel_filename, const char *cpu_type)\n> > > {\n> > > DeviceState *armv7m;\n> > > \n> > > - if (cpu_model == NULL) {\n> > > - cpu_model = \"cortex-m3\";\n> > > - }\n> > > - \n> > \n> > I was going to suggest doing the default_cpu_type stuff in a\n> > separate patch, but it might require touching those lines twice.\n> > So I guess this is OK.\n> I've have tried it, but yes it's more changes and there is also\n> chicken/egg problem, cleanest way I've stopped at is to get rid of\n> cpu_model fallback + cpu_generic_init() in one go.\n\nOK\n\n> \n> \n> > > armv7m = qdev_create(NULL, \"armv7m\");\n> > > qdev_prop_set_uint32(armv7m, \"num-irq\", num_irq);\n> > > - qdev_prop_set_string(armv7m, \"cpu-model\", cpu_model);\n> > > + qdev_prop_set_string(armv7m, \"cpu-type\", cpu_type);\n> > > object_property_set_link(OBJECT(armv7m), OBJECT(get_system_memory()),\n> > > \"memory\", &error_abort);\n> > > - /* This will exit with an error if the user passed us a bad cpu_model */\n> > > + /* This will exit with an error if the user passed us a bad cpu_type */\n> > > qdev_init_nofail(armv7m);\n> > > \n> > > armv7m_load_kernel(ARM_CPU(first_cpu), kernel_filename, mem_size);\n> [...]\n> \n> > > diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c\n> > > index 20e60f1..0d7190a 100644\n> > > --- a/hw/arm/highbank.c\n> > > +++ b/hw/arm/highbank.c\n> > > @@ -219,7 +219,6 @@ enum cxmachines {\n> > > static void calxeda_init(MachineState *machine, enum cxmachines machine_id)\n> > > {\n> > > ram_addr_t ram_size = machine->ram_size;\n> > > - const char *cpu_model = machine->cpu_model;\n> > > const char *kernel_filename = machine->kernel_filename;\n> > > const char *kernel_cmdline = machine->kernel_cmdline;\n> > > const char *initrd_filename = machine->initrd_filename;\n> > > @@ -236,19 +235,20 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id)\n> > > \n> > > switch (machine_id) {\n> > > case CALXEDA_HIGHBANK:\n> > > - cpu_model = \"cortex-a9\";\n> > > + machine->cpu_type = ARM_CPU_TYPE_NAME(\"cortex-a9\");\n> > > break;\n> > > case CALXEDA_MIDWAY:\n> > > - cpu_model = \"cortex-a15\";\n> > > + machine->cpu_type = ARM_CPU_TYPE_NAME(\"cortex-a15\");\n> > > break;\n> > > + default:\n> > > + assert(0);\n> > > } \n> > \n> > Why not delete this switch statement completely and set\n> > default_cpu_type at midway_class_init() and\n> > highbank_class_init()?\n> it would allow '-cpu foo' to take effect which isn't what current code does,\n> as series doesn't add valid_cpus[] check at the same time.\n\nOh, I see.\n\n\n> \n> So here we do pretty much strait-forward conversion from cpu_model\n> to cpu_type and nothing else.\n\nOK.\n\n> \n> > \n> > \n> > > \n> > > for (n = 0; n < smp_cpus; n++) {\n> > > - ObjectClass *oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);\n> > > Object *cpuobj;\n> > > ARMCPU *cpu;\n> > > \n> > > - cpuobj = object_new(object_class_get_name(oc));\n> > > + cpuobj = object_new(machine->cpu_type);\n> > > cpu = ARM_CPU(cpuobj);\n> > > \n> > > object_property_set_int(cpuobj, QEMU_PSCI_CONDUIT_SMC,\n> [...]\n> \n> > > diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c\n> > > index c16657d..79b317a 100644\n> > > --- a/hw/arm/pxa2xx.c\n> > > +++ b/hw/arm/pxa2xx.c\n> > > @@ -2052,21 +2052,19 @@ static void pxa2xx_reset(void *opaque, int line, int level)\n> > > \n> > > /* Initialise a PXA270 integrated chip (ARM based core). */\n> > > PXA2xxState *pxa270_init(MemoryRegion *address_space,\n> > > - unsigned int sdram_size, const char *revision)\n> > > + unsigned int sdram_size, const char *cpu_type)\n> > > {\n> > > PXA2xxState *s;\n> > > int i;\n> > > DriveInfo *dinfo;\n> > > s = g_new0(PXA2xxState, 1);\n> > > \n> > > - if (revision && strncmp(revision, \"pxa27\", 5)) {\n> > > + if (strncmp(cpu_type, ARM_CPU_TYPE_NAME(\"pxa27\"), 5)) { \n> > \n> > Why are you using ARM_CPU_TYPE_NAME here, if you are only\n> > checking if cpu_type starts with \"pxa27\"?\n> mainly to show that we are dealing with types here,\n> I can leave plain \"pxa27\" if you prefer.\n\nConsidering that we're dealing with a strncmp() hack that needs\nARM_CPU_TYPE_NAME to work in a very specific way, I would prefer\nto leave the actual argument to strncmp() explicitly visible,\nuntil we implement another solution.\n\n> \n> \n> > I suggest adding a TODO here noting that we implement this using\n> > either a TYPE_ARM_PXA27 subclass (so we can use\n> > object_class_dynamic_cast()), or a ARMCPUClass field to identify\n> > if the CPU is pxa27.\n> dynamic cast would be nice, but (\"pxa27\", 5) cover a range of cpu types\n> starting with this prefix, to use cast class structure should be reorganized\n> to make all pxa27 based cpus have a common pxa27 ancestor.\n> Or just use more verbose complete list of valid_cpus[]\n> \n> It's out of scope of this patch including TODO comment,\n> all boards should be audited anyways to make proper use of valid_cpus[]\n> and adding not related TODO comments here doesn't seem right.\n\nTrue, now we have the plan of adding valid_cpus[], and this would\naffect lots of other boards. I won't mind if you prefer to not\nadd the TODO comment on this series.\n\n> \n> \n> > > fprintf(stderr, \"Machine requires a PXA27x processor.\\n\");\n> > > exit(1);\n> > > } \n> > \n> > This would be another use case for a generic CPU model validation\n> > mechanism in MachineClass.\n> yep, just applied to a range of cpus instead of typical leaf class.\n> \n> [...]\n> \n> > > diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c\n> > > index c1145dd..3d1a231 100644\n> > > --- a/hw/arm/strongarm.c\n> > > +++ b/hw/arm/strongarm.c\n> > > @@ -1581,23 +1581,19 @@ static const TypeInfo strongarm_ssp_info = {\n> > > \n> > > /* Main CPU functions */\n> > > StrongARMState *sa1110_init(MemoryRegion *sysmem,\n> > > - unsigned int sdram_size, const char *rev)\n> > > + unsigned int sdram_size, const char *cpu_type)\n> > > {\n> > > StrongARMState *s;\n> > > int i;\n> > > \n> > > s = g_new0(StrongARMState, 1);\n> > > \n> > > - if (!rev) {\n> > > - rev = \"sa1110-b5\";\n> > > - }\n> > > -\n> > > - if (strncmp(rev, \"sa1110\", 6)) {\n> > > + if (strncmp(cpu_type, \"sa1110\", 6)) {\n> > > error_report(\"Machine requires a SA1110 processor.\");\n> > > exit(1); \n> > \n> > Same suggestion as on pxa270_init(): adding a TODO here noting\n> > that we implement this using either object_class_dynamic_cast(),\n> > or a ARMCPUClass field to identify if the CPU is sa1110.\n> same as pxa27, it's a case of range of cpus,\n> TODO is orthogonal to patch topic, so I'd prefer not to add it here.\n\nOK\n\n> \n> > \n> > \n> > > }\n> > > \n> > > - s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, rev));\n> > > + s->cpu = ARM_CPU(cpu_create(cpu_type));\n> > > \n> > > memory_region_allocate_system_memory(&s->sdram, NULL, \"strongarm.sdram\",\n> > > sdram_size);\n> > > diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c\n> > > index 8b757ff..75631f6 100644\n> > > --- a/hw/arm/tosa.c\n> > > +++ b/hw/arm/tosa.c\n> > > @@ -219,7 +219,6 @@ static struct arm_boot_info tosa_binfo = {\n> > > \n> > > static void tosa_init(MachineState *machine)\n> > > {\n> > > - const char *cpu_model = machine->cpu_model;\n> > > const char *kernel_filename = machine->kernel_filename;\n> > > const char *kernel_cmdline = machine->kernel_cmdline;\n> > > const char *initrd_filename = machine->initrd_filename;\n> > > @@ -229,9 +228,6 @@ static void tosa_init(MachineState *machine)\n> > > TC6393xbState *tmio;\n> > > DeviceState *scp0, *scp1;\n> > > \n> > > - if (!cpu_model)\n> > > - cpu_model = \"pxa255\";\n> > > - \n> > \n> > Don't we need to set mc->default_cpu_type at\n> > tosapda_machine_init() to replace this?\n> board doesn't actually take user input and above remove code does nothing,\n> look into pxa255_init() where it uses hardcoded cpu model\n> cpu_generic_init(TYPE_ARM_CPU, \"pxa255\")\n> \n> another user connex_init() of pxa255_init() were already cleaned up\n> or didn't have junk to begin with\n\nYou are right, I didn't notice cpu_model was an unused variable.\n\n> \n> > > mpu = pxa255_init(address_space_mem, tosa_binfo.ram_size);\n> > > \n> > > memory_region_init_ram(rom, NULL, \"tosa.rom\", TOSA_ROM, &error_fatal);\n> [...]\n> \n> > > diff --git a/target/arm/cpu.c b/target/arm/cpu.c\n> > > index 05c038b..feeeeb2 100644\n> > > --- a/target/arm/cpu.c\n> > > +++ b/target/arm/cpu.c\n> > > @@ -867,7 +867,7 @@ static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)\n> > > }\n> > > \n> > > cpuname = g_strsplit(cpu_model, \",\", 1);\n> > > - typename = g_strdup_printf(\"%s-\" TYPE_ARM_CPU, cpuname[0]);\n> > > + typename = g_strdup_printf(\"%s\" ARM_CPU_TYPE_SUFFIX, cpuname[0]); \n> > \n> > What about doing the same we do in x86 and s390:\n> > \n> > g_strdup_printf(ARM_CPU_TYPE_NAME(\"%s\"), cpuname[0]);\n> sure\n> \n\nI think this and the strncmp() line are the only suggestions that\nI'm still keeping. But they shouldn't block the series, so:\n\nReviewed-by: Eduardo Habkost ","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=208.118.235.17; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ext-mx06.extmail.prod.ext.phx2.redhat.com;\n\tdmarc=none (p=none dis=none) header.from=redhat.com","ext-mx06.extmail.prod.ext.phx2.redhat.com;\n\tspf=fail smtp.mailfrom=ehabkost@redhat.com"],"Received":["from lists.gnu.org (lists.gnu.org [208.118.235.17])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xs4cm4bjnz9rxl\n\tfor ;\n\tTue, 12 Sep 2017 22:59:20 +1000 (AEST)","from localhost ([::1]:35683 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1drkmc-0002Ca-L7\n\tfor incoming@patchwork.ozlabs.org; Tue, 12 Sep 2017 08:59:18 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:54804)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1drkh2-00068g-5b\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 08:53:34 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1drkh0-0002p5-4v\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 08:53:32 -0400","from mx1.redhat.com ([209.132.183.28]:43576)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1drkgv-0002mY-UE; Tue, 12 Sep 2017 08:53:26 -0400","from smtp.corp.redhat.com\n\t(int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby mx1.redhat.com (Postfix) with ESMTPS id DDE17356D6;\n\tTue, 12 Sep 2017 12:53:24 +0000 (UTC)","from localhost (ovpn-116-15.gru2.redhat.com [10.97.116.15])\n\tby smtp.corp.redhat.com (Postfix) with ESMTP id 3DD0E6F42B;\n\tTue, 12 Sep 2017 12:53:24 +0000 (UTC)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mx1.redhat.com DDE17356D6","Date":"Tue, 12 Sep 2017 09:53:22 -0300","From":"Eduardo Habkost ","To":"Igor Mammedov ","Message-ID":"<20170912125322.GW7570@localhost.localdomain>","References":"<1504533662-198084-1-git-send-email-imammedo@redhat.com>\n\t<1504533662-198084-7-git-send-email-imammedo@redhat.com>\n\t<20170905213152.GG17184@localhost.localdomain>\n\t<20170912141159.22c63bce@nial.brq.redhat.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170912141159.22c63bce@nial.brq.redhat.com>","X-Fnord":"you can see the fnord","User-Agent":"Mutt/1.8.3 (2017-05-23)","X-Scanned-By":"MIMEDefang 2.79 on 10.5.11.11","X-Greylist":"Sender IP whitelisted, not delayed by milter-greylist-4.5.16\n\t(mx1.redhat.com [10.5.110.30]);\n\tTue, 12 Sep 2017 12:53:25 +0000 (UTC)","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]","X-Received-From":"209.132.183.28","Subject":"Re: [Qemu-devel] [PATCH 6/6] arm: drop intermadiate cpu_model ->\n\tcpu type parsing and use cpu type directly","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Peter Maydell ,\n\tAndrew Jones , \n\tRob Herring , Igor Mitsyanko ,\n\tAlistair Francis , qemu-devel@nongnu.org,\n\tqemu-arm@nongnu.org, Jan Kiszka ,\n\t\"Edgar E. Iglesias\" ,\n\tRichard Henderson ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1767098,"web_url":"http://patchwork.ozlabs.org/comment/1767098/","msgid":"<20170912160629.7731bdbe@nial.brq.redhat.com>","list_archive_url":null,"date":"2017-09-12T14:06:29","subject":"Re: [Qemu-devel] [PATCH 6/6] arm: drop intermadiate cpu_model ->\n\tcpu type parsing and use cpu type directly","submitter":{"id":11305,"url":"http://patchwork.ozlabs.org/api/people/11305/","name":"Igor Mammedov","email":"imammedo@redhat.com"},"content":"On Tue, 12 Sep 2017 09:53:22 -0300\nEduardo Habkost wrote:\n\n> On Tue, Sep 12, 2017 at 02:11:59PM +0200, Igor Mammedov wrote:\n> > On Tue, 5 Sep 2017 18:31:52 -0300\n> > Eduardo Habkost wrote:\n> > \n> > > On Mon, Sep 04, 2017 at 04:01:02PM +0200, Igor Mammedov wrote: \n> > > > there are 2 use cases to deal with:\n> > > > 1: fixed CPU models per board/soc\n> > > > 2: boards with user configurable cpu_model and fallback to\n> > > > default cpu_model if user hasn't specified one explicitly\n> > > > \n> > > > For the 1st\n> > > > drop intermediate cpu_model parsing and use const cpu type\n> > > > directly, which replaces:\n> > > > typename = object_class_get_name(\n> > > > cpu_class_by_name(TYPE_ARM_CPU, cpu_model))\n> > > > object_new(typename)\n> > > > with\n> > > > object_new(FOO_CPU_TYPE_NAME)\n> > > > or\n> > > > cpu_generic_init(BASE_CPU_TYPE, \"my cpu model\")\n> > > > with\n> > > > cpu_create(FOO_CPU_TYPE_NAME)\n> > > > \n> > > > as result 1st use case doesn't have to invoke not necessary\n> > > > translation and not needed code is removed.\n> > > > \n> > > > For the 2nd\n> > > > 1: set default cpu type with MachineClass::default_cpu_type and\n> > > > 2: use generic cpu_model parsing that done before machine_init()\n> > > > is run and:\n> > > > 2.1: drop custom cpu_model parsing where pattern is:\n> > > > typename = object_class_get_name(\n> > > > cpu_class_by_name(TYPE_ARM_CPU, cpu_model))\n> > > > [parse_features(typename, cpu_model, &err) ]\n> > > > \n> > > > 2.2: or replace cpu_generic_init() which does what\n> > > > 2.1 does + create_cpu(typename) with just\n> > > > create_cpu(machine->cpu_type)\n> > > > as result cpu_name -> cpu_type translation is done using\n> > > > generic machine code one including parsing optional features\n> > > > if supported/present (removes a bunch of duplicated cpu_model\n> > > > parsing code) and default cpu type is defined in an uniform way\n> > > > within machine_class_init callbacks instead of adhoc places\n> > > > in boadr's machine_init code.\n> > > > \n> > > > Signed-off-by: Igor Mammedov \n> > > > --- \n> > [...]\n> > \n> > > > @@ -285,20 +259,16 @@ static void armv7m_reset(void *opaque)\n> > > > Returns the ARMv7M device. */\n> > > > \n> > > > DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,\n> > > > - const char *kernel_filename, const char *cpu_model)\n> > > > + const char *kernel_filename, const char *cpu_type)\n> > > > {\n> > > > DeviceState *armv7m;\n> > > > \n> > > > - if (cpu_model == NULL) {\n> > > > - cpu_model = \"cortex-m3\";\n> > > > - }\n> > > > - \n> > > \n> > > I was going to suggest doing the default_cpu_type stuff in a\n> > > separate patch, but it might require touching those lines twice.\n> > > So I guess this is OK. \n> > I've have tried it, but yes it's more changes and there is also\n> > chicken/egg problem, cleanest way I've stopped at is to get rid of\n> > cpu_model fallback + cpu_generic_init() in one go. \n> \n> OK\n> \n> > \n> > \n> > > > armv7m = qdev_create(NULL, \"armv7m\");\n> > > > qdev_prop_set_uint32(armv7m, \"num-irq\", num_irq);\n> > > > - qdev_prop_set_string(armv7m, \"cpu-model\", cpu_model);\n> > > > + qdev_prop_set_string(armv7m, \"cpu-type\", cpu_type);\n> > > > object_property_set_link(OBJECT(armv7m), OBJECT(get_system_memory()),\n> > > > \"memory\", &error_abort);\n> > > > - /* This will exit with an error if the user passed us a bad cpu_model */\n> > > > + /* This will exit with an error if the user passed us a bad cpu_type */\n> > > > qdev_init_nofail(armv7m);\n> > > > \n> > > > armv7m_load_kernel(ARM_CPU(first_cpu), kernel_filename, mem_size); \n> > [...]\n> > \n> > > > diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c\n> > > > index 20e60f1..0d7190a 100644\n> > > > --- a/hw/arm/highbank.c\n> > > > +++ b/hw/arm/highbank.c\n> > > > @@ -219,7 +219,6 @@ enum cxmachines {\n> > > > static void calxeda_init(MachineState *machine, enum cxmachines machine_id)\n> > > > {\n> > > > ram_addr_t ram_size = machine->ram_size;\n> > > > - const char *cpu_model = machine->cpu_model;\n> > > > const char *kernel_filename = machine->kernel_filename;\n> > > > const char *kernel_cmdline = machine->kernel_cmdline;\n> > > > const char *initrd_filename = machine->initrd_filename;\n> > > > @@ -236,19 +235,20 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id)\n> > > > \n> > > > switch (machine_id) {\n> > > > case CALXEDA_HIGHBANK:\n> > > > - cpu_model = \"cortex-a9\";\n> > > > + machine->cpu_type = ARM_CPU_TYPE_NAME(\"cortex-a9\");\n> > > > break;\n> > > > case CALXEDA_MIDWAY:\n> > > > - cpu_model = \"cortex-a15\";\n> > > > + machine->cpu_type = ARM_CPU_TYPE_NAME(\"cortex-a15\");\n> > > > break;\n> > > > + default:\n> > > > + assert(0);\n> > > > } \n> > > \n> > > Why not delete this switch statement completely and set\n> > > default_cpu_type at midway_class_init() and\n> > > highbank_class_init()? \n> > it would allow '-cpu foo' to take effect which isn't what current code does,\n> > as series doesn't add valid_cpus[] check at the same time. \n> \n> Oh, I see.\n> \n> \n> > \n> > So here we do pretty much strait-forward conversion from cpu_model\n> > to cpu_type and nothing else. \n> \n> OK.\n> \n> > \n> > > \n> > > \n> > > > \n> > > > for (n = 0; n < smp_cpus; n++) {\n> > > > - ObjectClass *oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);\n> > > > Object *cpuobj;\n> > > > ARMCPU *cpu;\n> > > > \n> > > > - cpuobj = object_new(object_class_get_name(oc));\n> > > > + cpuobj = object_new(machine->cpu_type);\n> > > > cpu = ARM_CPU(cpuobj);\n> > > > \n> > > > object_property_set_int(cpuobj, QEMU_PSCI_CONDUIT_SMC, \n> > [...]\n> > \n> > > > diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c\n> > > > index c16657d..79b317a 100644\n> > > > --- a/hw/arm/pxa2xx.c\n> > > > +++ b/hw/arm/pxa2xx.c\n> > > > @@ -2052,21 +2052,19 @@ static void pxa2xx_reset(void *opaque, int line, int level)\n> > > > \n> > > > /* Initialise a PXA270 integrated chip (ARM based core). */\n> > > > PXA2xxState *pxa270_init(MemoryRegion *address_space,\n> > > > - unsigned int sdram_size, const char *revision)\n> > > > + unsigned int sdram_size, const char *cpu_type)\n> > > > {\n> > > > PXA2xxState *s;\n> > > > int i;\n> > > > DriveInfo *dinfo;\n> > > > s = g_new0(PXA2xxState, 1);\n> > > > \n> > > > - if (revision && strncmp(revision, \"pxa27\", 5)) {\n> > > > + if (strncmp(cpu_type, ARM_CPU_TYPE_NAME(\"pxa27\"), 5)) { \n> > > \n> > > Why are you using ARM_CPU_TYPE_NAME here, if you are only\n> > > checking if cpu_type starts with \"pxa27\"? \n> > mainly to show that we are dealing with types here,\n> > I can leave plain \"pxa27\" if you prefer. \n> \n> Considering that we're dealing with a strncmp() hack that needs\n> ARM_CPU_TYPE_NAME to work in a very specific way, I would prefer\n> to leave the actual argument to strncmp() explicitly visible,\n> until we implement another solution.\n> \n> > \n> > \n> > > I suggest adding a TODO here noting that we implement this using\n> > > either a TYPE_ARM_PXA27 subclass (so we can use\n> > > object_class_dynamic_cast()), or a ARMCPUClass field to identify\n> > > if the CPU is pxa27. \n> > dynamic cast would be nice, but (\"pxa27\", 5) cover a range of cpu types\n> > starting with this prefix, to use cast class structure should be reorganized\n> > to make all pxa27 based cpus have a common pxa27 ancestor.\n> > Or just use more verbose complete list of valid_cpus[]\n> > \n> > It's out of scope of this patch including TODO comment,\n> > all boards should be audited anyways to make proper use of valid_cpus[]\n> > and adding not related TODO comments here doesn't seem right. \n> \n> True, now we have the plan of adding valid_cpus[], and this would\n> affect lots of other boards. I won't mind if you prefer to not\n> add the TODO comment on this series.\n> \n> > \n> > \n> > > > fprintf(stderr, \"Machine requires a PXA27x processor.\\n\");\n> > > > exit(1);\n> > > > } \n> > > \n> > > This would be another use case for a generic CPU model validation\n> > > mechanism in MachineClass. \n> > yep, just applied to a range of cpus instead of typical leaf class.\n> > \n> > [...]\n> > \n> > > > diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c\n> > > > index c1145dd..3d1a231 100644\n> > > > --- a/hw/arm/strongarm.c\n> > > > +++ b/hw/arm/strongarm.c\n> > > > @@ -1581,23 +1581,19 @@ static const TypeInfo strongarm_ssp_info = {\n> > > > \n> > > > /* Main CPU functions */\n> > > > StrongARMState *sa1110_init(MemoryRegion *sysmem,\n> > > > - unsigned int sdram_size, const char *rev)\n> > > > + unsigned int sdram_size, const char *cpu_type)\n> > > > {\n> > > > StrongARMState *s;\n> > > > int i;\n> > > > \n> > > > s = g_new0(StrongARMState, 1);\n> > > > \n> > > > - if (!rev) {\n> > > > - rev = \"sa1110-b5\";\n> > > > - }\n> > > > -\n> > > > - if (strncmp(rev, \"sa1110\", 6)) {\n> > > > + if (strncmp(cpu_type, \"sa1110\", 6)) {\n> > > > error_report(\"Machine requires a SA1110 processor.\");\n> > > > exit(1); \n> > > \n> > > Same suggestion as on pxa270_init(): adding a TODO here noting\n> > > that we implement this using either object_class_dynamic_cast(),\n> > > or a ARMCPUClass field to identify if the CPU is sa1110. \n> > same as pxa27, it's a case of range of cpus,\n> > TODO is orthogonal to patch topic, so I'd prefer not to add it here. \n> \n> OK\n> \n> > \n> > > \n> > > \n> > > > }\n> > > > \n> > > > - s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, rev));\n> > > > + s->cpu = ARM_CPU(cpu_create(cpu_type));\n> > > > \n> > > > memory_region_allocate_system_memory(&s->sdram, NULL, \"strongarm.sdram\",\n> > > > sdram_size);\n> > > > diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c\n> > > > index 8b757ff..75631f6 100644\n> > > > --- a/hw/arm/tosa.c\n> > > > +++ b/hw/arm/tosa.c\n> > > > @@ -219,7 +219,6 @@ static struct arm_boot_info tosa_binfo = {\n> > > > \n> > > > static void tosa_init(MachineState *machine)\n> > > > {\n> > > > - const char *cpu_model = machine->cpu_model;\n> > > > const char *kernel_filename = machine->kernel_filename;\n> > > > const char *kernel_cmdline = machine->kernel_cmdline;\n> > > > const char *initrd_filename = machine->initrd_filename;\n> > > > @@ -229,9 +228,6 @@ static void tosa_init(MachineState *machine)\n> > > > TC6393xbState *tmio;\n> > > > DeviceState *scp0, *scp1;\n> > > > \n> > > > - if (!cpu_model)\n> > > > - cpu_model = \"pxa255\";\n> > > > - \n> > > \n> > > Don't we need to set mc->default_cpu_type at\n> > > tosapda_machine_init() to replace this? \n> > board doesn't actually take user input and above remove code does nothing,\n> > look into pxa255_init() where it uses hardcoded cpu model\n> > cpu_generic_init(TYPE_ARM_CPU, \"pxa255\")\n> > \n> > another user connex_init() of pxa255_init() were already cleaned up\n> > or didn't have junk to begin with \n> \n> You are right, I didn't notice cpu_model was an unused variable.\n> \n> > \n> > > > mpu = pxa255_init(address_space_mem, tosa_binfo.ram_size);\n> > > > \n> > > > memory_region_init_ram(rom, NULL, \"tosa.rom\", TOSA_ROM, &error_fatal); \n> > [...]\n> > \n> > > > diff --git a/target/arm/cpu.c b/target/arm/cpu.c\n> > > > index 05c038b..feeeeb2 100644\n> > > > --- a/target/arm/cpu.c\n> > > > +++ b/target/arm/cpu.c\n> > > > @@ -867,7 +867,7 @@ static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)\n> > > > }\n> > > > \n> > > > cpuname = g_strsplit(cpu_model, \",\", 1);\n> > > > - typename = g_strdup_printf(\"%s-\" TYPE_ARM_CPU, cpuname[0]);\n> > > > + typename = g_strdup_printf(\"%s\" ARM_CPU_TYPE_SUFFIX, cpuname[0]); \n> > > \n> > > What about doing the same we do in x86 and s390:\n> > > \n> > > g_strdup_printf(ARM_CPU_TYPE_NAME(\"%s\"), cpuname[0]); \n> > sure\n> > \n> \n> I think this and the strncmp() line are the only suggestions that\n> I'm still keeping. But they shouldn't block the series, so:\n> \n> Reviewed-by: Eduardo Habkost \nThanks!\n\nI'll do fixups and squash 3/6 into 1/6 as suggested and respin.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ext-mx07.extmail.prod.ext.phx2.redhat.com;\n\tdmarc=none (p=none dis=none) header.from=redhat.com","ext-mx07.extmail.prod.ext.phx2.redhat.com;\n\tspf=fail smtp.mailfrom=imammedo@redhat.com"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xs69K3Szxz9sNV\n\tfor ;\n\tWed, 13 Sep 2017 00:09:09 +1000 (AEST)","from localhost ([::1]:36096 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1drlsB-0003k6-7r\n\tfor incoming@patchwork.ozlabs.org; Tue, 12 Sep 2017 10:09:07 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:59494)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1drlpx-00029I-Lz\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 10:06:51 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1drlps-0006Jm-Jz\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 10:06:49 -0400","from mx1.redhat.com ([209.132.183.28]:60518)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1drlpi-00068P-B5; Tue, 12 Sep 2017 10:06:34 -0400","from smtp.corp.redhat.com\n\t(int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby mx1.redhat.com (Postfix) with ESMTPS id 1FC9CC04BD2C;\n\tTue, 12 Sep 2017 14:06:33 +0000 (UTC)","from nial.brq.redhat.com (unknown [10.43.2.209])\n\tby smtp.corp.redhat.com (Postfix) with ESMTP id 6BCC06C516;\n\tTue, 12 Sep 2017 14:06:30 +0000 (UTC)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mx1.redhat.com 1FC9CC04BD2C","Date":"Tue, 12 Sep 2017 16:06:29 +0200","From":"Igor Mammedov ","To":"Eduardo Habkost ","Message-ID":"<20170912160629.7731bdbe@nial.brq.redhat.com>","In-Reply-To":"<20170912125322.GW7570@localhost.localdomain>","References":"<1504533662-198084-1-git-send-email-imammedo@redhat.com>\n\t<1504533662-198084-7-git-send-email-imammedo@redhat.com>\n\t<20170905213152.GG17184@localhost.localdomain>\n\t<20170912141159.22c63bce@nial.brq.redhat.com>\n\t<20170912125322.GW7570@localhost.localdomain>","MIME-Version":"1.0","Content-Type":"text/plain; charset=US-ASCII","Content-Transfer-Encoding":"7bit","X-Scanned-By":"MIMEDefang 2.79 on 10.5.11.14","X-Greylist":"Sender IP whitelisted, not delayed by milter-greylist-4.5.16\n\t(mx1.redhat.com [10.5.110.31]);\n\tTue, 12 Sep 2017 14:06:33 +0000 (UTC)","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]","X-Received-From":"209.132.183.28","Subject":"Re: [Qemu-devel] [PATCH 6/6] arm: drop intermadiate cpu_model ->\n\tcpu type parsing and use cpu type directly","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Peter Maydell ,\n\tAndrew Jones , \n\tRob Herring , Igor Mitsyanko ,\n\tAlistair Francis , qemu-devel@nongnu.org,\n\tqemu-arm@nongnu.org, Jan Kiszka ,\n\t\"Edgar E. Iglesias\" ,\n\tRichard Henderson ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1767230,"web_url":"http://patchwork.ozlabs.org/comment/1767230/","msgid":"","list_archive_url":null,"date":"2017-09-12T16:29:32","subject":"Re: [Qemu-devel] [PATCH 6/6] arm: drop intermadiate cpu_model ->\n\tcpu type parsing and use cpu type directly","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/people/64571/","name":"Alistair Francis","email":"alistair23@gmail.com"},"content":"On Tue, Sep 12, 2017 at 3:53 AM, Igor Mammedov wrote:\n> On Tue, 5 Sep 2017 19:12:26 -0300\n> Eduardo Habkost wrote:\n>\n>> On Tue, Sep 05, 2017 at 02:47:52PM -0700, Alistair Francis wrote:\n>> > On Tue, Sep 5, 2017 at 2:31 PM, Eduardo Habkost wrote:\n>> [...]\n>> > >> diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c\n>> > >> index f61e735..1cd6374 100644\n>> > >> --- a/hw/arm/stm32f205_soc.c\n>> > >> +++ b/hw/arm/stm32f205_soc.c\n>> > >> @@ -112,7 +112,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)\n>> > >>\n>> > >> armv7m = DEVICE(&s->armv7m);\n>> > >> qdev_prop_set_uint32(armv7m, \"num-irq\", 96);\n>> > >> - qdev_prop_set_string(armv7m, \"cpu-model\", s->cpu_model);\n>> > >> + qdev_prop_set_string(armv7m, \"cpu-type\", s->cpu_type);\n>> > >> object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),\n>> > >> \"memory\", &error_abort);\n>> > >> object_property_set_bool(OBJECT(&s->armv7m), true, \"realized\", &err);\n>> > >> @@ -200,7 +200,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)\n>> > >> }\n>> > >>\n>> > >> static Property stm32f205_soc_properties[] = {\n>> > >> - DEFINE_PROP_STRING(\"cpu-model\", STM32F205State, cpu_model),\n>> > >> + DEFINE_PROP_STRING(\"cpu-type\", STM32F205State, cpu_type),\n>> > >\n>> > > Same as armv7m: are we 100% sure users are not setting this\n>> > > manually?\n>> >\n>> > In an embedded board like this it really doesn't make sense to let the\n>> > user overwrite the CPU. The SoC will take it as an option, but the\n>> > board (which creates the SoC) just blindly always uses the same CPU.\n>> > That feature is more for QOMificatoion then any real reason though.\n>> >\n>>\n>> I'm not talking about -cpu (no user-visible change in the\n>> handling of -cpu should result from this patch), but about\n>> possible cases where the user set the \"cpu-model\" property using\n>> another mechanism, like -global. Probably it's impossible for an\n>> user to override the property successfully, but I would like to\n>> be sure.\n>>\n>>\n>> > In saying that I think a warning if the user tries to set the CPU\n>> > would make sense. I know that this issues comes up in other ARM boards\n>> > (Zynq-7000 has the same issue as well) so maybe a machine property\n>> > saying that the board doesn't accept custom CPUs would be a good idea.\n> Agreed, it would be useful, however goal of the patch to drop\n> cpu_generic_init() preferably without changing behavior\n>\n> so I'd leave extra stuff you mention upto board maintainers\n> to fix up on top.\n>\n>\n>> Yeah, there are multiple cases in this patch where boards are\n>> validating the CPU model, but not all boards do that. A generic\n>> MachineClass::valid_cpu_types[] field would be useful.\n> so far I've met 3 use cases for valid_cpu_types\n> * no check - just try to use whatever user provided\n> * check for concrete cpu models (leaf classes)\n> * check for super-class based in partial cpu_model match\n>\n> it is nice to have valid_cpu_types[] /I recall even trying out something similar/\n> but then series turns into mess where one tries to fix several things\n> and on top of it in all targets, hence I've decided first to get rid of\n> all cpu_model handling in boards and only then think about valid_cpus using cpu types.\n>\n> I'd gladly give up 'valid cpus' to someone else more interested in it,\n> there are other users beside of ARM boards for it.\n> /seems Alistair is interested in it, at least in ARM part/\n\nYeah, I'm interested in getting a generic framework to make this\npossible in. Still just an RFC, I need to get back to that this week\nand tidy it up.\n\nThanks,\nAlistair\n\n>\n>\n>> > Overall I think this patch is moving in the right direction though and\n>> > this CPU option being ignored existed before this series.\n>>\n>> I agree this is going on the right direction. However, I don't\n>> see any board that ignore the CPU option: all of them seem to use\n>> cpu_model when creating the CPUs, already.\n> in ARM case there are boards that use\n> * '-cpu' provided model\n> * '-cpu' provided model with valid cpu checks\n> * 'hardcoded' cpu model ignoring '-cpu'/-global\n>\n> I've thought commit message sufficiently described current situation and changes.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"Ub8OU3DC\"; dkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xs9Wj578Fz9s7g\n\tfor ;\n\tWed, 13 Sep 2017 02:40:17 +1000 (AEST)","from localhost ([::1]:37092 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1droER-0007K9-Nj\n\tfor incoming@patchwork.ozlabs.org; Tue, 12 Sep 2017 12:40:15 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:43924)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1dro4c-0006b1-2R\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:30:12 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1dro4a-0002Bx-So\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:30:06 -0400","from mail-wr0-x241.google.com ([2a00:1450:400c:c0c::241]:33412)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from )\n\tid 1dro4a-0002Bb-J0; Tue, 12 Sep 2017 12:30:04 -0400","by mail-wr0-x241.google.com with SMTP id b9so6506861wra.0;\n\tTue, 12 Sep 2017 09:30:04 -0700 (PDT)","by 10.28.191.130 with HTTP; Tue, 12 Sep 2017 09:29:32 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=mime-version:in-reply-to:references:from:date:message-id:subject:to\n\t:cc; bh=di9xPHw9wcpr0UAdyBOrClZZSw5tNphZTouhYBMae3g=;\n\tb=Ub8OU3DCR5IdScOTpvNa+vWWSplcVvgCD4V6h+kwvtwORa3yRq+4bnLuW6YXhn8Fwr\n\tJJ97mknVT3Q9gSi7YvJMgTc2c44oszQlfvMKbWbe5JOIBjmfZ6VzkA84Qwccb6Xjerho\n\t8DCQzxWah06oIz+9+cFz+4XG7zPgyRXk7dNv5ooupCLXkKoE6ohG6b9p9pt+ddz8p0PO\n\tliwtGBBb6Q4iO7FmZM7xzizu10MwN0i+VKtTm0PtDn/35+C+VijC12tx7CyR9qKQtLce\n\tr7FpuOWzk6A2mf6XPMsWbHZQIjImJzbXBsaKko11TPOvhyEUmnIuieejVZ10ZbzBkkR5\n\tl7hg==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:mime-version:in-reply-to:references:from:date\n\t:message-id:subject:to:cc;\n\tbh=di9xPHw9wcpr0UAdyBOrClZZSw5tNphZTouhYBMae3g=;\n\tb=Mk5E17Drj1hcPq3Gpf6Yn0JyNIL42zib2T3t9UMRAWxg6WzQVy65nW1VLR693sS52M\n\tQGLqrSekVe2felEL/0/n5LavBA+Fkxl0fR4y6gwvafcoJ7fNkL2G9OZ2VppOnkrqUeQy\n\tHlbDJLIF68yyEixHVXOLHHxjZ+evEaQyMQY/9QkSmjYTtny7wLjRCBsMj6JI6/ZgTCp1\n\txKRTyy/Y5vvbWmBcRkVPlI3D32uHjYfOAXuFdufSLcgz2+ld5WPeSC/y93MY49SvjoiD\n\tXZ91my2rx77reg06Ko9TUiOHvsB4x87WIfTMbyqHt2YAgkUZnYHpkH2erX634LOKWCos\n\tzHZg==","X-Gm-Message-State":"AHPjjUhZElHRbSQqh48jGoZGKT3qRkCpAo2yHAP7qNo4dRlG4iiMLgsT\n\tZI9z4ajhzdcMT7wzRLk9qLS4QwiFZw==","X-Google-Smtp-Source":"ADKCNb5rVpsjMCHLia48RnPZ4JB2fayeF5a4xoA6W84tYlPkeE8KyfVUCIanTkhsLA+9BfZ2lLbbgtbQ8qnMPl9LEa8=","X-Received":"by 10.223.187.74 with SMTP id x10mr12467056wrg.66.1505233803373; \n\tTue, 12 Sep 2017 09:30:03 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"<20170912125307.5681ec0e@nial.brq.redhat.com>","References":"<1504533662-198084-1-git-send-email-imammedo@redhat.com>\n\t<1504533662-198084-7-git-send-email-imammedo@redhat.com>\n\t<20170905213152.GG17184@localhost.localdomain>\n\t\n\t<20170905221226.GZ7570@localhost.localdomain>\n\t<20170912125307.5681ec0e@nial.brq.redhat.com>","From":"Alistair Francis ","Date":"Tue, 12 Sep 2017 09:29:32 -0700","Message-ID":"","To":"Igor Mammedov ","Content-Type":"text/plain; charset=\"UTF-8\"","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2a00:1450:400c:c0c::241","Subject":"Re: [Qemu-devel] [PATCH 6/6] arm: drop intermadiate cpu_model ->\n\tcpu type parsing and use cpu type directly","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Peter Maydell ,\n\tAndrew Jones , \n\tEduardo Habkost , Rob Herring , \n\tIgor Mitsyanko ,\n\tAlistair Francis ,\n\t\"qemu-devel@nongnu.org Developers\" ,\n\tqemu-arm , Jan Kiszka ,\n\t\"Edgar E. Iglesias\" ,\n\tRichard Henderson ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}}]