[{"id":1763416,"web_url":"http://patchwork.ozlabs.org/comment/1763416/","msgid":"<20170905144620.mleywtmz7nmbdb5j@valkosipuli.retiisi.org.uk>","list_archive_url":null,"date":"2017-09-05T14:46:20","subject":"Re: [PATCH v3 1/2] dt-bindings: media: Add Cadence MIPI-CSI2 RX\n\tDevice Tree bindings","submitter":{"id":1593,"url":"http://patchwork.ozlabs.org/api/people/1593/","name":"Sakari Ailus","email":"sakari.ailus@iki.fi"},"content":"Hi Maxime,\n\nOn Mon, Sep 04, 2017 at 03:03:34PM +0200, Maxime Ripard wrote:\n> The Cadence MIPI-CSI2 RX controller is a CSI2RX bridge that supports up to\n> 4 CSI-2 lanes, and can route the frames to up to 4 streams, depending on\n> the hardware implementation.\n> \n> It can operate with an external D-PHY, an internal one or no D-PHY at all\n> in some configurations.\n> \n> Acked-by: Rob Herring \n> Acked-by: Benoit Parrot \n> Signed-off-by: Maxime Ripard \n> ---\n> .../devicetree/bindings/media/cdns-csi2rx.txt | 98 ++++++++++++++++++++++\n> 1 file changed, 98 insertions(+)\n> create mode 100644 Documentation/devicetree/bindings/media/cdns-csi2rx.txt\n\nNaming this according to the compatible string would make it easier to\nfind. The same pattern is used by a number of existing binding files.\n\nUp to you.\n\n> \n> diff --git a/Documentation/devicetree/bindings/media/cdns-csi2rx.txt b/Documentation/devicetree/bindings/media/cdns-csi2rx.txt\n> new file mode 100644\n> index 000000000000..2395030d8c72\n> --- /dev/null\n> +++ b/Documentation/devicetree/bindings/media/cdns-csi2rx.txt\n> @@ -0,0 +1,98 @@\n> +Cadence MIPI-CSI2 RX controller\n> +===============================\n> +\n> +The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI\n> +lanes in input, and 4 different pixel streams in output.\n> +\n> +Required properties:\n> + - compatible: must be set to \"cdns,csi2rx\" and an SoC-specific compatible\n> + - reg: base address and size of the memory mapped region\n> + - clocks: phandles to the clocks driving the controller\n> + - clock-names: must contain:\n> + * sys_clk: main clock\n> + * p_clk: register bank clock\n> + * pixel_if[0-3]_clk: pixel stream output clock, one for each stream\n> + implemented in hardware, between 0 and 3\n> +\n> +Optional properties:\n> + - phys: phandle to the external D-PHY, phy-names must be provided\n> + - phy-names: must contain dphy, if the implementation uses an\n> + external D-PHY\n> +\n> +Required subnodes:\n> + - ports: A ports node with endpoint definitions as defined in\n> + Documentation/devicetree/bindings/media/video-interfaces.txt. The\n> + first port subnode should be the input endpoint, the next ones the\n> + output, one for each stream supported by the CSI2-RX controller.\n\nWhile I guess the DT compiler won't rearrange the nodes, it'd be better to\ndefine the port numbers explicitly, i.e. that input is number 0.\n\n> + The ports ID must be the stream output number used in the\n> + implementation, plus 1.\n\nAnd also that outputs are from 1 to 4.\n\nWith that,\n\nAcked-by: Sakari Ailus ","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xmqKZ6JWtz9t2v\n\tfor ;\n\tWed, 6 Sep 2017 00:46:26 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751276AbdIEOqZ (ORCPT\n\t);\n\tTue, 5 Sep 2017 10:46:25 -0400","from nblzone-211-213.nblnetworks.fi ([83.145.211.213]:41958 \"EHLO\n\thillosipuli.retiisi.org.uk\" rhost-flags-OK-OK-OK-FAIL)\n\tby vger.kernel.org with ESMTP id S1751316AbdIEOqY (ORCPT\n\t); Tue, 5 Sep 2017 10:46:24 -0400","from valkosipuli.localdomain (valkosipuli.retiisi.org.uk\n\t[IPv6:2001:1bc8:1a6:d3d5::80:2])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby hillosipuli.retiisi.org.uk (Postfix) with ESMTPS id 2CA99600D3;\n\tTue, 5 Sep 2017 17:46:21 +0300 (EEST)","from sakke by valkosipuli.localdomain with local (Exim 4.89)\n\t(envelope-from )\n\tid 1dpF7M-0002XH-IK; Tue, 05 Sep 2017 17:46:20 +0300"],"Date":"Tue, 5 Sep 2017 17:46:20 +0300","From":"Sakari Ailus ","To":"Maxime Ripard ","Cc":"Mauro Carvalho Chehab , Mark Rutland\n\t, Rob Herring , Laurent\n\tPinchart , \n\tlinux-media@vger.kernel.org, devicetree@vger.kernel.org, Cyprian Wronka\n\t, Neil Webb , Richard Sproul\n\t, Alan Douglas , Steve Creaney\n\t, Thomas Petazzoni\n\t, Boris Brezillon\n\t, Niklas =?iso-8859-1?q?S=F6derlun?=\n\t=?iso-8859-1?q?d?= ,\n\tHans Verkuil , Sakari Ailus\n\t, Benoit Parrot ","Subject":"Re: [PATCH v3 1/2] dt-bindings: media: Add Cadence MIPI-CSI2 RX\n\tDevice Tree bindings","Message-ID":"<20170905144620.mleywtmz7nmbdb5j@valkosipuli.retiisi.org.uk>","References":"<20170904130335.23280-1-maxime.ripard@free-electrons.com>\n\t<20170904130335.23280-2-maxime.ripard@free-electrons.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170904130335.23280-2-maxime.ripard@free-electrons.com>","User-Agent":"NeoMutt/20170113 (1.7.2)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1768776,"web_url":"http://patchwork.ozlabs.org/comment/1768776/","msgid":"<1580072.HvWFtpbqJt@avalon>","list_archive_url":null,"date":"2017-09-14T18:40:53","subject":"Re: [PATCH v3 1/2] dt-bindings: media: Add Cadence MIPI-CSI2 RX\n\tDevice Tree bindings","submitter":{"id":11034,"url":"http://patchwork.ozlabs.org/api/people/11034/","name":"Laurent Pinchart","email":"laurent.pinchart@ideasonboard.com"},"content":"Hi Maxime,\n\nThank you for the patch.\n\nOn Monday, 4 September 2017 16:03:34 EEST Maxime Ripard wrote:\n> The Cadence MIPI-CSI2 RX controller is a CSI2RX bridge that supports up to\n> 4 CSI-2 lanes, and can route the frames to up to 4 streams, depending on\n> the hardware implementation.\n> \n> It can operate with an external D-PHY, an internal one or no D-PHY at all\n> in some configurations.\n> \n> Acked-by: Rob Herring \n> Acked-by: Benoit Parrot \n> Signed-off-by: Maxime Ripard \n> ---\n> .../devicetree/bindings/media/cdns-csi2rx.txt | 98 +++++++++++++++++++\n> 1 file changed, 98 insertions(+)\n> create mode 100644 Documentation/devicetree/bindings/media/cdns-csi2rx.txt\n> \n> diff --git a/Documentation/devicetree/bindings/media/cdns-csi2rx.txt\n> b/Documentation/devicetree/bindings/media/cdns-csi2rx.txt new file mode\n> 100644\n> index 000000000000..2395030d8c72\n> --- /dev/null\n> +++ b/Documentation/devicetree/bindings/media/cdns-csi2rx.txt\n> @@ -0,0 +1,98 @@\n> +Cadence MIPI-CSI2 RX controller\n> +===============================\n> +\n> +The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4\n> CSI\n> +lanes in input, and 4 different pixel streams in output.\n> +\n> +Required properties:\n> + - compatible: must be set to \"cdns,csi2rx\" and an SoC-specific compatible\n> + - reg: base address and size of the memory mapped region\n> + - clocks: phandles to the clocks driving the controller\n> + - clock-names: must contain:\n> + * sys_clk: main clock\n> + * p_clk: register bank clock\n> + * pixel_if[0-3]_clk: pixel stream output clock, one for each stream\n> + implemented in hardware, between 0 and 3\n> +\n> +Optional properties:\n> + - phys: phandle to the external D-PHY, phy-names must be provided\n> + - phy-names: must contain dphy, if the implementation uses an\n> + external D-PHY\n> +\n> +Required subnodes:\n> + - ports: A ports node with endpoint definitions as defined in\n> + Documentation/devicetree/bindings/media/video-interfaces.txt.\n> The\n> + first port subnode should be the input endpoint, the next ones\n> the\n> + output, one for each stream supported by the CSI2-RX controller.\n> + The ports ID must be the stream output number used in the\n> + implementation, plus 1.\n\nThis sounds a bit unclear to me. How about the following ?\n\n - ports: A ports node with one port child node per device input and output\n port, in accordance with the video interface bindings defined in\n Documentation/devicetree/bindings/media/video-interfaces.txt. The\n port nodes numbered as follows.\n\n Port\tDescription\n -----------------------------\n 0\tCSI-2 input\n 1\tStream 0 output\n 2\tStream 1 output\n 3\tStream 2 output\n 4\tStream 3 output\n\n The stream output port nodes are optional if they are not connected\n to anything at the hardware level.\n\n> +\n> +Example:\n> +\n> +csi2rx: csi-bridge@0d060000 {\n> +\tcompatible = \"cdns,csi2rx\";\n> +\treg = <0x0d060000 0x1000>;\n> +\tclocks = <&byteclock>, <&byteclock>\n> +\t\t <&coreclock>, <&coreclock>,\n> +\t\t <&coreclock>, <&coreclock>;\n> +\tclock-names = \"sys_clk\", \"p_clk\",\n> +\t\t \"pixel_if0_clk\", \"pixel_if1_clk\",\n> +\t\t \"pixel_if2_clk\", \"pixel_if3_clk\";\n> +\n> +\tports {\n> +\t\t#address-cells = <1>;\n> +\t\t#size-cells = <0>;\n> +\n> +\t\tport@0 {\n> +\t\t\t#address-cells = <1>;\n> +\t\t\t#size-cells = <0>;\n\nThose two properties are not needed as the endpoint isn't numbered. Same for \nall other ports below.\n\nWith this fixed and the ports node description clarified,\n\nReviewed-by: Laurent Pinchart \n\n> +\t\t\treg = <0>;\n> +\n> +\t\t\tcsi2rx_in_sensor: endpoint {\n> +\t\t\t\tremote-endpoint = <&sensor_out_csi2rx>;\n> +\t\t\t\tclock-lanes = <0>;\n> +\t\t\t\tdata-lanes = <1 2>;\n> +\t\t\t};\n> +\t\t};\n> +\n> +\t\tport@1 {\n> +\t\t\t#address-cells = <1>;\n> +\t\t\t#size-cells = <0>;\n> +\t\t\treg = <1>;\n> +\n> +\t\t\tcsi2rx_out_grabber0: endpoint {\n> +\t\t\t\tremote-endpoint = <&grabber0_in_csi2rx>;\n> +\t\t\t};\n> +\t\t};\n> +\n> +\t\tport@2 {\n> +\t\t\t#address-cells = <1>;\n> +\t\t\t#size-cells = <0>;\n> +\t\t\treg = <2>;\n> +\n> +\t\t\tcsi2rx_out_grabber1: endpoint {\n> +\t\t\t\tremote-endpoint = <&grabber1_in_csi2rx>;\n> +\t\t\t};\n> +\t\t};\n> +\n> +\t\tport@3 {\n> +\t\t\t#address-cells = <1>;\n> +\t\t\t#size-cells = <0>;\n> +\t\t\treg = <3>;\n> +\n> +\t\t\tcsi2rx_out_grabber2: endpoint {\n> +\t\t\t\tremote-endpoint = <&grabber2_in_csi2rx>;\n> +\t\t\t};\n> +\t\t};\n> +\n> +\t\tport@4 {\n> +\t\t\t#address-cells = <1>;\n> +\t\t\t#size-cells = <0>;\n> +\t\t\treg = <4>;\n> +\n> +\t\t\tcsi2rx_out_grabber3: endpoint {\n> +\t\t\t\tremote-endpoint = <&grabber3_in_csi2rx>;\n> +\t\t\t};\n> +\t\t};\n> +\t};\n> +};","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=ideasonboard.com header.i=@ideasonboard.com\n\theader.b=\"CEWjYl83\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xtS606jSGz9sRm\n\tfor ;\n\tFri, 15 Sep 2017 04:40:56 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751698AbdINSkz (ORCPT\n\t);\n\tThu, 14 Sep 2017 14:40:55 -0400","from galahad.ideasonboard.com ([185.26.127.97]:45594 \"EHLO\n\tgalahad.ideasonboard.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751631AbdINSkx (ORCPT\n\t); Thu, 14 Sep 2017 14:40:53 -0400","from avalon.localnet (unknown [12.145.98.253])\n\tby galahad.ideasonboard.com (Postfix) with ESMTPSA id 0C813201F5;\n\tThu, 14 Sep 2017 20:38:27 +0200 (CEST)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com;\n\ts=mail; t=1505414307;\n\tbh=NuB1wVJ7SZGIGRmd+JjHy7V8KBdOe0YDXiunGGeIppY=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n\tb=CEWjYl83cHqe91Qmyu6MlZAe16qdZ2CNVgPXTVM/DhkB9kDFH0fIw7tXwevQmaOgM\n\tSxpIY6k7tzjl0LyF6cw9PGzUz+2yyhXMIqqV7ft8rShxlOxKDnhVqkS9tLEkFggzt3\n\t5k91Vl6KWnfZzzX9pdLiPc5cOoo/BC47useqOFUo=","From":"Laurent Pinchart ","To":"Maxime Ripard ","Cc":"Mauro Carvalho Chehab , Mark Rutland\n\t, Rob Herring ,\n\tlinux-media@vger.kernel.org, devicetree@vger.kernel.org,\n\tCyprian Wronka , Neil Webb ,\n\tRichard Sproul , \n\tAlan Douglas ,\n\tSteve Creaney , Thomas Petazzoni\n\t, Boris Brezillon\n\t, Niklas =?iso-8859-1?q?S=F6derlun?=\n\t=?iso-8859-1?q?d?= ,\n\tHans Verkuil , Sakari Ailus\n\t, Benoit Parrot ","Subject":"Re: [PATCH v3 1/2] dt-bindings: media: Add Cadence MIPI-CSI2 RX\n\tDevice Tree bindings","Date":"Thu, 14 Sep 2017 21:40:53 +0300","Message-ID":"<1580072.HvWFtpbqJt@avalon>","In-Reply-To":"<20170904130335.23280-2-maxime.ripard@free-electrons.com>","References":"<20170904130335.23280-1-maxime.ripard@free-electrons.com>\n\t<20170904130335.23280-2-maxime.ripard@free-electrons.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"7Bit","Content-Type":"text/plain; charset=\"us-ascii\"","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}}]