[{"id":1762449,"web_url":"http://patchwork.ozlabs.org/comment/1762449/","msgid":"","list_archive_url":null,"date":"2017-09-04T06:42:54","subject":"Re: [U-Boot] [next PATCH v2 1/2] ARM: mvebu: Add SoC IDs for\n\tMarvell's integrated CPUs","submitter":{"id":13,"url":"http://patchwork.ozlabs.org/api/people/13/","name":"Stefan Roese","email":"sr@denx.de"},"content":"On 04.09.2017 07:38, Chris Packham wrote:\n> These SoCs are network packet processors (switch chips) with integrated\n> ARMv7 cores. They share a great deal of commonality with the Armada-XP\n> CPUs.\n> \n> Signed-off-by: Chris Packham \n> ---\n> There are actually a number of IDs for these chips, probably a dozen in\n> total. I haven't enumerated them all in this patch, the 98DX4251,\n> 98DX3336 and 98DX3236 are the base versions in their respective ranges.\n> These 3 IDs also happen to suit my immediate need but I can add the\n> additional ones in an follow up patch or a re-roll of this one.\n> \n> Changes in v2:\n> - none\n> \n> arch/arm/mach-mvebu/cpu.c | 14 ++++++++++++++\n> arch/arm/mach-mvebu/include/mach/cpu.h | 1 +\n> arch/arm/mach-mvebu/include/mach/soc.h | 3 +++\n> 3 files changed, 18 insertions(+)\n\nReviewed-by: Stefan Roese \n\nThanks,\nStefan","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xm0fS0fGBz9s72\n\tfor ;\n\tMon, 4 Sep 2017 16:43:12 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid C0D7AC21DAD; Mon, 4 Sep 2017 06:43:04 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 2BAC0C21DAD;\n\tMon, 4 Sep 2017 06:43:02 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid A1F74C21DAD; Mon, 4 Sep 2017 06:43:01 +0000 (UTC)","from mx1.mailbox.org (mx1.mailbox.org [80.241.60.212])\n\tby lists.denx.de (Postfix) with ESMTPS id 65B3CC21DA1\n\tfor ; Mon, 4 Sep 2017 06:43:01 +0000 (UTC)","from smtp1.mailbox.org (smtp1.mailbox.org [80.241.60.240])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby mx1.mailbox.org (Postfix) with ESMTPS id 4BCE5442B3;\n\tMon, 4 Sep 2017 08:43:00 +0200 (CEST)","from smtp1.mailbox.org ([80.241.60.240])\n\tby spamfilter02.heinlein-hosting.de (spamfilter02.heinlein-hosting.de\n\t[80.241.56.116]) (amavisd-new, port 10030)\n\twith ESMTP id uPwAM3PfGdtm; Mon, 4 Sep 2017 08:42:57 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-0.7 required=5.0 tests=RCVD_IN_DNSWL_LOW\n\tautolearn=unavailable autolearn_force=no version=3.4.0","X-Virus-Scanned":"amavisd-new at heinlein-support.de","To":"Chris Packham , u-boot@lists.denx.de","References":"<20170904053832.12229-1-judge.packham@gmail.com>","From":"Stefan Roese ","Message-ID":"","Date":"Mon, 4 Sep 2017 08:42:54 +0200","MIME-Version":"1.0","In-Reply-To":"<20170904053832.12229-1-judge.packham@gmail.com>","Content-Language":"en-US","Cc":"Luka Perkov ","Subject":"Re: [U-Boot] [next PATCH v2 1/2] ARM: mvebu: Add SoC IDs for\n\tMarvell's integrated CPUs","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Transfer-Encoding":"base64","Content-Type":"text/plain; charset=\"utf-8\"; Format=\"flowed\"","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1775277,"web_url":"http://patchwork.ozlabs.org/comment/1775277/","msgid":"<7652af3d-7875-fb8c-d65b-e5ec7590bd77@denx.de>","list_archive_url":null,"date":"2017-09-26T08:51:15","subject":"Re: [U-Boot] [next PATCH v2 1/2] ARM: mvebu: Add SoC IDs for\n\tMarvell's integrated CPUs","submitter":{"id":13,"url":"http://patchwork.ozlabs.org/api/people/13/","name":"Stefan Roese","email":"sr@denx.de"},"content":"On 04.09.2017 07:38, Chris Packham wrote:\n> These SoCs are network packet processors (switch chips) with integrated\n> ARMv7 cores. They share a great deal of commonality with the Armada-XP\n> CPUs.\n> \n> Signed-off-by: Chris Packham \n> ---\n> There are actually a number of IDs for these chips, probably a dozen in\n> total. I haven't enumerated them all in this patch, the 98DX4251,\n> 98DX3336 and 98DX3236 are the base versions in their respective ranges.\n> These 3 IDs also happen to suit my immediate need but I can add the\n> additional ones in an follow up patch or a re-roll of this one.\n> \n> Changes in v2:\n> - none\n\nApplied to u-boot-marvell/master.\n\nThanks,\nStefan","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y1ZTC1r1Dz9t3B\n\tfor ;\n\tTue, 26 Sep 2017 18:52:15 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid E401CC21D90; Tue, 26 Sep 2017 08:51:48 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 7A899C21F03;\n\tTue, 26 Sep 2017 08:51:46 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 93EBAC21F00; Tue, 26 Sep 2017 08:51:26 +0000 (UTC)","from mx2.mailbox.org (mx2.mailbox.org [80.241.60.215])\n\tby lists.denx.de (Postfix) with ESMTPS id 548AEC21E50\n\tfor ; Tue, 26 Sep 2017 08:51:23 +0000 (UTC)","from smtp1.mailbox.org (smtp1.mailbox.org [80.241.60.240])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby mx2.mailbox.org (Postfix) with ESMTPS id AEA4F4C53B;\n\tTue, 26 Sep 2017 10:51:22 +0200 (CEST)","from smtp1.mailbox.org ([80.241.60.240])\n\tby spamfilter02.heinlein-hosting.de (spamfilter02.heinlein-hosting.de\n\t[80.241.56.116]) (amavisd-new, port 10030)\n\twith ESMTP id 7Gd7rWzfZs2A; Tue, 26 Sep 2017 10:51:17 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-0.7 required=5.0 tests=RCVD_IN_DNSWL_LOW\n\tautolearn=unavailable autolearn_force=no version=3.4.0","X-Virus-Scanned":"amavisd-new at heinlein-support.de","To":"Chris Packham , u-boot@lists.denx.de","References":"<20170904053832.12229-1-judge.packham@gmail.com>","From":"Stefan Roese ","Message-ID":"<7652af3d-7875-fb8c-d65b-e5ec7590bd77@denx.de>","Date":"Tue, 26 Sep 2017 10:51:15 +0200","MIME-Version":"1.0","In-Reply-To":"<20170904053832.12229-1-judge.packham@gmail.com>","Content-Language":"en-US","Cc":"Prafulla Wadaskar ,\n\tLuka Perkov ","Subject":"Re: [U-Boot] [next PATCH v2 1/2] ARM: mvebu: Add SoC IDs for\n\tMarvell's integrated CPUs","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Transfer-Encoding":"base64","Content-Type":"text/plain; charset=\"utf-8\"; Format=\"flowed\"","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}}]