[{"id":1762345,"web_url":"http://patchwork.ozlabs.org/comment/1762345/","msgid":"","list_archive_url":null,"date":"2017-09-03T23:23:09","subject":"Re: [PATCH 01/10] dmaengine: sun6i: Correct setting of clock\n\tautogating register for A83T/H3","submitter":{"id":61837,"url":"http://patchwork.ozlabs.org/api/people/61837/","name":"Andre Przywara","email":"andre.przywara@arm.com"},"content":"On 03/09/17 23:40, Stefan Brüns wrote:\n> The H83T uses a compatible string different from the A23, but requires\n\n A83T\n\n> the same clock autogating register setting.\n> \n> The H3 also requires setting the clock autogating register, but has\n> the register at a different offset.\n> \n> Some currently available SoCs not yet supported by the sun6i-dma driver\n> will require new compatible strings. These SoCs either follow the A23\n> register model (e.g. V3s) or the H3 register model (A64, R40), so a new\n> variable is added to the config struct to group SoCs with common register\n> models.\n\nAs mentioned in that other mail, using the actual properties as names\nhere instead of grouping them to rather arbitrary groups seems more\nuseful and future-proof to me and should be easier to read.\nIn this case this should simplify this patch:\nsun8i_a23_dma_cfg = {\n \t.nr_max_channels = 8,\n \t.nr_max_requests = 24,\n \t.nr_max_vchans = 37,\n+\t.auto_clock_gate = 0x20,\n...\n-\tif (of_device_is_compatible(pdev->dev.of_node,\n-\t\t\t\t \"allwinner,sun8i-a23-dma\"))\n-\t\twritel(SUN8I_DMA_GATE_ENABLE, sdc->base + SUN8I_DMA_GATE);\n+\tif (sdc->cfg->auto_clock_gate)\n+\t\twritel(SUN8I_DMA_GATE_ENABLE,\n+\t\t sdc->base + sdc->cfg->auto_clock_gate);\n\n> Signed-off-by: Stefan Brüns \n> ---\n> drivers/dma/sun6i-dma.c | 34 +++++++++++++++++++++++++++++++---\n> 1 file changed, 31 insertions(+), 3 deletions(-)\n> \n> diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c\n> index a2358780ab2c..1d9b3be30d22 100644\n> --- a/drivers/dma/sun6i-dma.c\n> +++ b/drivers/dma/sun6i-dma.c\n> @@ -48,6 +48,9 @@\n> #define SUN8I_DMA_GATE\t\t0x20\n> #define SUN8I_DMA_GATE_ENABLE\t0x4\n> \n> +#define SUNXI_H3_SECURITE_REG\t\t0x20\n\ntypo?\t SUNXI_H3_SECURITY_REG ?\n\nCheers,\nAndre.\n\n> +#define SUNXI_H3_DMA_GATE\t\t0x28\n> +#define SUNXI_H3_DMA_GATE_ENABLE\t0x4\n> /*\n> * Channels specific registers\n> */\n> @@ -90,6 +93,21 @@\n> #define NORMAL_WAIT\t8\n> #define DRQ_SDRAM\t1\n> \n> +/*\n> + * DMA Controller generations\n> + *\n> + * Newer SoC generations changed or added some register definitions:\n> + * - A23 added a clock gate register\n> + * - H3 has a different offset for the clock gating register,\n> + * the burst length field has a different offset in the channel\n> + * configuration register, also additional burst lengths/widths.\n> + */\n> +enum dmac_variant {\n> +\tDMAC_VARIANT_A31,\n> +\tDMAC_VARIANT_A23,\n> +\tDMAC_VARIANT_H3,\n> +};\n> +\n> /*\n> * Hardware channels / ports representation\n> *\n> @@ -101,6 +119,7 @@ struct sun6i_dma_config {\n> \tu32 nr_max_channels;\n> \tu32 nr_max_requests;\n> \tu32 nr_max_vchans;\n> +\tenum dmac_variant dmac_variant;\n> };\n> \n> /*\n> @@ -998,6 +1017,7 @@ static struct sun6i_dma_config sun6i_a31_dma_cfg = {\n> \t.nr_max_channels = 16,\n> \t.nr_max_requests = 30,\n> \t.nr_max_vchans = 53,\n> +\t.dmac_variant = DMAC_VARIANT_A31,\n> };\n> \n> /*\n> @@ -1009,23 +1029,29 @@ static struct sun6i_dma_config sun8i_a23_dma_cfg = {\n> \t.nr_max_channels = 8,\n> \t.nr_max_requests = 24,\n> \t.nr_max_vchans = 37,\n> +\t.dmac_variant = DMAC_VARIANT_A23,\n> };\n> \n> static struct sun6i_dma_config sun8i_a83t_dma_cfg = {\n> \t.nr_max_channels = 8,\n> \t.nr_max_requests = 28,\n> \t.nr_max_vchans = 39,\n> +\t.dmac_variant = DMAC_VARIANT_A23,\n> };\n> \n> /*\n> * The H3 has 12 physical channels, a maximum DRQ port id of 27,\n> * and a total of 34 usable source and destination endpoints.\n> + * It also supports additional burst lengths and bus widths,\n> + * and the burst length fields have different offsets.\n> */\n> \n> static struct sun6i_dma_config sun8i_h3_dma_cfg = {\n> \t.nr_max_channels = 12,\n> \t.nr_max_requests = 27,\n> \t.nr_max_vchans = 34,\n> +\t.dmac_variant = DMAC_VARIANT_H3,\n> +};\n> };\n> \n> static const struct of_device_id sun6i_dma_match[] = {\n> @@ -1177,11 +1203,13 @@ static int sun6i_dma_probe(struct platform_device *pdev)\n> \t/*\n> \t * sun8i variant requires us to toggle a dma gating register,\n> \t * as seen in Allwinner's SDK. This register is not documented\n> -\t * in the A23 user manual.\n> +\t * in the A23 user manual, but appears in e.g. the H83T manual.\n> +\t * For the H3, H5 and A64, the register has a different location\n> \t */\n> -\tif (of_device_is_compatible(pdev->dev.of_node,\n> -\t\t\t\t \"allwinner,sun8i-a23-dma\"))\n> +\tif (sdc->cfg->dmac_variant == DMAC_VARIANT_A23)\n> \t\twritel(SUN8I_DMA_GATE_ENABLE, sdc->base + SUN8I_DMA_GATE);\n> +\telse if (sdc->cfg->dmac_variant == DMAC_VARIANT_H3)\n> +\t\twritel(SUNXI_H3_DMA_GATE_ENABLE, sdc->base + SUNXI_H3_DMA_GATE);\n> \n> \treturn 0;\n> \n>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; 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Sun, 3 Sep 2017 16:26:47 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:\n\tMessage-ID:From:References:To:Subject:Reply-To:Content-ID:Content-Description\n\t:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=wxjEE92ByGDpBgvqAr5tE3BXp84n9xxYEyU/EWtNMCY=;\n\tb=RADUf9RRjL899o\n\tuROS0AY5JyKXqYnit7kD1sURzLss09yi+emjKHdRgVwATWIU4HewLv/EUqY7fJe2JNoU+yk08zyRG\n\t+a1kkAh8MH29cJd5mIK5hVC1ws5rEBowg/T9f1kvd9967NvFBZy4GjhuGiZdVO2GtU4oSZeCkQBLJ\n\tC/zgR/CDCKevMGLG/a1xw7KHWLRckp9v1H+WKNG742Q498N64mhYOHG1iziJ/J4xUZSlQTus0oiU0\n\tmf7V+7gO0NWwKY4/8w1T3Nkt+0lLbif++IXshHRYM232e/qSRzsmU66MZFmFuyf03ajnn/BuF3q8/\n\tmshRPMHUN+hlHdzvuwZg==;","Subject":"Re: [PATCH 01/10] dmaengine: sun6i: Correct setting of clock\n\tautogating register for A83T/H3","To":"=?utf-8?q?Stefan_Br=C3=BCns?= ,\n\tlinux-sunxi@googlegroups.com","References":"<20170903224100.17893-1-stefan.bruens@rwth-aachen.de>\n\t<20170903224100.17893-2-stefan.bruens@rwth-aachen.de>","From":"=?utf-8?q?Andr=C3=A9_Przywara?= ","Organization":"ARM Ltd.","Message-ID":"","Date":"Mon, 4 Sep 2017 00:23:09 +0100","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101\n\tThunderbird/45.8.0","MIME-Version":"1.0","In-Reply-To":"<20170903224100.17893-2-stefan.bruens@rwth-aachen.de>","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170903_162710_157037_B7040341 ","X-CRM114-Status":"GOOD ( 20.41 )","X-Spam-Score":"-6.9 (------)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-6.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/,\n\thigh trust [217.140.101.70 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"devicetree@vger.kernel.org, Vinod Koul ,\n\tlinux-kernel@vger.kernel.org, Code Kipper ,\n\tChen-Yu Tsai , Rob Herring ,\n\tdmaengine@vger.kernel.org,\n\tMaxime Ripard , \n\tlinux-arm-kernel@lists.infradead.org","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1762462,"web_url":"http://patchwork.ozlabs.org/comment/1762462/","msgid":"<20170904070620.3lpkmq6nt2qrgwah@flea>","list_archive_url":null,"date":"2017-09-04T07:06:20","subject":"Re: [PATCH 01/10] dmaengine: sun6i: Correct setting of clock\n\tautogating register for A83T/H3","submitter":{"id":12916,"url":"http://patchwork.ozlabs.org/api/people/12916/","name":"Maxime Ripard","email":"maxime.ripard@free-electrons.com"},"content":"On Mon, Sep 04, 2017 at 12:23:09AM +0100, André Przywara wrote:\n> On 03/09/17 23:40, Stefan Brüns wrote:\n> > The H83T uses a compatible string different from the A23, but requires\n> \n> A83T\n> \n> > the same clock autogating register setting.\n> > \n> > The H3 also requires setting the clock autogating register, but has\n> > the register at a different offset.\n> > \n> > Some currently available SoCs not yet supported by the sun6i-dma driver\n> > will require new compatible strings. These SoCs either follow the A23\n> > register model (e.g. V3s) or the H3 register model (A64, R40), so a new\n> > variable is added to the config struct to group SoCs with common register\n> > models.\n> \n> As mentioned in that other mail, using the actual properties as names\n> here instead of grouping them to rather arbitrary groups seems more\n> useful and future-proof to me and should be easier to read.\n> In this case this should simplify this patch:\n> sun8i_a23_dma_cfg = {\n> \t.nr_max_channels = 8,\n> \t.nr_max_requests = 24,\n> \t.nr_max_vchans = 37,\n> +\t.auto_clock_gate = 0x20,\n> ...\n> -\tif (of_device_is_compatible(pdev->dev.of_node,\n> -\t\t\t\t \"allwinner,sun8i-a23-dma\"))\n> -\t\twritel(SUN8I_DMA_GATE_ENABLE, sdc->base + SUN8I_DMA_GATE);\n> +\tif (sdc->cfg->auto_clock_gate)\n> +\t\twritel(SUN8I_DMA_GATE_ENABLE,\n> +\t\t sdc->base + sdc->cfg->auto_clock_gate);\n\nI agree.\n\nMaxime","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"mxSaiEGa\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xm19v3nktz9s7m\n\tfor ;\n\tMon, 4 Sep 2017 17:06:59 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dolTE-0002MP-5u; Mon, 04 Sep 2017 07:06:56 +0000","from mail.free-electrons.com ([62.4.15.54])\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dolT9-0002HS-89 for linux-arm-kernel@lists.infradead.org;\n\tMon, 04 Sep 2017 07:06:53 +0000","by mail.free-electrons.com (Postfix, from userid 110)\n\tid 77EC22081C; Mon, 4 Sep 2017 09:06:29 +0200 (CEST)","from localhost (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr\n\t[90.63.216.87])\n\tby mail.free-electrons.com (Postfix) with ESMTPSA id 470E1207F9;\n\tMon, 4 Sep 2017 09:06:19 +0200 (CEST)"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:Content-Type:Cc:\n\tList-Subscribe:List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:\n\tIn-Reply-To:MIME-Version:References:Message-ID:Subject:To:From:Date:Reply-To:\n\tContent-Transfer-Encoding:Content-ID:Content-Description:Resent-Date:\n\tResent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner;\n\tbh=r4GjwRMhh3XaVNyznDVW5lcZWshHyI+mP1DVaVQrdHo=;\n\tb=mxSaiEGahBOqVugoISPh+ddAq\n\tZCXtUpSUOJjY/sDOYqyPatQd1pQvJSjcJspTqWboGfTebxV6Rr4F7rVZSOiBbVutNegYGqxqk7GqZ\n\tcwN/1SGFBFmhTcvGXrDQbmW+UAPghzGByZLtQTTXz7WyQjb1XZlxvr3ZoLJDMuqehyUkva2kpJE24\n\tdSfd1jbmciR4tFJHCs18RJp0iRRiHyM0he5+fJvk779vq+J0xLpCUXBtMhTZZ1Rr0EUdz9SCGUIq9\n\t1xs9AcUlVwkYxSaAKFbLOKfBBX5W4/kng72p1z/oZet9HvQdBCQ+7CTFvZNh6GNjAsdl6d+e9Zh4e\n\t1P8cztbAg==;","X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tmail.free-electrons.com","X-Spam-Level":"","X-Spam-Status":"No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT,\n\tURIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0","Date":"Mon, 4 Sep 2017 09:06:20 +0200","From":"Maxime Ripard ","To":"=?iso-8859-1?q?Andr=E9?= Przywara ","Subject":"Re: [PATCH 01/10] dmaengine: sun6i: Correct setting of clock\n\tautogating register for A83T/H3","Message-ID":"<20170904070620.3lpkmq6nt2qrgwah@flea>","References":"<20170903224100.17893-1-stefan.bruens@rwth-aachen.de>\n\t<20170903224100.17893-2-stefan.bruens@rwth-aachen.de>\n\t","MIME-Version":"1.0","In-Reply-To":"","User-Agent":"NeoMutt/20170714 (1.8.3)","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170904_000651_638702_DD785C75 ","X-CRM114-Status":"GOOD ( 18.48 )","X-Spam-Score":"-1.9 (-)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-1.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"devicetree@vger.kernel.org, Vinod Koul ,\n\tlinux-kernel@vger.kernel.org, Code Kipper , \n\tlinux-sunxi@googlegroups.com, Rob Herring , \n\tdmaengine@vger.kernel.org, Chen-Yu Tsai , Stefan\n\t=?iso-8859-1?q?Br=FCns?= ,\n\tlinux-arm-kernel@lists.infradead.org","Content-Type":"multipart/mixed;\n\tboundary=\"===============0066811077115610907==\"","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}}]