[{"id":1762478,"web_url":"http://patchwork.ozlabs.org/comment/1762478/","msgid":"<20170904093224.62b43efb@nial.brq.redhat.com>","list_archive_url":null,"date":"2017-09-04T07:32:24","subject":"Re: [Qemu-devel] [PATCH v2 2/6] xlnx-zynqmp-pmu: Add the CPU and\n\tmemory","submitter":{"id":11305,"url":"http://patchwork.ozlabs.org/api/people/11305/","name":"Igor Mammedov","email":"imammedo@redhat.com"},"content":"On Fri, 1 Sep 2017 14:00:37 -0700\nAlistair Francis wrote:\n\n> Connect the MicroBlaze CPU and the ROM and RAM memory regions.\n> \n> Signed-off-by: Alistair Francis \n> ---\n> \n> hw/microblaze/xlnx-zynqmp-pmu.c | 65 +++++++++++++++++++++++++++++++++++++++--\n> 1 file changed, 63 insertions(+), 2 deletions(-)\n> \n> diff --git a/hw/microblaze/xlnx-zynqmp-pmu.c b/hw/microblaze/xlnx-zynqmp-pmu.c\n> index fc3c8b236f..33584cfa4d 100644\n> --- a/hw/microblaze/xlnx-zynqmp-pmu.c\n> +++ b/hw/microblaze/xlnx-zynqmp-pmu.c\n> @@ -18,8 +18,11 @@\n> #include \"qemu/osdep.h\"\n> #include \"qapi/error.h\"\n> #include \"qemu-common.h\"\n> +#include \"exec/address-spaces.h\"\n> #include \"hw/boards.h\"\n> +#include \"hw/qdev-properties.h\"\n> #include \"cpu.h\"\n> +#include \"boot.h\"\n> \n> /* Define the PMU device */\n> \n> @@ -27,21 +30,51 @@\n> #define XLNX_ZYNQMP_PMU(obj) OBJECT_CHECK(XlnxZynqMPPMUState, (obj), \\\n> TYPE_XLNX_ZYNQMP_PMU)\n> \n> +#define XLNX_ZYNQMP_PMU_ROM_SIZE 0x8000\n> +#define XLNX_ZYNQMP_PMU_ROM_ADDR 0xFFD00000\n> +#define XLNX_ZYNQMP_PMU_RAM_ADDR 0xFFDC0000\n> +\n> typedef struct XlnxZynqMPPMUState {\n> /*< private >*/\n> DeviceState parent_obj;\n> \n> /*< public >*/\n> + MicroBlazeCPU cpu;\n> } XlnxZynqMPPMUState;\n> \n> static void xlnx_zynqmp_pmu_init(Object *obj)\n> {\n> + XlnxZynqMPPMUState *s = XLNX_ZYNQMP_PMU(obj);\n> \n> + object_initialize(&s->cpu, sizeof(s->cpu),\n> + TYPE_MICROBLAZE_CPU);\n> + object_property_add_child(obj, \"pmu-cpu[*]\", OBJECT(&s->cpu),\n ^^^ why do you use this syntax here?\n\n> + &error_abort);\n> }\n> \n> static void xlnx_zynqmp_pmu_realize(DeviceState *dev, Error **errp)\n> {\n> -\n> + XlnxZynqMPPMUState *s = XLNX_ZYNQMP_PMU(dev);\n> +\n> + object_property_set_uint(OBJECT(&s->cpu), XLNX_ZYNQMP_PMU_ROM_ADDR,\n> + \"base-vectors\", &error_abort);\n> + object_property_set_bool(OBJECT(&s->cpu), true, \"use-stack-protection\",\n> + &error_abort);\n> + object_property_set_uint(OBJECT(&s->cpu), 0, \"use-fpu\", &error_abort);\n> + object_property_set_uint(OBJECT(&s->cpu), 0, \"use-hw-mul\", &error_abort);\n> + object_property_set_bool(OBJECT(&s->cpu), true, \"use-barrel\",\n> + &error_abort);\n> + object_property_set_bool(OBJECT(&s->cpu), true, \"use-msr-instr\",\n> + &error_abort);\n> + object_property_set_bool(OBJECT(&s->cpu), true, \"use-pcmp-instr\",\n> + &error_abort);\n> + object_property_set_bool(OBJECT(&s->cpu), false, \"use-mmu\", &error_abort);\n> + object_property_set_bool(OBJECT(&s->cpu), true, \"endianness\",\n> + &error_abort);\n> + object_property_set_str(OBJECT(&s->cpu), \"8.40.b\", \"version\",\n> + &error_abort);\n> + object_property_set_uint(OBJECT(&s->cpu), 0, \"pvr\", &error_abort);\n> + object_property_set_bool(OBJECT(&s->cpu), true, \"realized\", &error_fatal);\nI'd replace error_fatal here with errp\n\n> }\n> \n> static void xlnx_zynqmp_pmu_class_init(ObjectClass *oc, void *data)\n> @@ -70,7 +103,35 @@ type_init(xlnx_zynqmp_pmu_register_types)\n> \n> static void xlnx_zcu102_pmu_init(MachineState *machine)\n> {\n> -\n> + XlnxZynqMPPMUState *pmu = g_new0(XlnxZynqMPPMUState, 1);\n> + MemoryRegion *address_space_mem = get_system_memory();\n> + MemoryRegion *pmu_rom = g_new(MemoryRegion, 1);\n> + MemoryRegion *pmu_ram = g_new(MemoryRegion, 1);\n> +\n> + /* Create the ROM */\n> + memory_region_init_rom(pmu_rom, NULL, \"xlnx-zcu102-pmu.rom\",\n> + XLNX_ZYNQMP_PMU_ROM_SIZE, &error_fatal);\n> + memory_region_add_subregion(address_space_mem, XLNX_ZYNQMP_PMU_ROM_ADDR,\n> + pmu_rom);\n> +\n> + /* Create the RAM */\n> + memory_region_init_ram(pmu_ram, NULL, \"xlnx-zcu102-pmu.ram\",\n> + machine->ram_size, &error_fatal);\n> + memory_region_add_subregion(address_space_mem, XLNX_ZYNQMP_PMU_RAM_ADDR,\n> + pmu_ram);\n> +\n> + /* Create the PMU device */\n> + object_initialize(pmu, sizeof(XlnxZynqMPPMUState), TYPE_XLNX_ZYNQMP_PMU);\n> + object_property_add_child(OBJECT(machine), \"pmu\", OBJECT(pmu),\n> + &error_abort);\n> + object_property_set_bool(OBJECT(pmu), true, \"realized\", &error_fatal);\n> +\n> + /* Load the kernel */\n> + microblaze_load_kernel(&pmu->cpu, XLNX_ZYNQMP_PMU_RAM_ADDR,\n> + machine->ram_size,\n> + machine->kernel_filename,\n> + machine->dtb,\n> + NULL);\n> }\n> \n> static void xlnx_zcu102_pmu_machine_init(MachineClass *mc)","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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Mon, 04 Sep 2017 03:32:34 -0400","from mx1.redhat.com ([209.132.183.28]:26153)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1dolrw-0001ks-Fj; Mon, 04 Sep 2017 03:32:28 -0400","from smtp.corp.redhat.com\n\t(int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby mx1.redhat.com (Postfix) with ESMTPS id 39CC8806A1;\n\tMon, 4 Sep 2017 07:32:27 +0000 (UTC)","from nial.brq.redhat.com (unknown [10.43.2.241])\n\tby smtp.corp.redhat.com (Postfix) with ESMTP id D46387E235;\n\tMon, 4 Sep 2017 07:32:25 +0000 (UTC)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mx1.redhat.com 39CC8806A1","Date":"Mon, 4 Sep 2017 09:32:24 +0200","From":"Igor Mammedov ","To":"Alistair Francis ","Message-ID":"<20170904093224.62b43efb@nial.brq.redhat.com>","In-Reply-To":"<241130c59df31aebaf4f23b5f151b6b5c91f36fa.1504293917.git.alistair.francis@xilinx.com>","References":"\n\t<241130c59df31aebaf4f23b5f151b6b5c91f36fa.1504293917.git.alistair.francis@xilinx.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=US-ASCII","Content-Transfer-Encoding":"7bit","X-Scanned-By":"MIMEDefang 2.79 on 10.5.11.11","X-Greylist":"Sender IP whitelisted, not delayed by milter-greylist-4.5.16\n\t(mx1.redhat.com [10.5.110.26]);\n\tMon, 04 Sep 2017 07:32:27 +0000 (UTC)","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]","X-Received-From":"209.132.183.28","Subject":"Re: [Qemu-devel] [PATCH v2 2/6] xlnx-zynqmp-pmu: Add the CPU and\n\tmemory","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"edgar.iglesias@xilinx.com, edgar.iglesias@gmail.com, qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org, alistair23@gmail.com","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1763527,"web_url":"http://patchwork.ozlabs.org/comment/1763527/","msgid":"","list_archive_url":null,"date":"2017-09-05T17:36:36","subject":"Re: [Qemu-devel] [PATCH v2 2/6] xlnx-zynqmp-pmu: Add the CPU and\n\tmemory","submitter":{"id":47878,"url":"http://patchwork.ozlabs.org/api/people/47878/","name":"Alistair Francis","email":"alistair.francis@xilinx.com"},"content":"On Mon, Sep 4, 2017 at 12:32 AM, Igor Mammedov wrote:\n> On Fri, 1 Sep 2017 14:00:37 -0700\n> Alistair Francis wrote:\n>\n>> Connect the MicroBlaze CPU and the ROM and RAM memory regions.\n>>\n>> Signed-off-by: Alistair Francis \n>> ---\n>>\n>> hw/microblaze/xlnx-zynqmp-pmu.c | 65 +++++++++++++++++++++++++++++++++++++++--\n>> 1 file changed, 63 insertions(+), 2 deletions(-)\n>>\n>> diff --git a/hw/microblaze/xlnx-zynqmp-pmu.c b/hw/microblaze/xlnx-zynqmp-pmu.c\n>> index fc3c8b236f..33584cfa4d 100644\n>> --- a/hw/microblaze/xlnx-zynqmp-pmu.c\n>> +++ b/hw/microblaze/xlnx-zynqmp-pmu.c\n>> @@ -18,8 +18,11 @@\n>> #include \"qemu/osdep.h\"\n>> #include \"qapi/error.h\"\n>> #include \"qemu-common.h\"\n>> +#include \"exec/address-spaces.h\"\n>> #include \"hw/boards.h\"\n>> +#include \"hw/qdev-properties.h\"\n>> #include \"cpu.h\"\n>> +#include \"boot.h\"\n>>\n>> /* Define the PMU device */\n>>\n>> @@ -27,21 +30,51 @@\n>> #define XLNX_ZYNQMP_PMU(obj) OBJECT_CHECK(XlnxZynqMPPMUState, (obj), \\\n>> TYPE_XLNX_ZYNQMP_PMU)\n>>\n>> +#define XLNX_ZYNQMP_PMU_ROM_SIZE 0x8000\n>> +#define XLNX_ZYNQMP_PMU_ROM_ADDR 0xFFD00000\n>> +#define XLNX_ZYNQMP_PMU_RAM_ADDR 0xFFDC0000\n>> +\n>> typedef struct XlnxZynqMPPMUState {\n>> /*< private >*/\n>> DeviceState parent_obj;\n>>\n>> /*< public >*/\n>> + MicroBlazeCPU cpu;\n>> } XlnxZynqMPPMUState;\n>>\n>> static void xlnx_zynqmp_pmu_init(Object *obj)\n>> {\n>> + XlnxZynqMPPMUState *s = XLNX_ZYNQMP_PMU(obj);\n>>\n>> + object_initialize(&s->cpu, sizeof(s->cpu),\n>> + TYPE_MICROBLAZE_CPU);\n>> + object_property_add_child(obj, \"pmu-cpu[*]\", OBJECT(&s->cpu),\n> ^^^ why do you use this syntax here?\n>\n\nWoops, that was a left over from the ARM ZynqMP. I'll remove the '[*]'\n\n>> + &error_abort);\n>> }\n>>\n>> static void xlnx_zynqmp_pmu_realize(DeviceState *dev, Error **errp)\n>> {\n>> -\n>> + XlnxZynqMPPMUState *s = XLNX_ZYNQMP_PMU(dev);\n>> +\n>> + object_property_set_uint(OBJECT(&s->cpu), XLNX_ZYNQMP_PMU_ROM_ADDR,\n>> + \"base-vectors\", &error_abort);\n>> + object_property_set_bool(OBJECT(&s->cpu), true, \"use-stack-protection\",\n>> + &error_abort);\n>> + object_property_set_uint(OBJECT(&s->cpu), 0, \"use-fpu\", &error_abort);\n>> + object_property_set_uint(OBJECT(&s->cpu), 0, \"use-hw-mul\", &error_abort);\n>> + object_property_set_bool(OBJECT(&s->cpu), true, \"use-barrel\",\n>> + &error_abort);\n>> + object_property_set_bool(OBJECT(&s->cpu), true, \"use-msr-instr\",\n>> + &error_abort);\n>> + object_property_set_bool(OBJECT(&s->cpu), true, \"use-pcmp-instr\",\n>> + &error_abort);\n>> + object_property_set_bool(OBJECT(&s->cpu), false, \"use-mmu\", &error_abort);\n>> + object_property_set_bool(OBJECT(&s->cpu), true, \"endianness\",\n>> + &error_abort);\n>> + object_property_set_str(OBJECT(&s->cpu), \"8.40.b\", \"version\",\n>> + &error_abort);\n>> + object_property_set_uint(OBJECT(&s->cpu), 0, \"pvr\", &error_abort);\n>> + object_property_set_bool(OBJECT(&s->cpu), true, \"realized\", &error_fatal);\n> I'd replace error_fatal here with errp\n\nWill do.\n\nThanks,\nAlistair\n\n>\n>> }\n>>\n>> static void xlnx_zynqmp_pmu_class_init(ObjectClass *oc, void *data)\n>> @@ -70,7 +103,35 @@ type_init(xlnx_zynqmp_pmu_register_types)\n>>\n>> static void xlnx_zcu102_pmu_init(MachineState *machine)\n>> {\n>> -\n>> + XlnxZynqMPPMUState *pmu = g_new0(XlnxZynqMPPMUState, 1);\n>> + MemoryRegion *address_space_mem = get_system_memory();\n>> + MemoryRegion *pmu_rom = g_new(MemoryRegion, 1);\n>> + MemoryRegion *pmu_ram = g_new(MemoryRegion, 1);\n>> +\n>> + /* Create the ROM */\n>> + memory_region_init_rom(pmu_rom, NULL, \"xlnx-zcu102-pmu.rom\",\n>> + XLNX_ZYNQMP_PMU_ROM_SIZE, &error_fatal);\n>> + memory_region_add_subregion(address_space_mem, XLNX_ZYNQMP_PMU_ROM_ADDR,\n>> + pmu_rom);\n>> +\n>> + /* Create the RAM */\n>> + memory_region_init_ram(pmu_ram, NULL, \"xlnx-zcu102-pmu.ram\",\n>> + machine->ram_size, &error_fatal);\n>> + memory_region_add_subregion(address_space_mem, XLNX_ZYNQMP_PMU_RAM_ADDR,\n>> + pmu_ram);\n>> +\n>> + /* Create the PMU device */\n>> + object_initialize(pmu, sizeof(XlnxZynqMPPMUState), TYPE_XLNX_ZYNQMP_PMU);\n>> + object_property_add_child(OBJECT(machine), \"pmu\", OBJECT(pmu),\n>> + &error_abort);\n>> + object_property_set_bool(OBJECT(pmu), true, \"realized\", &error_fatal);\n>> +\n>> + /* Load the kernel */\n>> + microblaze_load_kernel(&pmu->cpu, XLNX_ZYNQMP_PMU_RAM_ADDR,\n>> + machine->ram_size,\n>> + machine->kernel_filename,\n>> + machine->dtb,\n>> + NULL);\n>> }\n>>\n>> static void xlnx_zcu102_pmu_machine_init(MachineClass *mc)\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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