[{"id":1764368,"web_url":"http://patchwork.ozlabs.org/comment/1764368/","msgid":"","list_archive_url":null,"date":"2017-09-06T20:52:26","subject":"Re: [patch v7 2/4] drivers: jtag: Add Aspeed SoC 24xx and 25xx\n\tfamilies JTAG master driver","submitter":{"id":30,"url":"http://patchwork.ozlabs.org/api/people/30/","name":"Arnd Bergmann","email":"arnd@arndb.de"},"content":"On Fri, Sep 1, 2017 at 6:06 PM, Oleksandr Shamray\n wrote:\n> Driver adds support of Aspeed 2500/2400 series SOC JTAG master controller.\n>\n> Driver implements the following jtag ops:\n> - freq_get;\n> - freq_set;\n> - status_get;\n> - idle;\n> - xfer;\n>\n> It has been tested on Mellanox system with BMC equipped with\n> Aspeed 2520 SoC for programming CPLD devices.\n>\n> Signed-off-by: Oleksandr Shamray \n> Signed-off-by: Jiri Pirko \n\nNo further comments about this driver, if there is agreement about the subsystem\nin general, it looks good to go in.\n\nAcked-by: Arnd Bergmann ","X-Original-To":["incoming@patchwork.ozlabs.org","openbmc@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","openbmc@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xnbPY5jRvz9sRY\n\tfor ;\n\tThu, 7 Sep 2017 06:52:33 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xnbPY3tCnzDrT1\n\tfor ;\n\tThu, 7 Sep 2017 06:52:33 +1000 (AEST)","from mail-oi0-x242.google.com (mail-oi0-x242.google.com\n\t[IPv6:2607:f8b0:4003:c06::242])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xnbPT0x9MzDqZf\n\tfor ; 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\n\tWed, 06 Sep 2017 13:52:27 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"<1504281966-6199-3-git-send-email-oleksandrs@mellanox.com>","References":"<1504281966-6199-1-git-send-email-oleksandrs@mellanox.com>\n\t<1504281966-6199-3-git-send-email-oleksandrs@mellanox.com>","From":"Arnd Bergmann ","Date":"Wed, 6 Sep 2017 22:52:26 +0200","X-Google-Sender-Auth":"5paTLAYr-MhdgCIcI1DQIdEMlRQ","Message-ID":"","Subject":"Re: [patch v7 2/4] drivers: jtag: Add Aspeed SoC 24xx and 25xx\n\tfamilies JTAG master driver","To":"Oleksandr Shamray ","Content-Type":"text/plain; charset=\"UTF-8\"","X-BeenThere":"openbmc@lists.ozlabs.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"Development list for OpenBMC ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"devicetree@vger.kernel.org, Mauro Carvalho Chehab ,\n\t=?utf-8?b?SmnFmcOtIFDDrXJrbw==?= ,\n\tsystem-sw-low-level@mellanox.com, gregkh , \n\tOpenBMC Maillist , Linux Kernel Mailing List\n\t, \n\topenocd-devel-owner@lists.sourceforge.net, mec@shout.net, Jiri Pirko\n\t, Rob Herring , \n\tlinux-serial@vger.kernel.org, vadimp@maellanox.com, Tobias Klauser\n\t, Linux API , David\n\tMiller , Linux ARM\n\t","Errors-To":"openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org","Sender":"\"openbmc\"\n\t"}},{"id":1765057,"web_url":"http://patchwork.ozlabs.org/comment/1765057/","msgid":"","list_archive_url":null,"date":"2017-09-08T03:36:57","subject":"Re: [patch v7 2/4] drivers: jtag: Add Aspeed SoC 24xx and 25xx\n\tfamilies JTAG master driver","submitter":{"id":48628,"url":"http://patchwork.ozlabs.org/api/people/48628/","name":"Joel Stanley","email":"joel@jms.id.au"},"content":"Hello Oleksandr,\n\nOn Sat, Sep 2, 2017 at 1:36 AM, Oleksandr Shamray\n wrote:\n> Driver adds support of Aspeed 2500/2400 series SOC JTAG master controller.\n\nLooks good. I have some small comments. The most important is the\ncompatible string.\n\n\n> --- a/drivers/jtag/Kconfig\n> +++ b/drivers/jtag/Kconfig\n> @@ -14,3 +14,16 @@ menuconfig JTAG\n>\n> To compile this driver as a module, choose M here: the module will\n> be called jtag.\n> +\n> +menuconfig JTAG_ASPEED\n> + tristate \"Aspeed SoC JTAG controller support\"\n> + depends on JTAG && HAS_IOMEM\n\nYou could add this if you want:\n\n depends ARCH_ASPEED || COMPILE_TEST\n\n> + ---help---\n> + This provides a support for Aspeed JTAG device, equipped on\n> + Aspeed SoC 24xx and 25xx families. Drivers allows programming\n> + of hardware devices, connected to SoC through the JTAG interface.\n> +\n\n> +\n> +static char *end_status_str[] = {\"idle\", \"ir pause\", \"drpause\"};\n> +\n> +static u32 aspeed_jtag_read(struct aspeed_jtag *aspeed_jtag, u32 reg)\n> +{\n> + return readl(aspeed_jtag->reg_base + reg);\n> +}\n> +\n> +static void\n> +aspeed_jtag_write(struct aspeed_jtag *aspeed_jtag, u32 val, u32 reg)\n> +{\n> + writel(val, aspeed_jtag->reg_base + reg);\n> +}\n> +\n> +static int aspeed_jtag_freq_set(struct jtag *jtag, __u32 freq)\n\nWhat's the __u32 for (the __ part)?\n\n> +{\n> + struct aspeed_jtag *aspeed_jtag = jtag_priv(jtag);\n> + unsigned long apb_frq;\n> + u32 tck_val;\n> + u16 div;\n> +\n> + apb_frq = clk_get_rate(aspeed_jtag->pclk);\n> + div = (apb_frq % freq == 0) ? (apb_frq / freq) - 1 : (apb_frq / freq);\n> + tck_val = aspeed_jtag_read(aspeed_jtag, ASPEED_JTAG_TCK);\n> + aspeed_jtag_write(aspeed_jtag,\n> + (tck_val & ASPEED_JTAG_TCK_DIVISOR_MASK) | div,\n> + ASPEED_JTAG_TCK);\n> + return 0;\n> +}\n\n> +\n> +static int aspeed_jtag_xfer(struct jtag *jtag, struct jtag_xfer *xfer)\n> +{\n> + static const char sm_update_shiftir[] = {1, 1, 0, 0};\n> + static const char sm_update_shiftdr[] = {1, 0, 0};\n> + static const char sm_pause_idle[] = {1, 1, 0};\n> + static const char sm_pause_update[] = {1, 1};\n\nNit: I was confused by the char, perhaps u8?\n\n> +int aspeed_jtag_init(struct platform_device *pdev,\n> + struct aspeed_jtag *aspeed_jtag)\n> +{\n> + struct resource *res;\n> + int err;\n> +\n> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n> + aspeed_jtag->reg_base = devm_ioremap_resource(aspeed_jtag->dev, res);\n> + if (IS_ERR(aspeed_jtag->reg_base)) {\n> + err = -ENOMEM;\n> + goto out_region;\n\nCan you just return here?\n\n> + }\n> +\n> + aspeed_jtag->pclk = devm_clk_get(aspeed_jtag->dev, NULL);\n> + if (IS_ERR(aspeed_jtag->pclk)) {\n> + dev_err(aspeed_jtag->dev, \"devm_clk_get failed\\n\");\n> + return PTR_ERR(aspeed_jtag->pclk);\n> + }\n> +\n> + clk_prepare_enable(aspeed_jtag->pclk);\n> +\n> + aspeed_jtag->irq = platform_get_irq(pdev, 0);\n> + if (aspeed_jtag->irq < 0) {\n> + dev_err(aspeed_jtag->dev, \"no irq specified\\n\");\n> + err = -ENOENT;\n> + goto out_region;\n> + }\n> +\n> + /* Enable clock */\n> + aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_CTL_ENG_EN |\n> + ASPEED_JTAG_CTL_ENG_OUT_EN, ASPEED_JTAG_CTRL);\n> + aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_SW_MODE_EN |\n> + ASPEED_JTAG_SW_MODE_TDIO, ASPEED_JTAG_SW);\n> +\n> + err = devm_request_irq(aspeed_jtag->dev, aspeed_jtag->irq,\n> + aspeed_jtag_interrupt, 0,\n> + \"aspeed-jtag\", aspeed_jtag);\n> + if (err) {\n> + dev_err(aspeed_jtag->dev, \"aspeed_jtag unable to get IRQ\");\n> + goto out_region;\n> + }\n\nCan we grab the IRQ before enabling the clock? If not, we should\ndisable the clock in the error path.\n\n\n> + dev_dbg(&pdev->dev, \"aspeed_jtag:IRQ %d.\\n\", aspeed_jtag->irq);\n> +\n> + aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_ISR_INST_PAUSE |\n> + ASPEED_JTAG_ISR_INST_COMPLETE |\n> + ASPEED_JTAG_ISR_DATA_PAUSE |\n> + ASPEED_JTAG_ISR_DATA_COMPLETE |\n> + ASPEED_JTAG_ISR_INST_PAUSE_EN |\n> + ASPEED_JTAG_ISR_INST_COMPLETE_EN |\n> + ASPEED_JTAG_ISR_DATA_PAUSE_EN |\n> + ASPEED_JTAG_ISR_DATA_COMPLETE_EN,\n> + ASPEED_JTAG_ISR);\n> +\n> + aspeed_jtag->flag = 0;\n> + init_waitqueue_head(&aspeed_jtag->jtag_wq);\n> + return 0;\n> +\n> +out_region:\n> + release_mem_region(res->start, resource_size(res));\n\nI don't think this is necessary.\n\n> + return err;\n> +}\n> +\n> +int aspeed_jtag_deinit(struct platform_device *pdev,\n> + struct aspeed_jtag *aspeed_jtag)\n> +{\n> + aspeed_jtag_write(aspeed_jtag, 0, ASPEED_JTAG_ISR);\n> + devm_free_irq(aspeed_jtag->dev, aspeed_jtag->irq, aspeed_jtag);\n\nThe IRQ freeing happen automatically thanks to devm.\n\n> + /* Disabe clock */\n\nDisable\n\n> + aspeed_jtag_write(aspeed_jtag, 0, ASPEED_JTAG_CTRL);\n> + clk_disable_unprepare(aspeed_jtag->pclk);\n> + return 0;\n> +}\n> +\n> +static const struct jtag_ops aspeed_jtag_ops = {\n> + .freq_get = aspeed_jtag_freq_get,\n> + .freq_set = aspeed_jtag_freq_set,\n> + .status_get = aspeed_jtag_status_get,\n> + .idle = aspeed_jtag_idle,\n> + .xfer = aspeed_jtag_xfer\n> +};\n> +\n> +static int aspeed_jtag_probe(struct platform_device *pdev)\n> +{\n> + struct aspeed_jtag *aspeed_jtag;\n> + struct jtag *jtag;\n> + int err;\n> +\n> + if (!of_device_is_compatible(pdev->dev.of_node, \"aspeed,aspeed-jtag\"))\n> + return -ENOMEM;\n> +\n> + jtag = jtag_alloc(sizeof(*aspeed_jtag), &aspeed_jtag_ops);\n> + if (!jtag)\n> + return -ENODEV;\n> +\n> + platform_set_drvdata(pdev, jtag);\n> + aspeed_jtag = jtag_priv(jtag);\n> + aspeed_jtag->dev = &pdev->dev;\n> +\n> + /* Initialize device*/\n> + err = aspeed_jtag_init(pdev, aspeed_jtag);\n> + if (err)\n> + goto err_jtag_init;\n> +\n> + /* Initialize JTAG core structure*/\n> + err = jtag_register(jtag);\n> + if (err)\n> + goto err_jtag_register;\n> +\n> + return 0;\n> +\n> +err_jtag_register:\n> + aspeed_jtag_deinit(pdev, aspeed_jtag);\n> +err_jtag_init:\n> + jtag_free(jtag);\n> + return err;\n> +}\n> +\n> +static int aspeed_jtag_remove(struct platform_device *pdev)\n> +{\n> + struct jtag *jtag;\n> +\n> + jtag = platform_get_drvdata(pdev);\n> + aspeed_jtag_deinit(pdev, jtag_priv(jtag));\n> + jtag_unregister(jtag);\n> + jtag_free(jtag);\n> + return 0;\n> +}\n> +\n> +static const struct of_device_id aspeed_jtag_of_match[] = {\n> + { .compatible = \"aspeed,aspeed2400-jtag\", },\n> + { .compatible = \"aspeed,aspeed2500-jtag\", },\n\nThe convention is to use ast2500 for our compatible strings, so these should be:\n\n aspeed,ast2500-jtag\n aspeed,ast2400-jtag\n\nCheers,\n\nJoel","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","openbmc@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","openbmc@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xpNLR50CNz9sQl\n\tfor ;\n\tFri, 8 Sep 2017 13:37:35 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xpNLR1GjLzDrYs\n\tfor ;\n\tFri, 8 Sep 2017 13:37:35 +1000 (AEST)","from mail-lf0-x243.google.com (mail-lf0-x243.google.com\n\t[IPv6:2a00:1450:4010:c07::243])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xpNLB5SkdzDrVv\n\tfor ; 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charset=\"UTF-8\"","X-BeenThere":"openbmc@lists.ozlabs.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"Development list for OpenBMC ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"devicetree , mchehab@kernel.org,\n\tjiri@resnulli.us, Arnd Bergmann ,\n\tsystem-sw-low-level@mellanox.com, Greg KH ,\n\tOpenBMC Maillist ,\n\tLinux Kernel Mailing List ,\n\topenocd-devel-owner@lists.sourceforge.net, mec@shout.net,\n\tJiri Pirko , Rob Herring ,\n\tlinux-serial@vger.kernel.org, vadimp@maellanox.com,\n\tTobias Klauser , linux-api@vger.kernel.org,\n\t\"David S . Miller\" ,\n\tLinux ARM ","Errors-To":"openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org","Sender":"\"openbmc\"\n\t"}}]