[{"id":1762680,"web_url":"http://patchwork.ozlabs.org/comment/1762680/","msgid":"","list_archive_url":null,"date":"2017-09-04T14:14:58","subject":"Re: [PATCH][GCC][ARM] Dot Product commandline options [Patch (1/8)]","submitter":{"id":67887,"url":"http://patchwork.ozlabs.org/api/people/67887/","name":"Richard Earnshaw","email":"Richard.Earnshaw@arm.com"},"content":"On 01/09/17 14:19, Tamar Christina wrote:\n> Hi All,\n> \n> This patch adds support for the +dotprod extension to ARM.\n> Dot Product requires Adv.SIMD to work and so enables this option\n> by default when enabled.\n> \n> It is available from ARMv8.2-a and onwards and is enabled by\n> default on Cortex-A55 and Cortex-A75.\n> \n> Regtested and bootstrapped on arm-none-eabi and no issues.\n> \n> Ok for trunk?\n> \n> gcc/\n> 2017-09-01 Tamar Christina \n> \n> \t* config/arm/arm.h (TARGET_DOTPROD): New.\n> \t* config/arm/arm.c (arm_arch_dotprod): New.\n> \t(arm_option_reconfigure_globals): Add arm_arch_dotprod.\n> \t* config/arm/arm-c.c (__ARM_FEATURE_DOTPROD): New.\n> \t* config/arm/arm-cpus.in (cortex-a55, cortex-75): Enabled +dotprod.\n> \t(armv8.2-a, cortex-a75.cortex-a55): Likewise.\n> \t* config/arm/arm-isa.h (isa_bit_dotprod, ISA_DOTPROD): New.\n> \t* config/arm/t-multilib (v8_2_a_simd_variants): Add dotprod.\n> \t* doc/invoke.texi (armv8.2-a): Document dotprod\n> \n> \n> 7949-diff.patch\n> \n> \n> diff --git a/gcc/config/arm/arm-c.c b/gcc/config/arm/arm-c.c\n> index 55472434c3a6e90c5693bbaabd3265f7d968787f..295f03bf8ee02be7c89ed2967d283be206e9f25a 100644\n> --- a/gcc/config/arm/arm-c.c\n> +++ b/gcc/config/arm/arm-c.c\n> @@ -73,6 +73,7 @@ arm_cpu_builtins (struct cpp_reader* pfile)\n> def_or_undef_macro (pfile, \"__ARM_FEATURE_QRDMX\", TARGET_NEON_RDMA);\n> \n> def_or_undef_macro (pfile, \"__ARM_FEATURE_CRC32\", TARGET_CRC32);\n> + def_or_undef_macro (pfile, \"__ARM_FEATURE_DOTPROD\", TARGET_DOTPROD);\n> def_or_undef_macro (pfile, \"__ARM_32BIT_STATE\", TARGET_32BIT);\n> \n> cpp_undef (pfile, \"__ARM_FEATURE_CMSE\");\n> diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in\n> index d009a9e18acb093aefe0f9d8d6de49489fc2325c..7707eec5edf36b0cb4339bc52bc45a92b6ea007f 100644\n> --- a/gcc/config/arm/arm-cpus.in\n> +++ b/gcc/config/arm/arm-cpus.in\n> @@ -357,6 +357,7 @@ begin arch armv8.2-a\n> option crypto add FP_ARMv8 CRYPTO\n> option nocrypto remove ALL_CRYPTO\n> option nofp remove ALL_FP\n> + option dotprod add FP_ARMv8 DOTPROD\n> end arch armv8.2-a\n> \n> begin arch armv8-m.base\n> @@ -1269,9 +1270,10 @@ begin cpu cortex-a55\n> cname cortexa55\n> tune for cortex-a53\n> tune flags LDSCHED\n> - architecture armv8.2-a+fp16\n> + architecture armv8.2-a+fp16+dotprod\n> fpu neon-fp-armv8\n> option crypto add FP_ARMv8 CRYPTO\n> + option dotprod add FP_ARMv8 DOTPROD\n> option nofp remove ALL_FP\n> costs cortex_a53\n> end cpu cortex-a55\n> @@ -1280,9 +1282,10 @@ begin cpu cortex-a75\n> cname cortexa75\n> tune for cortex-a57\n> tune flags LDSCHED\n> - architecture armv8.2-a+fp16\n> + architecture armv8.2-a+fp16+dotprod\n> fpu neon-fp-armv8\n> option crypto add FP_ARMv8 CRYPTO\n> + option dotprod add FP_ARMv8 DOTPROD\n> costs cortex_a73\n> end cpu cortex-a75\n> \n> @@ -1292,9 +1295,10 @@ begin cpu cortex-a75.cortex-a55\n> cname cortexa75cortexa55\n> tune for cortex-a53\n> tune flags LDSCHED\n> - architecture armv8.2-a+fp16\n> + architecture armv8.2-a+fp16+dotprod\n> fpu neon-fp-armv8\n> option crypto add FP_ARMv8 CRYPTO\n> + option dotprod add FP_ARMv8 DOTPROD\n> costs cortex_a73\n> end cpu cortex-a75.cortex-a55\n> \n> diff --git a/gcc/config/arm/arm-isa.h b/gcc/config/arm/arm-isa.h\n> index dbd29eaa52f2007498c2aff6263b8b6c3a70e2c2..60a50edf08dd7d3ac9ad46967250f4dcc6b8768b 100644\n> --- a/gcc/config/arm/arm-isa.h\n> +++ b/gcc/config/arm/arm-isa.h\n> @@ -66,6 +66,7 @@ enum isa_feature\n> isa_bit_fp_d32,\t/* 32 Double precision registers. */\n> isa_bit_crypto,\t/* Crypto extension to ARMv8. */\n> isa_bit_fp16,\t/* FP16 data processing (half-precision float). */\n> + isa_bit_dotprod,\t/* Dot Product instructions. */\n> \n> /* ISA Quirks (errata?). Don't forget to add this to the list of\n> all quirks below. */\n> @@ -159,6 +160,7 @@ enum isa_feature\n> #define ISA_FP_ARMv8\tISA_FPv5, ISA_FP_D32\n> #define ISA_NEON\tISA_FP_D32, isa_bit_neon\n> #define ISA_CRYPTO\tISA_NEON, isa_bit_crypto\n> +#define ISA_DOTPROD\tISA_NEON, isa_bit_dotprod\n\nYou also need to update ISA_ALL_FP to include your new feature;\notherwise it won't be correctly removed if +nofp is used.\n\n> \n> /* List of all quirk bits to strip out when comparing CPU features with\n> architectures. */\n> diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h\n> index 4f53583cf0219de4329bc64a47a5a42c550ff354..44a95bf7eb2eab8e3cf07ac9cc7aad3d9997b27f 100644\n> --- a/gcc/config/arm/arm.h\n> +++ b/gcc/config/arm/arm.h\n> @@ -210,6 +210,11 @@ extern tree arm_fp16_type_node;\n> /* FPU supports ARMv8.1 Adv.SIMD extensions. */\n> #define TARGET_NEON_RDMA (TARGET_NEON && arm_arch8_1)\n> \n> +/* Supports for Dot Product AdvSIMD extensions. */\n> +#define TARGET_DOTPROD (TARGET_NEON\t\t\t\t\t\\\n> +\t\t\t&& bitmap_bit_p (arm_active_target.isa,\t\t\\\n> +\t\t\t\t\tisa_bit_dotprod))\n> +\n> /* FPU supports the floating point FP16 instructions for ARMv8.2 and later. */\n> #define TARGET_VFP_FP16INST \\\n> (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP5 && arm_fp16_inst)\n> diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c\n> index 71379dd5afc4c0dd62fdafd08777793d2ad47ae7..486591137f95cfb2e51adb7082f346edf84449de 100644\n> --- a/gcc/config/arm/arm.c\n> +++ b/gcc/config/arm/arm.c\n> @@ -952,6 +952,9 @@ int arm_condexec_masklen = 0;\n> /* Nonzero if chip supports the ARMv8 CRC instructions. */\n> int arm_arch_crc = 0;\n> \n> +/* Nonzero if chip supports the AdvSIMD Dot Product instructions. */\n> +int arm_arch_dotprod = 0;\n> +\n> /* Nonzero if chip supports the ARMv8-M security extensions. */\n> int arm_arch_cmse = 0;\n> \n> @@ -3594,6 +3597,8 @@ arm_option_reconfigure_globals (void)\n> arm_arch_cmse = bitmap_bit_p (arm_active_target.isa, isa_bit_cmse);\n> arm_fp16_inst = bitmap_bit_p (arm_active_target.isa, isa_bit_fp16);\n> arm_arch_lpae = bitmap_bit_p (arm_active_target.isa, isa_bit_lpae);\n> + arm_arch_dotprod = bitmap_bit_p (arm_active_target.isa, isa_bit_dotprod);\n> +\n> if (arm_fp16_inst)\n> {\n> if (arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE)\n> diff --git a/gcc/config/arm/t-multilib b/gcc/config/arm/t-multilib\n> index ec4b76dbc8fc56093c2b27c95e0947558496fe5a..47f3673160a766c5b1b8972f7670355f2c357b56 100644\n> --- a/gcc/config/arm/t-multilib\n> +++ b/gcc/config/arm/t-multilib\n> @@ -68,7 +68,7 @@ v7ve_vfpv4_simd_variants := +simd\n> v8_a_nosimd_variants\t:= +crc\n> v8_a_simd_variants\t:= $(call all_feat_combs, simd crypto)\n> v8_1_a_simd_variants\t:= $(call all_feat_combs, simd crypto)\n> -v8_2_a_simd_variants\t:= $(call all_feat_combs, simd fp16 crypto)\n> +v8_2_a_simd_variants\t:= $(call all_feat_combs, simd fp16 crypto dotprod)\n> \n> \n> ifneq (,$(HAS_APROFILE))\n> diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi\n> index 64363e54a00c56a3de545735620189f7ec0cde04..4cb5836a9da22681d192c3750fc8e5a50024ac10 100644\n> --- a/gcc/doc/invoke.texi\n> +++ b/gcc/doc/invoke.texi\n> @@ -15492,6 +15492,10 @@ The ARMv8.1 Advanced SIMD and floating-point instructions.\n> The cryptographic instructions. This also enables the Advanced SIMD and\n> floating-point instructions.\n> \n> +@item +dotprod\n> +Enable the Dot Product extension. This also enables Advanced SIMD instructions\n> +and allows auto vectorization of dot products to the Dot Product instructions.\n> +\n\nNo need to talk about auto-vectorization. I think you should use nearly\nidentical wording to the +fp16 option - ie it also enables Adv SIMD and FP.\n> @item +nocrypto\n> Disable the cryptographic extension.\n> \n> \n\nOK with those changes.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list gcc-patches@gcc.gnu.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=gcc-patches-return-461422-incoming=patchwork.ozlabs.org@gcc.gnu.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org\n\theader.b=\"G6CVEhSl\"; dkim-atps=neutral","sourceware.org; auth=none"],"Received":["from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xmBhd420cz9s7C\n\tfor ;\n\tTue, 5 Sep 2017 00:15:44 +1000 (AEST)","(qmail 13145 invoked by alias); 4 Sep 2017 14:15:35 -0000","(qmail 9561 invoked by uid 89); 4 Sep 2017 14:15:32 -0000","from usa-sjc-mx-foss1.foss.arm.com (HELO foss.arm.com)\n\t(217.140.101.70) by sourceware.org\n\t(qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP;\n\tMon, 04 Sep 2017 14:15:24 +0000","from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249])\tby\n\tusa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id\n\tC638B15A2; Mon, 4 Sep 2017 07:15:15 -0700 (PDT)","from e105689-lin.cambridge.arm.com (e105689-lin.cambridge.arm.com\n\t[10.2.207.32])\tby usa-sjc-imap-foss1.foss.arm.com (Postfix)\n\twith ESMTPSA id 257C83F3E1; Mon, 4 Sep 2017 07:15:13 -0700 (PDT)"],"DomainKey-Signature":"a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender\n\t:subject:to:cc:references:from:message-id:date:mime-version\n\t:in-reply-to:content-type:content-transfer-encoding; q=dns; s=\n\tdefault; b=FIgEHZYQbJB/gHxeBOg7lgQ4ufbFAPeqN+h0GcOaYjqvLq0kIfHNY\n\tcQwDCCQP8jLCWQNGpMhLk/9fO06mFIRz+5YwQUdNijlw60dzXR0J9B/Y6/jUqNW0\n\tNbp2UdG10AUGRqDUrYdZDhT6Yiooa7PGyCXr5mvIQ6kslKKxMkeO3Q=","DKIM-Signature":"v=1; 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Linux x86_64;\n\trv:52.0) Gecko/20100101 Thunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"<20170901131912.GA31822@arm.com>","Content-Type":"text/plain; charset=us-ascii","Content-Transfer-Encoding":"7bit"}},{"id":1767748,"web_url":"http://patchwork.ozlabs.org/comment/1767748/","msgid":"<59B90213.3020906@foss.arm.com>","list_archive_url":null,"date":"2017-09-13T10:01:55","subject":"Re: [PATCH][GCC][ARM] Dot Product commandline options [Patch (1/8)]","submitter":{"id":66284,"url":"http://patchwork.ozlabs.org/api/people/66284/","name":"Kyrill Tkachov","email":"kyrylo.tkachov@foss.arm.com"},"content":"Hi Tamar,\n\nOn 01/09/17 14:19, Tamar Christina wrote:\n> Hi All,\n>\n> This patch adds support for the +dotprod extension to ARM.\n> Dot Product requires Adv.SIMD to work and so enables this option\n> by default when enabled.\n>\n> It is available from ARMv8.2-a and onwards and is enabled by\n> default on Cortex-A55 and Cortex-A75.\n>\n> Regtested and bootstrapped on arm-none-eabi and no issues.\n\nI'm assuming you mean arm-none-linux-gnueabihf :)\n\n> Ok for trunk?\n>\n> gcc/\n> 2017-09-01 Tamar Christina \n>\n> \t* config/arm/arm.h (TARGET_DOTPROD): New.\n> \t* config/arm/arm.c (arm_arch_dotprod): New.\n> \t(arm_option_reconfigure_globals): Add arm_arch_dotprod.\n> \t* config/arm/arm-c.c (__ARM_FEATURE_DOTPROD): New.\n> \t* config/arm/arm-cpus.in (cortex-a55, cortex-75): Enabled +dotprod.\n> \t(armv8.2-a, cortex-a75.cortex-a55): Likewise.\n> \t* config/arm/arm-isa.h (isa_bit_dotprod, ISA_DOTPROD): New.\n\narm-isa.h is now autogenerated after r251799 so you'll need to rebase on \ntop of that.\nThat being said, that patch was temporarily reverted [1] so you'll have \nto apply it manually in your\ntree to rebase, or wait until it is reapplied.\n\n[1] https://gcc.gnu.org/ml/gcc-patches/2017-09/msg00579.html\n\nThe patch looks ok to me otherwise with a documentation nit below.\n\n> \t* config/arm/t-multilib (v8_2_a_simd_variants): Add dotprod.\n> \t* doc/invoke.texi (armv8.2-a): Document dotprod\n>\n\n--- a/gcc/doc/invoke.texi\n+++ b/gcc/doc/invoke.texi\n@@ -15492,6 +15492,10 @@ The ARMv8.1 Advanced SIMD and floating-point instructions.\n The cryptographic instructions. This also enables the Advanced SIMD and\n floating-point instructions.\n \n+@item +dotprod\n+Enable the Dot Product extension. This also enables Advanced SIMD instructions\n+and allows auto vectorization of dot products to the Dot Product instructions.\n\nThis should be \"auto-vectorization\"\n\nThanks,\nKyrill","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list gcc-patches@gcc.gnu.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=gcc-patches-return-462012-incoming=patchwork.ozlabs.org@gcc.gnu.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org\n\theader.b=\"o2nJjkUJ\"; dkim-atps=neutral","sourceware.org; auth=none"],"Received":["from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xscdv1V85z9s9Y\n\tfor ;\n\tWed, 13 Sep 2017 20:02:10 +1000 (AEST)","(qmail 111552 invoked by alias); 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Linux x86_64;\n\trv:31.0) Gecko/20100101 Thunderbird/31.2.0","MIME-Version":"1.0","To":"Tamar Christina , gcc-patches@gcc.gnu.org","CC":"nd@arm.com, Ramana.Radhakrishnan@arm.com, Richard.Earnshaw@arm.com,\n\tnickc@redhat.com","Subject":"Re: [PATCH][GCC][ARM] Dot Product commandline options [Patch (1/8)]","References":"<20170901131912.GA31822@arm.com>","In-Reply-To":"<20170901131912.GA31822@arm.com>","Content-Type":"text/plain; charset=utf-8; format=flowed","Content-Transfer-Encoding":"7bit"}},{"id":1781564,"web_url":"http://patchwork.ozlabs.org/comment/1781564/","msgid":"","list_archive_url":null,"date":"2017-10-06T12:44:21","subject":"Re: [PATCH][GCC][ARM] Dot Product commandline options [Patch (1/8)]","submitter":{"id":69689,"url":"http://patchwork.ozlabs.org/api/people/69689/","name":"Tamar Christina","email":"Tamar.Christina@arm.com"},"content":"Hi All,\n\nThis is a respin of the patch with the feedback processed.\n\nRegtested on arm-none-eabi, armeb-none-eabi,\naarch64-none-elf and aarch64_be-none-elf with no issues found.\n\nOk for trunk?\n\ngcc/\n2017-10-06 Tamar Christina \n\n * config/arm/arm.h (TARGET_DOTPROD): New.\n * config/arm/arm.c (arm_arch_dotprod): New.\n (arm_option_reconfigure_globals): Add arm_arch_dotprod.\n * config/arm/arm-c.c (__ARM_FEATURE_DOTPROD): New.\n * config/arm/arm-cpus.in (cortex-a55, cortex-75): Enabled +dotprod.\n (armv8.2-a, cortex-a75.cortex-a55): Likewise.\n (feature dotprod, group dotprod, ALL_SIMD_INTERNAL): New.\n (ALL_FPU_INTERNAL): Use ALL_SIMD_INTERNAL.\n * config/arm/t-multilib (v8_2_a_simd_variants): Add dotprod.\n * doc/invoke.texi (armv8.2-a): Document dotprod","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list gcc-patches@gcc.gnu.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org\n\t(client-ip=209.132.180.131; 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gcc-patches@gcc.gnu.org\n> Cc: nd; Ramana Radhakrishnan; Richard Earnshaw; nickc@redhat.com\n> Subject: Re: [PATCH][GCC][ARM] Dot Product commandline options [Patch (1/8)]\n> \n> Hi Tamar,\n> \n> On 01/09/17 14:19, Tamar Christina wrote:\n>> Hi All,\n>>\n>> This patch adds support for the +dotprod extension to ARM.\n>> Dot Product requires Adv.SIMD to work and so enables this option\n>> by default when enabled.\n>>\n>> It is available from ARMv8.2-a and onwards and is enabled by\n>> default on Cortex-A55 and Cortex-A75.\n>>\n>> Regtested and bootstrapped on arm-none-eabi and no issues.\n> \n> I'm assuming you mean arm-none-linux-gnueabihf :)\n> \n>> Ok for trunk?\n>>\n>> gcc/\n>> 2017-09-01 Tamar Christina \n>>\n>> * config/arm/arm.h (TARGET_DOTPROD): New.\n>> * config/arm/arm.c (arm_arch_dotprod): New.\n>> (arm_option_reconfigure_globals): Add arm_arch_dotprod.\n>> * config/arm/arm-c.c (__ARM_FEATURE_DOTPROD): New.\n>> * config/arm/arm-cpus.in (cortex-a55, cortex-75): Enabled +dotprod.\n>> (armv8.2-a, cortex-a75.cortex-a55): Likewise.\n>> * config/arm/arm-isa.h (isa_bit_dotprod, ISA_DOTPROD): New.\n> \n> arm-isa.h is now autogenerated after r251799 so you'll need to rebase on\n> top of that.\n> That being said, that patch was temporarily reverted [1] so you'll have\n> to apply it manually in your\n> tree to rebase, or wait until it is reapplied.\n> \n> [1] https://gcc.gnu.org/ml/gcc-patches/2017-09/msg00579.html\n> \n> The patch looks ok to me otherwise with a documentation nit below.\n> \n>> * config/arm/t-multilib (v8_2_a_simd_variants): Add dotprod.\n>> * doc/invoke.texi (armv8.2-a): Document dotprod\n>>\n> \n> --- a/gcc/doc/invoke.texi\n> +++ b/gcc/doc/invoke.texi\n> @@ -15492,6 +15492,10 @@ The ARMv8.1 Advanced SIMD and floating-point instructions.\n> The cryptographic instructions. This also enables the Advanced SIMD and\n> floating-point instructions.\n> \n> +@item +dotprod\n> +Enable the Dot Product extension. This also enables Advanced SIMD instructions\n> +and allows auto vectorization of dot products to the Dot Product instructions.\n> \n> This should be \"auto-vectorization\"\n> \n> Thanks,\n> Kyrill\n> \n> \n> \n\n\nHmm, can you arrange to add patches as text/plain attachments, so that\nwhen I reply the patch is included for comments, please?\n\n+# double-precision FP. Make sure bits that are not an FPU bit go\ninstructions\n+# ALL_SIMD instead of ALL_SIMD_INTERNAL.\n\nTwo spaces after full stop. The new sentence doesn't make sense.\nInstead, I think you should probably put the following:\n\n\"ALL_FPU lists all the feature bits associated with the floating-point\nunit; these will all be removed if the floating-point unit is disabled\n(eg -mfloat-abi=soft). ALL_FPU_INTERNAL must ONLY contain features that\nform part of a named -mfpu option; it is used to map the capabilities\nback to a named FPU for the benefit of the assembler. ALL_SIMD_INTERNAL\nand ALL_SIMD are similarly defined to help with the construction of\nALL_FPU and ALL_FPU_INTERNAL; they describe the SIMD extensions that are\neither part of a named FPU or optional extensions respectively.\"\n\nYou might need to rejig the other sentence there as well to make it more\nconsistent.\n\n@@ -239,6 +243,7 @@ define fgroup FP_D32\tFP_DBL fp_d32\n define fgroup FP_ARMv8\tFPv5 FP_D32\n define fgroup NEON\tFP_D32 neon\n define fgroup CRYPTO\tNEON crypto\n+define fgroup DOTPROD NEON dotprod\n\nlines above have a hard tab between the group name and the features it\ncontains. Your entry has spaces. Please fix for consistency.\n\n@@ -1473,9 +1479,10 @@ begin cpu cortex-a55\n cname cortexa55\n tune for cortex-a53\n tune flags LDSCHED\n- architecture armv8.2-a+fp16\n+ architecture armv8.2-a+fp16+dotprod\n fpu neon-fp-armv8\n option crypto add FP_ARMv8 CRYPTO\n+ option dotprod add FP_ARMv8 DOTPROD\n\nWe don't have an option entry for +fp16 (all Cortex-a55 cores implement\nit), so we should treat dotprod similarly here. Crypto is a special\ncase because it isn't enabled by default. Similarly for the other cores\nlater in the patch.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list gcc-patches@gcc.gnu.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=gcc-patches-return-463664-incoming=patchwork.ozlabs.org@gcc.gnu.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org\n\theader.b=\"ldaLNE5e\"; dkim-atps=neutral","sourceware.org; auth=none"],"Received":["from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y7w2P2RTDz9t48\n\tfor ;\n\tSat, 7 Oct 2017 03:24:29 +1100 (AEDT)","(qmail 108784 invoked by alias); 6 Oct 2017 16:24:05 -0000","(qmail 108758 invoked by uid 89); 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a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender\n\t:subject:to:cc:references:from:message-id:date:mime-version\n\t:in-reply-to:content-type:content-transfer-encoding; s=default;\n\tbh=GT3d8tFFE1Mob1O+ApDWmb9nZnA=; b=ldaLNE5eFxME7Nk6R/PdR3VgXI4u\n\tr7/xgKyqQJd1u0O7dZITDF2l45iBJZVzFUWDAsSAv9mzgw/ZUhDvDTVEmCiCJrNd\n\tEjD16FKbKlC8m1j/LQkYHNrf5CEM2X19O6Y+dCrN5IYFHNHxVDldMhbI0UOXKp/B\n\th3SBpY3mK4NyDts=","Mailing-List":"contact gcc-patches-help@gcc.gnu.org; run by ezmlm","Precedence":"bulk","List-Id":"","List-Unsubscribe":"","List-Archive":"","List-Post":"","List-Help":"","Sender":"gcc-patches-owner@gcc.gnu.org","X-Virus-Found":"No","X-Spam-SWARE-Status":"No, score=-11.9 required=5.0 tests=BAYES_00, GIT_PATCH_2,\n\tGIT_PATCH_3, RP_MATCHES_RCVD,\n\tSPF_PASS autolearn=ham version=3.3.2 spammy=","X-HELO":"foss.arm.com","Subject":"Re: [PATCH][GCC][ARM] Dot Product commandline options [Patch (1/8)]","To":"Tamar Christina ,\n\tKyrill Tkachov ,\n\t\"gcc-patches@gcc.gnu.org\" ","Cc":"nd , Ramana Radhakrishnan ,\n\t\"nickc@redhat.com\" ","References":"<20170901131912.GA31822@arm.com> <59B90213.3020906@foss.arm.com>\n\t","From":"\"Richard Earnshaw (lists)\" ","Message-ID":"","Date":"Fri, 6 Oct 2017 17:23:53 +0100","User-Agent":"Mozilla/5.0 (X11; Linux x86_64;\n\trv:52.0) Gecko/20100101 Thunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"","Content-Type":"text/plain; charset=utf-8","Content-Transfer-Encoding":"7bit"}},{"id":1782670,"web_url":"http://patchwork.ozlabs.org/comment/1782670/","msgid":"<20171009095656.GA21312@arm.com>","list_archive_url":null,"date":"2017-10-09T09:56:56","subject":"Re: [PATCH][GCC][ARM] Dot Product commandline options [Patch (1/8)]","submitter":{"id":69689,"url":"http://patchwork.ozlabs.org/api/people/69689/","name":"Tamar Christina","email":"Tamar.Christina@arm.com"},"content":"Hi Richard,\n\nHere is a respin with the requested changes.\n\nOk for trunk?\n\nThanks,\nTamar\n\ngcc/\n2017-10-09 Tamar Christina \n\n\t* config/arm/arm.h (TARGET_DOTPROD): New.\n\t* config/arm/arm.c (arm_arch_dotprod): New.\n\t(arm_option_reconfigure_globals): Add arm_arch_dotprod.\n\t* config/arm/arm-c.c (__ARM_FEATURE_DOTPROD): New.\n\t* config/arm/arm-cpus.in (armv8.2-a): Enabled +dotprod.\n\t(feature dotprod, group dotprod, ALL_SIMD_INTERNAL): New.\n\t(ALL_FPU_INTERNAL): Use ALL_SIMD_INTERNAL.\n\t* config/arm/t-multilib (v8_2_a_simd_variants): Add dotprod.\n\t* doc/invoke.texi (armv8.2-a): Document dotprod\n\nThe 10/06/2017 17:23, Richard Earnshaw (lists) wrote:\n> On 06/10/17 13:44, Tamar Christina wrote:\n> > Hi All,\n> > \n> > This is a respin of the patch with the feedback processed.\n> > \n> > Regtested on arm-none-eabi, armeb-none-eabi,\n> > aarch64-none-elf and aarch64_be-none-elf with no issues found.\n> > \n> > Ok for trunk?\n> > \n> > gcc/\n> > 2017-10-06 Tamar Christina \n> > \n> > * config/arm/arm.h (TARGET_DOTPROD): New.\n> > * config/arm/arm.c (arm_arch_dotprod): New.\n> > (arm_option_reconfigure_globals): Add arm_arch_dotprod.\n> > * config/arm/arm-c.c (__ARM_FEATURE_DOTPROD): New.\n> > * config/arm/arm-cpus.in (cortex-a55, cortex-75): Enabled +dotprod.\n> > (armv8.2-a, cortex-a75.cortex-a55): Likewise.\n> > (feature dotprod, group dotprod, ALL_SIMD_INTERNAL): New.\n> > (ALL_FPU_INTERNAL): Use ALL_SIMD_INTERNAL.\n> > * config/arm/t-multilib (v8_2_a_simd_variants): Add dotprod.\n> > * doc/invoke.texi (armv8.2-a): Document dotprod\n> > ________________________________________\n> > From: Kyrill Tkachov \n> > Sent: Wednesday, September 13, 2017 11:01:55 AM\n> > To: Tamar Christina; gcc-patches@gcc.gnu.org\n> > Cc: nd; Ramana Radhakrishnan; Richard Earnshaw; nickc@redhat.com\n> > Subject: Re: [PATCH][GCC][ARM] Dot Product commandline options [Patch (1/8)]\n> > \n> > Hi Tamar,\n> > \n> > On 01/09/17 14:19, Tamar Christina wrote:\n> >> Hi All,\n> >>\n> >> This patch adds support for the +dotprod extension to ARM.\n> >> Dot Product requires Adv.SIMD to work and so enables this option\n> >> by default when enabled.\n> >>\n> >> It is available from ARMv8.2-a and onwards and is enabled by\n> >> default on Cortex-A55 and Cortex-A75.\n> >>\n> >> Regtested and bootstrapped on arm-none-eabi and no issues.\n> > \n> > I'm assuming you mean arm-none-linux-gnueabihf :)\n> > \n> >> Ok for trunk?\n> >>\n> >> gcc/\n> >> 2017-09-01 Tamar Christina \n> >>\n> >> * config/arm/arm.h (TARGET_DOTPROD): New.\n> >> * config/arm/arm.c (arm_arch_dotprod): New.\n> >> (arm_option_reconfigure_globals): Add arm_arch_dotprod.\n> >> * config/arm/arm-c.c (__ARM_FEATURE_DOTPROD): New.\n> >> * config/arm/arm-cpus.in (cortex-a55, cortex-75): Enabled +dotprod.\n> >> (armv8.2-a, cortex-a75.cortex-a55): Likewise.\n> >> * config/arm/arm-isa.h (isa_bit_dotprod, ISA_DOTPROD): New.\n> > \n> > arm-isa.h is now autogenerated after r251799 so you'll need to rebase on\n> > top of that.\n> > That being said, that patch was temporarily reverted [1] so you'll have\n> > to apply it manually in your\n> > tree to rebase, or wait until it is reapplied.\n> > \n> > [1] https://gcc.gnu.org/ml/gcc-patches/2017-09/msg00579.html\n> > \n> > The patch looks ok to me otherwise with a documentation nit below.\n> > \n> >> * config/arm/t-multilib (v8_2_a_simd_variants): Add dotprod.\n> >> * doc/invoke.texi (armv8.2-a): Document dotprod\n> >>\n> > \n> > --- a/gcc/doc/invoke.texi\n> > +++ b/gcc/doc/invoke.texi\n> > @@ -15492,6 +15492,10 @@ The ARMv8.1 Advanced SIMD and floating-point instructions.\n> > The cryptographic instructions. This also enables the Advanced SIMD and\n> > floating-point instructions.\n> > \n> > +@item +dotprod\n> > +Enable the Dot Product extension. This also enables Advanced SIMD instructions\n> > +and allows auto vectorization of dot products to the Dot Product instructions.\n> > \n> > This should be \"auto-vectorization\"\n> > \n> > Thanks,\n> > Kyrill\n> > \n> > \n> > \n> \n> \n> Hmm, can you arrange to add patches as text/plain attachments, so that\n> when I reply the patch is included for comments, please?\n> \n> +# double-precision FP. Make sure bits that are not an FPU bit go\n> instructions\n> +# ALL_SIMD instead of ALL_SIMD_INTERNAL.\n> \n> Two spaces after full stop. The new sentence doesn't make sense.\n> Instead, I think you should probably put the following:\n> \n> \"ALL_FPU lists all the feature bits associated with the floating-point\n> unit; these will all be removed if the floating-point unit is disabled\n> (eg -mfloat-abi=soft). ALL_FPU_INTERNAL must ONLY contain features that\n> form part of a named -mfpu option; it is used to map the capabilities\n> back to a named FPU for the benefit of the assembler. ALL_SIMD_INTERNAL\n> and ALL_SIMD are similarly defined to help with the construction of\n> ALL_FPU and ALL_FPU_INTERNAL; they describe the SIMD extensions that are\n> either part of a named FPU or optional extensions respectively.\"\n> \n> You might need to rejig the other sentence there as well to make it more\n> consistent.\n> \n> @@ -239,6 +243,7 @@ define fgroup FP_D32\tFP_DBL fp_d32\n> define fgroup FP_ARMv8\tFPv5 FP_D32\n> define fgroup NEON\tFP_D32 neon\n> define fgroup CRYPTO\tNEON crypto\n> +define fgroup DOTPROD NEON dotprod\n> \n> lines above have a hard tab between the group name and the features it\n> contains. Your entry has spaces. Please fix for consistency.\n> \n> @@ -1473,9 +1479,10 @@ begin cpu cortex-a55\n> cname cortexa55\n> tune for cortex-a53\n> tune flags LDSCHED\n> - architecture armv8.2-a+fp16\n> + architecture armv8.2-a+fp16+dotprod\n> fpu neon-fp-armv8\n> option crypto add FP_ARMv8 CRYPTO\n> + option dotprod add FP_ARMv8 DOTPROD\n> \n> We don't have an option entry for +fp16 (all Cortex-a55 cores implement\n> it), so we should treat dotprod similarly here. Crypto is a special\n> case because it isn't enabled by default. Similarly for the other cores\n> later in the patch.\n\n--\ndiff --git a/gcc/config/arm/arm-c.c b/gcc/config/arm/arm-c.c\nindex 55472434c3a6e90c5693bbaabd3265f7d968787f..295f03bf8ee02be7c89ed2967d283be206e9f25a 100644\n--- a/gcc/config/arm/arm-c.c\n+++ b/gcc/config/arm/arm-c.c\n@@ -73,6 +73,7 @@ arm_cpu_builtins (struct cpp_reader* pfile)\n def_or_undef_macro (pfile, \"__ARM_FEATURE_QRDMX\", TARGET_NEON_RDMA);\n \n def_or_undef_macro (pfile, \"__ARM_FEATURE_CRC32\", TARGET_CRC32);\n+ def_or_undef_macro (pfile, \"__ARM_FEATURE_DOTPROD\", TARGET_DOTPROD);\n def_or_undef_macro (pfile, \"__ARM_32BIT_STATE\", TARGET_32BIT);\n \n cpp_undef (pfile, \"__ARM_FEATURE_CMSE\");\ndiff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in\nindex 07de4c9375ba7a0df0d8bd00385e54a4042e5264..2da2a7d8e2b63d3d93ca73172b10ff23c1d8d8f9 100644\n--- a/gcc/config/arm/arm-cpus.in\n+++ b/gcc/config/arm/arm-cpus.in\n@@ -156,6 +156,8 @@ define feature crypto\n # FP16 data processing (half-precision float).\n define feature fp16\n \n+# Dot Product instructions extension to ARMv8.2-a.\n+define feature dotprod\n \n # ISA Quirks (errata?). Don't forget to add this to the fgroup\n # ALL_QUIRKS below.\n@@ -173,6 +175,17 @@ define feature quirk_cm3_ldrd\n define feature smallmul\n \n # Feature groups. Conventionally all (or mostly) upper case.\n+# ALL_FPU lists all the feature bits associated with the floating-point\n+# unit; these will all be removed if the floating-point unit is disabled\n+# (eg -mfloat-abi=soft). ALL_FPU_INTERNAL must ONLY contain features that\n+# form part of a named -mfpu option; it is used to map the capabilities\n+# back to a named FPU for the benefit of the assembler.\n+#\n+# ALL_SIMD_INTERNAL and ALL_SIMD are similarly defined to help with the\n+# construction of ALL_FPU and ALL_FPU_INTERNAL; they describe the SIMD\n+# extensions that are either part of a named FPU or optional extensions\n+# respectively.\n+\n \n # List of all cryptographic extensions to stripout if crypto is\n # disabled. Currently, that's trivial, but we define it anyway for\n@@ -182,11 +195,12 @@ define fgroup ALL_CRYPTO\tcrypto\n # List of all SIMD bits to strip out if SIMD is disabled. This does\n # strip off 32 D-registers, but does not remove support for\n # double-precision FP.\n-define fgroup ALL_SIMD\tfp_d32 neon ALL_CRYPTO\n+define fgroup ALL_SIMD_INTERNAL\tfp_d32 neon ALL_CRYPTO\n+define fgroup ALL_SIMD\tALL_SIMD_INTERNAL dotprod\n \n # List of all FPU bits to strip out if -mfpu is used to override the\n # default. fp16 is deliberately missing from this list.\n-define fgroup ALL_FPU_INTERNAL\tvfpv2 vfpv3 vfpv4 fpv5 fp16conv fp_dbl ALL_SIMD\n+define fgroup ALL_FPU_INTERNAL\tvfpv2 vfpv3 vfpv4 fpv5 fp16conv fp_dbl ALL_SIMD_INTERNAL\n \n # Similarly, but including fp16 and other extensions that aren't part of\n # -mfpu support.\n@@ -239,6 +253,7 @@ define fgroup FP_D32\tFP_DBL fp_d32\n define fgroup FP_ARMv8\tFPv5 FP_D32\n define fgroup NEON\tFP_D32 neon\n define fgroup CRYPTO\tNEON crypto\n+define fgroup DOTPROD\tNEON dotprod\n \n # List of all quirk bits to strip out when comparing CPU features with\n # architectures.\n@@ -561,6 +576,7 @@ begin arch armv8.2-a\n option crypto add FP_ARMv8 CRYPTO\n option nocrypto remove ALL_CRYPTO\n option nofp remove ALL_FP\n+ option dotprod add FP_ARMv8 DOTPROD\n end arch armv8.2-a\n \n begin arch armv8-m.base\n@@ -1473,7 +1489,7 @@ begin cpu cortex-a55\n cname cortexa55\n tune for cortex-a53\n tune flags LDSCHED\n- architecture armv8.2-a+fp16\n+ architecture armv8.2-a+fp16+dotprod\n fpu neon-fp-armv8\n option crypto add FP_ARMv8 CRYPTO\n option nofp remove ALL_FP\n@@ -1484,7 +1500,7 @@ begin cpu cortex-a75\n cname cortexa75\n tune for cortex-a57\n tune flags LDSCHED\n- architecture armv8.2-a+fp16\n+ architecture armv8.2-a+fp16+dotprod\n fpu neon-fp-armv8\n option crypto add FP_ARMv8 CRYPTO\n costs cortex_a73\n@@ -1496,7 +1512,7 @@ begin cpu cortex-a75.cortex-a55\n cname cortexa75cortexa55\n tune for cortex-a53\n tune flags LDSCHED\n- architecture armv8.2-a+fp16\n+ architecture armv8.2-a+fp16+dotprod\n fpu neon-fp-armv8\n option crypto add FP_ARMv8 CRYPTO\n costs cortex_a73\ndiff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h\nindex a3ca800f7a5cb876368480b97d0641f5d02af5d0..7e1eeb5254c2ce32ced2abdb43d1733ee1a45cd5 100644\n--- a/gcc/config/arm/arm.h\n+++ b/gcc/config/arm/arm.h\n@@ -210,6 +210,11 @@ extern tree arm_fp16_type_node;\n /* FPU supports ARMv8.1 Adv.SIMD extensions. */\n #define TARGET_NEON_RDMA (TARGET_NEON && arm_arch8_1)\n \n+/* Supports for Dot Product AdvSIMD extensions. */\n+#define TARGET_DOTPROD (TARGET_NEON\t\t\t\t\t\\\n+\t\t\t&& bitmap_bit_p (arm_active_target.isa,\t\t\\\n+\t\t\t\t\tisa_bit_dotprod))\n+\n /* FPU supports the floating point FP16 instructions for ARMv8.2 and later. */\n #define TARGET_VFP_FP16INST \\\n (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP5 && arm_fp16_inst)\ndiff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c\nindex 1943908bd840472bbab0a557d3e337c02b2ae26d..fb869d6441394d5caecbae9acebc19432ec788f2 100644\n--- a/gcc/config/arm/arm.c\n+++ b/gcc/config/arm/arm.c\n@@ -971,6 +971,9 @@ int arm_condexec_masklen = 0;\n /* Nonzero if chip supports the ARMv8 CRC instructions. */\n int arm_arch_crc = 0;\n \n+/* Nonzero if chip supports the AdvSIMD Dot Product instructions. */\n+int arm_arch_dotprod = 0;\n+\n /* Nonzero if chip supports the ARMv8-M security extensions. */\n int arm_arch_cmse = 0;\n \n@@ -3607,6 +3610,8 @@ arm_option_reconfigure_globals (void)\n arm_arch_cmse = bitmap_bit_p (arm_active_target.isa, isa_bit_cmse);\n arm_fp16_inst = bitmap_bit_p (arm_active_target.isa, isa_bit_fp16);\n arm_arch_lpae = bitmap_bit_p (arm_active_target.isa, isa_bit_lpae);\n+ arm_arch_dotprod = bitmap_bit_p (arm_active_target.isa, isa_bit_dotprod);\n+\n if (arm_fp16_inst)\n {\n if (arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE)\ndiff --git a/gcc/config/arm/t-multilib b/gcc/config/arm/t-multilib\nindex ec4b76dbc8fc56093c2b27c95e0947558496fe5a..47f3673160a766c5b1b8972f7670355f2c357b56 100644\n--- a/gcc/config/arm/t-multilib\n+++ b/gcc/config/arm/t-multilib\n@@ -68,7 +68,7 @@ v7ve_vfpv4_simd_variants := +simd\n v8_a_nosimd_variants\t:= +crc\n v8_a_simd_variants\t:= $(call all_feat_combs, simd crypto)\n v8_1_a_simd_variants\t:= $(call all_feat_combs, simd crypto)\n-v8_2_a_simd_variants\t:= $(call all_feat_combs, simd fp16 crypto)\n+v8_2_a_simd_variants\t:= $(call all_feat_combs, simd fp16 crypto dotprod)\n \n \n ifneq (,$(HAS_APROFILE))\ndiff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi\nindex f862b7f8c99e7e9cca200fbe5b7d969748fed3f9..a69b0d59cdfecf82b97c8fad0de35fe7ac939e19 100644\n--- a/gcc/doc/invoke.texi\n+++ b/gcc/doc/invoke.texi\n@@ -15597,6 +15597,9 @@ The ARMv8.1 Advanced SIMD and floating-point instructions.\n The cryptographic instructions. This also enables the Advanced SIMD and\n floating-point instructions.\n \n+@item +dotprod\n+Enable the Dot Product extension. This also enables Advanced SIMD instructions.\n+\n @item +nocrypto\n Disable the cryptographic extension.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list gcc-patches@gcc.gnu.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=gcc-patches-return-463735-incoming=patchwork.ozlabs.org@gcc.gnu.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org\n\theader.b=\"Zpsd/rBy\"; dkim-atps=neutral","sourceware.org; auth=none","spf=none (sender IP is )\n\tsmtp.mailfrom=Tamar.Christina@arm.com; "],"Received":["from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y9bJ74T1Gz9tY0\n\tfor ;\n\tMon, 9 Oct 2017 20:57:08 +1100 (AEDT)","(qmail 84167 invoked by alias); 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SFP:1101; SCL:1; SRVR:HE1PR0802MB2313; H:arm.com;\n\tFPR:; SPF:None; PTR:InfoNoRecords; MX:1; A:1; LANG:en; ","Received-SPF":"None (protection.outlook.com: arm.com does not designate\n\tpermitted sender hosts)","SpamDiagnosticOutput":"1:99","SpamDiagnosticMetadata":"NSPM","X-OriginatorOrg":"arm.com","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"09 Oct 2017 09:56:50.7375\n\t(UTC)","X-MS-Exchange-CrossTenant-FromEntityHeader":"Hosted","X-MS-Exchange-CrossTenant-Id":"f34e5979-57d9-4aaa-ad4d-b122a662184d","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"HE1PR0802MB2313","X-IsSubscribed":"yes"}},{"id":1782673,"web_url":"http://patchwork.ozlabs.org/comment/1782673/","msgid":"","list_archive_url":null,"date":"2017-10-09T10:00:45","subject":"Re: [PATCH][GCC][ARM] Dot Product commandline options [Patch (1/8)]","submitter":{"id":67887,"url":"http://patchwork.ozlabs.org/api/people/67887/","name":"Richard Earnshaw","email":"Richard.Earnshaw@arm.com"},"content":"On 09/10/17 10:56, Tamar Christina wrote:\n> Hi Richard,\n> \n> Here is a respin with the requested changes.\n> \n> Ok for trunk?\n> \n> Thanks,\n> Tamar\n> \n> gcc/\n> 2017-10-09 Tamar Christina \n> \n> \t* config/arm/arm.h (TARGET_DOTPROD): New.\n> \t* config/arm/arm.c (arm_arch_dotprod): New.\n> \t(arm_option_reconfigure_globals): Add arm_arch_dotprod.\n> \t* config/arm/arm-c.c (__ARM_FEATURE_DOTPROD): New.\n> \t* config/arm/arm-cpus.in (armv8.2-a): Enabled +dotprod.\n> \t(feature dotprod, group dotprod, ALL_SIMD_INTERNAL): New.\n> \t(ALL_FPU_INTERNAL): Use ALL_SIMD_INTERNAL.\n> \t* config/arm/t-multilib (v8_2_a_simd_variants): Add dotprod.\n> \t* doc/invoke.texi (armv8.2-a): Document dotprod\n> \n\nOK.\n\nR.\n\n> The 10/06/2017 17:23, Richard Earnshaw (lists) wrote:\n>> On 06/10/17 13:44, Tamar Christina wrote:\n>>> Hi All,\n>>>\n>>> This is a respin of the patch with the feedback processed.\n>>>\n>>> Regtested on arm-none-eabi, armeb-none-eabi,\n>>> aarch64-none-elf and aarch64_be-none-elf with no issues found.\n>>>\n>>> Ok for trunk?\n>>>\n>>> gcc/\n>>> 2017-10-06 Tamar Christina \n>>>\n>>> * config/arm/arm.h (TARGET_DOTPROD): New.\n>>> * config/arm/arm.c (arm_arch_dotprod): New.\n>>> (arm_option_reconfigure_globals): Add arm_arch_dotprod.\n>>> * config/arm/arm-c.c (__ARM_FEATURE_DOTPROD): New.\n>>> * config/arm/arm-cpus.in (cortex-a55, cortex-75): Enabled +dotprod.\n>>> (armv8.2-a, cortex-a75.cortex-a55): Likewise.\n>>> (feature dotprod, group dotprod, ALL_SIMD_INTERNAL): New.\n>>> (ALL_FPU_INTERNAL): Use ALL_SIMD_INTERNAL.\n>>> * config/arm/t-multilib (v8_2_a_simd_variants): Add dotprod.\n>>> * doc/invoke.texi (armv8.2-a): Document dotprod\n>>> ________________________________________\n>>> From: Kyrill Tkachov \n>>> Sent: Wednesday, September 13, 2017 11:01:55 AM\n>>> To: Tamar Christina; gcc-patches@gcc.gnu.org\n>>> Cc: nd; Ramana Radhakrishnan; Richard Earnshaw; nickc@redhat.com\n>>> Subject: Re: [PATCH][GCC][ARM] Dot Product commandline options [Patch (1/8)]\n>>>\n>>> Hi Tamar,\n>>>\n>>> On 01/09/17 14:19, Tamar Christina wrote:\n>>>> Hi All,\n>>>>\n>>>> This patch adds support for the +dotprod extension to ARM.\n>>>> Dot Product requires Adv.SIMD to work and so enables this option\n>>>> by default when enabled.\n>>>>\n>>>> It is available from ARMv8.2-a and onwards and is enabled by\n>>>> default on Cortex-A55 and Cortex-A75.\n>>>>\n>>>> Regtested and bootstrapped on arm-none-eabi and no issues.\n>>>\n>>> I'm assuming you mean arm-none-linux-gnueabihf :)\n>>>\n>>>> Ok for trunk?\n>>>>\n>>>> gcc/\n>>>> 2017-09-01 Tamar Christina \n>>>>\n>>>> * config/arm/arm.h (TARGET_DOTPROD): New.\n>>>> * config/arm/arm.c (arm_arch_dotprod): New.\n>>>> (arm_option_reconfigure_globals): Add arm_arch_dotprod.\n>>>> * config/arm/arm-c.c (__ARM_FEATURE_DOTPROD): New.\n>>>> * config/arm/arm-cpus.in (cortex-a55, cortex-75): Enabled +dotprod.\n>>>> (armv8.2-a, cortex-a75.cortex-a55): Likewise.\n>>>> * config/arm/arm-isa.h (isa_bit_dotprod, ISA_DOTPROD): New.\n>>>\n>>> arm-isa.h is now autogenerated after r251799 so you'll need to rebase on\n>>> top of that.\n>>> That being said, that patch was temporarily reverted [1] so you'll have\n>>> to apply it manually in your\n>>> tree to rebase, or wait until it is reapplied.\n>>>\n>>> [1] https://gcc.gnu.org/ml/gcc-patches/2017-09/msg00579.html\n>>>\n>>> The patch looks ok to me otherwise with a documentation nit below.\n>>>\n>>>> * config/arm/t-multilib (v8_2_a_simd_variants): Add dotprod.\n>>>> * doc/invoke.texi (armv8.2-a): Document dotprod\n>>>>\n>>>\n>>> --- a/gcc/doc/invoke.texi\n>>> +++ b/gcc/doc/invoke.texi\n>>> @@ -15492,6 +15492,10 @@ The ARMv8.1 Advanced SIMD and floating-point instructions.\n>>> The cryptographic instructions. This also enables the Advanced SIMD and\n>>> floating-point instructions.\n>>>\n>>> +@item +dotprod\n>>> +Enable the Dot Product extension. This also enables Advanced SIMD instructions\n>>> +and allows auto vectorization of dot products to the Dot Product instructions.\n>>>\n>>> This should be \"auto-vectorization\"\n>>>\n>>> Thanks,\n>>> Kyrill\n>>>\n>>>\n>>>\n>>\n>>\n>> Hmm, can you arrange to add patches as text/plain attachments, so that\n>> when I reply the patch is included for comments, please?\n>>\n>> +# double-precision FP. Make sure bits that are not an FPU bit go\n>> instructions\n>> +# ALL_SIMD instead of ALL_SIMD_INTERNAL.\n>>\n>> Two spaces after full stop. The new sentence doesn't make sense.\n>> Instead, I think you should probably put the following:\n>>\n>> \"ALL_FPU lists all the feature bits associated with the floating-point\n>> unit; these will all be removed if the floating-point unit is disabled\n>> (eg -mfloat-abi=soft). ALL_FPU_INTERNAL must ONLY contain features that\n>> form part of a named -mfpu option; it is used to map the capabilities\n>> back to a named FPU for the benefit of the assembler. ALL_SIMD_INTERNAL\n>> and ALL_SIMD are similarly defined to help with the construction of\n>> ALL_FPU and ALL_FPU_INTERNAL; they describe the SIMD extensions that are\n>> either part of a named FPU or optional extensions respectively.\"\n>>\n>> You might need to rejig the other sentence there as well to make it more\n>> consistent.\n>>\n>> @@ -239,6 +243,7 @@ define fgroup FP_D32\tFP_DBL fp_d32\n>> define fgroup FP_ARMv8\tFPv5 FP_D32\n>> define fgroup NEON\tFP_D32 neon\n>> define fgroup CRYPTO\tNEON crypto\n>> +define fgroup DOTPROD NEON dotprod\n>>\n>> lines above have a hard tab between the group name and the features it\n>> contains. Your entry has spaces. Please fix for consistency.\n>>\n>> @@ -1473,9 +1479,10 @@ begin cpu cortex-a55\n>> cname cortexa55\n>> tune for cortex-a53\n>> tune flags LDSCHED\n>> - architecture armv8.2-a+fp16\n>> + architecture armv8.2-a+fp16+dotprod\n>> fpu neon-fp-armv8\n>> option crypto add FP_ARMv8 CRYPTO\n>> + option dotprod add FP_ARMv8 DOTPROD\n>>\n>> We don't have an option entry for +fp16 (all Cortex-a55 cores implement\n>> it), so we should treat dotprod similarly here. Crypto is a special\n>> case because it isn't enabled by default. Similarly for the other cores\n>> later in the patch.\n> \n> \n> 7949-diff.patch\n> \n> \n> diff --git a/gcc/config/arm/arm-c.c b/gcc/config/arm/arm-c.c\n> index 55472434c3a6e90c5693bbaabd3265f7d968787f..295f03bf8ee02be7c89ed2967d283be206e9f25a 100644\n> --- a/gcc/config/arm/arm-c.c\n> +++ b/gcc/config/arm/arm-c.c\n> @@ -73,6 +73,7 @@ arm_cpu_builtins (struct cpp_reader* pfile)\n> def_or_undef_macro (pfile, \"__ARM_FEATURE_QRDMX\", TARGET_NEON_RDMA);\n> \n> def_or_undef_macro (pfile, \"__ARM_FEATURE_CRC32\", TARGET_CRC32);\n> + def_or_undef_macro (pfile, \"__ARM_FEATURE_DOTPROD\", TARGET_DOTPROD);\n> def_or_undef_macro (pfile, \"__ARM_32BIT_STATE\", TARGET_32BIT);\n> \n> cpp_undef (pfile, \"__ARM_FEATURE_CMSE\");\n> diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in\n> index 07de4c9375ba7a0df0d8bd00385e54a4042e5264..2da2a7d8e2b63d3d93ca73172b10ff23c1d8d8f9 100644\n> --- a/gcc/config/arm/arm-cpus.in\n> +++ b/gcc/config/arm/arm-cpus.in\n> @@ -156,6 +156,8 @@ define feature crypto\n> # FP16 data processing (half-precision float).\n> define feature fp16\n> \n> +# Dot Product instructions extension to ARMv8.2-a.\n> +define feature dotprod\n> \n> # ISA Quirks (errata?). Don't forget to add this to the fgroup\n> # ALL_QUIRKS below.\n> @@ -173,6 +175,17 @@ define feature quirk_cm3_ldrd\n> define feature smallmul\n> \n> # Feature groups. Conventionally all (or mostly) upper case.\n> +# ALL_FPU lists all the feature bits associated with the floating-point\n> +# unit; these will all be removed if the floating-point unit is disabled\n> +# (eg -mfloat-abi=soft). ALL_FPU_INTERNAL must ONLY contain features that\n> +# form part of a named -mfpu option; it is used to map the capabilities\n> +# back to a named FPU for the benefit of the assembler.\n> +#\n> +# ALL_SIMD_INTERNAL and ALL_SIMD are similarly defined to help with the\n> +# construction of ALL_FPU and ALL_FPU_INTERNAL; they describe the SIMD\n> +# extensions that are either part of a named FPU or optional extensions\n> +# respectively.\n> +\n> \n> # List of all cryptographic extensions to stripout if crypto is\n> # disabled. Currently, that's trivial, but we define it anyway for\n> @@ -182,11 +195,12 @@ define fgroup ALL_CRYPTO\tcrypto\n> # List of all SIMD bits to strip out if SIMD is disabled. This does\n> # strip off 32 D-registers, but does not remove support for\n> # double-precision FP.\n> -define fgroup ALL_SIMD\tfp_d32 neon ALL_CRYPTO\n> +define fgroup ALL_SIMD_INTERNAL\tfp_d32 neon ALL_CRYPTO\n> +define fgroup ALL_SIMD\tALL_SIMD_INTERNAL dotprod\n> \n> # List of all FPU bits to strip out if -mfpu is used to override the\n> # default. fp16 is deliberately missing from this list.\n> -define fgroup ALL_FPU_INTERNAL\tvfpv2 vfpv3 vfpv4 fpv5 fp16conv fp_dbl ALL_SIMD\n> +define fgroup ALL_FPU_INTERNAL\tvfpv2 vfpv3 vfpv4 fpv5 fp16conv fp_dbl ALL_SIMD_INTERNAL\n> \n> # Similarly, but including fp16 and other extensions that aren't part of\n> # -mfpu support.\n> @@ -239,6 +253,7 @@ define fgroup FP_D32\tFP_DBL fp_d32\n> define fgroup FP_ARMv8\tFPv5 FP_D32\n> define fgroup NEON\tFP_D32 neon\n> define fgroup CRYPTO\tNEON crypto\n> +define fgroup DOTPROD\tNEON dotprod\n> \n> # List of all quirk bits to strip out when comparing CPU features with\n> # architectures.\n> @@ -561,6 +576,7 @@ begin arch armv8.2-a\n> option crypto add FP_ARMv8 CRYPTO\n> option nocrypto remove ALL_CRYPTO\n> option nofp remove ALL_FP\n> + option dotprod add FP_ARMv8 DOTPROD\n> end arch armv8.2-a\n> \n> begin arch armv8-m.base\n> @@ -1473,7 +1489,7 @@ begin cpu cortex-a55\n> cname cortexa55\n> tune for cortex-a53\n> tune flags LDSCHED\n> - architecture armv8.2-a+fp16\n> + architecture armv8.2-a+fp16+dotprod\n> fpu neon-fp-armv8\n> option crypto add FP_ARMv8 CRYPTO\n> option nofp remove ALL_FP\n> @@ -1484,7 +1500,7 @@ begin cpu cortex-a75\n> cname cortexa75\n> tune for cortex-a57\n> tune flags LDSCHED\n> - architecture armv8.2-a+fp16\n> + architecture armv8.2-a+fp16+dotprod\n> fpu neon-fp-armv8\n> option crypto add FP_ARMv8 CRYPTO\n> costs cortex_a73\n> @@ -1496,7 +1512,7 @@ begin cpu cortex-a75.cortex-a55\n> cname cortexa75cortexa55\n> tune for cortex-a53\n> tune flags LDSCHED\n> - architecture armv8.2-a+fp16\n> + architecture armv8.2-a+fp16+dotprod\n> fpu neon-fp-armv8\n> option crypto add FP_ARMv8 CRYPTO\n> costs cortex_a73\n> diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h\n> index a3ca800f7a5cb876368480b97d0641f5d02af5d0..7e1eeb5254c2ce32ced2abdb43d1733ee1a45cd5 100644\n> --- a/gcc/config/arm/arm.h\n> +++ b/gcc/config/arm/arm.h\n> @@ -210,6 +210,11 @@ extern tree arm_fp16_type_node;\n> /* FPU supports ARMv8.1 Adv.SIMD extensions. */\n> #define TARGET_NEON_RDMA (TARGET_NEON && arm_arch8_1)\n> \n> +/* Supports for Dot Product AdvSIMD extensions. */\n> +#define TARGET_DOTPROD (TARGET_NEON\t\t\t\t\t\\\n> +\t\t\t&& bitmap_bit_p (arm_active_target.isa,\t\t\\\n> +\t\t\t\t\tisa_bit_dotprod))\n> +\n> /* FPU supports the floating point FP16 instructions for ARMv8.2 and later. */\n> #define TARGET_VFP_FP16INST \\\n> (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP5 && arm_fp16_inst)\n> diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c\n> index 1943908bd840472bbab0a557d3e337c02b2ae26d..fb869d6441394d5caecbae9acebc19432ec788f2 100644\n> --- a/gcc/config/arm/arm.c\n> +++ b/gcc/config/arm/arm.c\n> @@ -971,6 +971,9 @@ int arm_condexec_masklen = 0;\n> /* Nonzero if chip supports the ARMv8 CRC instructions. */\n> int arm_arch_crc = 0;\n> \n> +/* Nonzero if chip supports the AdvSIMD Dot Product instructions. */\n> +int arm_arch_dotprod = 0;\n> +\n> /* Nonzero if chip supports the ARMv8-M security extensions. */\n> int arm_arch_cmse = 0;\n> \n> @@ -3607,6 +3610,8 @@ arm_option_reconfigure_globals (void)\n> arm_arch_cmse = bitmap_bit_p (arm_active_target.isa, isa_bit_cmse);\n> arm_fp16_inst = bitmap_bit_p (arm_active_target.isa, isa_bit_fp16);\n> arm_arch_lpae = bitmap_bit_p (arm_active_target.isa, isa_bit_lpae);\n> + arm_arch_dotprod = bitmap_bit_p (arm_active_target.isa, isa_bit_dotprod);\n> +\n> if (arm_fp16_inst)\n> {\n> if (arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE)\n> diff --git a/gcc/config/arm/t-multilib b/gcc/config/arm/t-multilib\n> index ec4b76dbc8fc56093c2b27c95e0947558496fe5a..47f3673160a766c5b1b8972f7670355f2c357b56 100644\n> --- a/gcc/config/arm/t-multilib\n> +++ b/gcc/config/arm/t-multilib\n> @@ -68,7 +68,7 @@ v7ve_vfpv4_simd_variants := +simd\n> v8_a_nosimd_variants\t:= +crc\n> v8_a_simd_variants\t:= $(call all_feat_combs, simd crypto)\n> v8_1_a_simd_variants\t:= $(call all_feat_combs, simd crypto)\n> -v8_2_a_simd_variants\t:= $(call all_feat_combs, simd fp16 crypto)\n> +v8_2_a_simd_variants\t:= $(call all_feat_combs, simd fp16 crypto dotprod)\n> \n> \n> ifneq (,$(HAS_APROFILE))\n> diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi\n> index f862b7f8c99e7e9cca200fbe5b7d969748fed3f9..a69b0d59cdfecf82b97c8fad0de35fe7ac939e19 100644\n> --- a/gcc/doc/invoke.texi\n> +++ b/gcc/doc/invoke.texi\n> @@ -15597,6 +15597,9 @@ The ARMv8.1 Advanced SIMD and floating-point instructions.\n> The cryptographic instructions. This also enables the Advanced SIMD and\n> floating-point instructions.\n> \n> +@item +dotprod\n> +Enable the Dot Product extension. This also enables Advanced SIMD instructions.\n> +\n> @item +nocrypto\n> Disable the cryptographic extension.\n> \n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list gcc-patches@gcc.gnu.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=gcc-patches-return-463736-incoming=patchwork.ozlabs.org@gcc.gnu.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org\n\theader.b=\"ZdtqGV0T\"; dkim-atps=neutral","sourceware.org; auth=none"],"Received":["from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y9bNw2CgZz9tY0\n\tfor ;\n\tMon, 9 Oct 2017 21:01:20 +1100 (AEDT)","(qmail 88454 invoked by alias); 9 Oct 2017 10:01:12 -0000","(qmail 88407 invoked by uid 89); 9 Oct 2017 10:01:08 -0000","from usa-sjc-mx-foss1.foss.arm.com (HELO foss.arm.com)\n\t(217.140.101.70) by sourceware.org\n\t(qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP;\n\tMon, 09 Oct 2017 10:00:58 +0000","from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249])\tby\n\tusa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id\n\t8AC9C1435; Mon, 9 Oct 2017 03:00:56 -0700 (PDT)","from e105689-lin.cambridge.arm.com (e105689-lin.cambridge.arm.com\n\t[10.2.207.32])\tby usa-sjc-imap-foss1.foss.arm.com (Postfix)\n\twith ESMTPSA id F15EF3F578; Mon, 9 Oct 2017 03:00:54 -0700 (PDT)"],"DomainKey-Signature":"a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender\n\t:subject:to:cc:references:from:message-id:date:mime-version\n\t:in-reply-to:content-type:content-transfer-encoding; q=dns; s=\n\tdefault; b=uC2yrt6P3nKlKRs2XPsDmk+M9YBx3slGxDKJegFggQ0nzVt6lHOyH\n\tdKX7CH/YbAOFR9e7hGRqNN8aFJ5tT/DWIwhnj3xOOeEICvRg87bgTRZAuYcsAqZ6\n\t0sjCN91YBz/b4jBUc4KpeNhSXAVu7zVKaW9vihC5eatO6+d0nL/Guc=","DKIM-Signature":"v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender\n\t:subject:to:cc:references:from:message-id:date:mime-version\n\t:in-reply-to:content-type:content-transfer-encoding; s=default;\n\tbh=YpUWqdrVz3DfYQwTo+m7JPgOMRU=; b=ZdtqGV0TGKxQfDfqiOn8htpTecmY\n\tYcwkPSSEZIml3daQgEkO/qrAuC5c6uW7dv/af+prfc/e+h9Todwi3VmOAJwHm1iF\n\t0Dyk+AmP+cMxcT9eCOvGfWP/KLekHECZvbNzzID7rj1TZhiJCxaJcp+1nledeDtd\n\tYEVgPYlMU0F2aOs=","Mailing-List":"contact gcc-patches-help@gcc.gnu.org; run by ezmlm","Precedence":"bulk","List-Id":"","List-Unsubscribe":"","List-Archive":"","List-Post":"","List-Help":"","Sender":"gcc-patches-owner@gcc.gnu.org","X-Virus-Found":"No","X-Spam-SWARE-Status":"No, score=-26.7 required=5.0 tests=BAYES_00, GIT_PATCH_0,\n\tGIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_LOTSOFHASH,\n\tRP_MATCHES_RCVD, SPF_PASS autolearn=ham version=3.3.2 spammy=","X-HELO":"foss.arm.com","Subject":"Re: [PATCH][GCC][ARM] Dot Product commandline options [Patch (1/8)]","To":"Tamar Christina ","Cc":"Kyrill Tkachov ,\n\t\"gcc-patches@gcc.gnu.org\" , nd ,\n\tRamana Radhakrishnan ,\n\t\"nickc@redhat.com\" ","References":"<20170901131912.GA31822@arm.com> <59B90213.3020906@foss.arm.com>\n\t\n\t\n\t<20171009095656.GA21312@arm.com>","From":"\"Richard Earnshaw (lists)\" ","Message-ID":"","Date":"Mon, 9 Oct 2017 11:00:45 +0100","User-Agent":"Mozilla/5.0 (X11; Linux x86_64;\n\trv:52.0) Gecko/20100101 Thunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"<20171009095656.GA21312@arm.com>","Content-Type":"text/plain; charset=us-ascii","Content-Transfer-Encoding":"7bit"}}]