[{"id":1762891,"web_url":"http://patchwork.ozlabs.org/comment/1762891/","msgid":"","list_archive_url":null,"date":"2017-09-04T14:24:44","subject":"Re: [PATCH v2 2/3] arm: dts: add Nuvoton NPCM750 device tree","submitter":{"id":72291,"url":"http://patchwork.ozlabs.org/api/people/72291/","name":"Tomer Maimon","email":"tmaimon77@gmail.com"},"content":"On 1 September 2017 at 01:53, Brendan Higgins wrote:\n> Add a common device tree for all Nuvoton NPCM750 BMCs and a board\n> specific device tree for the NPCM750 (Poleg) evaluation board.\n>\n> Signed-off-by: Brendan Higgins \n> ---\n> .../arm/cpu-enable-method/nuvoton,npcm7xx-smp | 42 +++++\n> .../devicetree/bindings/arm/npcm/npcm.txt | 6 +\n> arch/arm/boot/dts/nuvoton-npcm750-evb.dts | 59 +++++++\n> arch/arm/boot/dts/nuvoton-npcm750.dtsi | 177 +++++++++++++++++++++\n> include/dt-bindings/clock/nuvoton,npcm7xx-clks.h | 39 +++++\n> 5 files changed, 323 insertions(+)\n> create mode 100644 Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm7xx-smp\n> create mode 100644 Documentation/devicetree/bindings/arm/npcm/npcm.txt\n> create mode 100644 arch/arm/boot/dts/nuvoton-npcm750-evb.dts\n> create mode 100644 arch/arm/boot/dts/nuvoton-npcm750.dtsi\n> create mode 100644 include/dt-bindings/clock/nuvoton,npcm7xx-clks.h\n>\n> diff --git a/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm7xx-smp b/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm7xx-smp\n> new file mode 100644\n> index 000000000000..e81f85b400cf\n> --- /dev/null\n> +++ b/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm7xx-smp\n> @@ -0,0 +1,42 @@\n> +=========================================================\n> +Secondary CPU enable-method \"nuvoton,npcm7xx-smp\" binding\n> +=========================================================\n> +\n> +To apply to all CPUs, a single \"nuvoton,npcm7xx-smp\" enable method should be\n> +defined in the \"cpus\" node.\n> +\n> +Enable method name: \"nuvoton,npcm7xx-smp\"\n> +Compatible machines: \"nuvoton,npcm750\"\n> +Compatible CPUs: \"arm,cortex-a9\"\n> +Related properties: (none)\n> +\n> +Note:\n> +This enable method needs valid nodes compatible with \"arm,cortex-a9-scu\" and\n> +\"nuvoton,npcm750-gcr\".\n> +\n> +Example:\n> +\n> + cpus {\n> + #address-cells = <1>;\n> + #size-cells = <0>;\n> + enable-method = \"nuvoton,npcm7xx-smp\";\n> +\n> + cpu@0 {\n> + device_type = \"cpu\";\n> + compatible = \"arm,cortex-a9\";\n> + clocks = <&clk NPCM7XX_CLK_CPU>;\n> + clock-names = \"clk_cpu\";\n> + reg = <0>;\n> + next-level-cache = <&L2>;\n> + };\n> +\n> + cpu@1 {\n> + device_type = \"cpu\";\n> + compatible = \"arm,cortex-a9\";\n> + clocks = <&clk NPCM7XX_CLK_CPU>;\n> + clock-names = \"clk_cpu\";\n> + reg = <1>;\n> + next-level-cache = <&L2>;\n> + };\n> + };\n> +\n> diff --git a/Documentation/devicetree/bindings/arm/npcm/npcm.txt b/Documentation/devicetree/bindings/arm/npcm/npcm.txt\n> new file mode 100644\n> index 000000000000..2d87d9ecea85\n> --- /dev/null\n> +++ b/Documentation/devicetree/bindings/arm/npcm/npcm.txt\n> @@ -0,0 +1,6 @@\n> +NPCM Platforms Device Tree Bindings\n> +-----------------------------------\n> +NPCM750 SoC\n> +Required root node properties:\n> + - compatible = \"nuvoton,npcm750\";\n> +\n> diff --git a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts\n> new file mode 100644\n> index 000000000000..54df32cff21b\n> --- /dev/null\n> +++ b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts\n> @@ -0,0 +1,59 @@\n> +/*\n> + * DTS file for all NPCM750 SoCs\n> + *\n> + * Copyright 2012 Tomer Maimon \n> + *\n> + * The code contained herein is licensed under the GNU General Public\n> + * License. You may obtain a copy of the GNU General Public License\n> + * Version 2 or later at the following locations:\n> + *\n> + * http://www.opensource.org/licenses/gpl-license.html\n> + * http://www.gnu.org/copyleft/gpl.html\n> + */\n> +\n> +/dts-v1/;\n> +#include \"nuvoton-npcm750.dtsi\"\n> +\n> +/ {\n> + model = \"Nuvoton npcm750 Development Board (Device Tree)\";\n> + compatible = \"nuvoton,npcm750\";\n> +\n> + chosen {\n> + stdout-path = &serial3;\n> + bootargs = \"earlyprintk=serial,serial3,115200\";\n> + };\n> +\n> + memory {\n> + reg = <0 0x40000000>;\n> + };\n> +\n> + cpus {\n> + enable-method = \"nuvoton,npcm7xx-smp\";\n> + };\n> +\n> + clk: clock-controller@f0801000 {\n> + status = \"okay\";\n> + };\n> +\n> + apb {\n> + watchdog1: watchdog@f0009000 {\n> + status = \"okay\";\n> + };\n> +\n> + serial0: serial0@f0001000 {\n> + status = \"okay\";\n> + };\n> +\n> + serial1: serial1@f0002000 {\n> + status = \"okay\";\n> + };\n> +\n> + serial2: serial2@f0003000 {\n> + status = \"okay\";\n> + };\n> +\n> + serial3: serial3@f0004000 {\n> + status = \"okay\";\n> + };\n> + };\n> +};\n> diff --git a/arch/arm/boot/dts/nuvoton-npcm750.dtsi b/arch/arm/boot/dts/nuvoton-npcm750.dtsi\n> new file mode 100644\n> index 000000000000..bca96b3ae9d3\n> --- /dev/null\n> +++ b/arch/arm/boot/dts/nuvoton-npcm750.dtsi\n> @@ -0,0 +1,177 @@\n> +/*\n> + * DTSi file for the NPCM750 SoC\n> + *\n> + * Copyright 2012 Tomer Maimon \n> + *\n> + * The code contained herein is licensed under the GNU General Public\n> + * License. You may obtain a copy of the GNU General Public License\n> + * Version 2 or later at the following locations:\n> + *\n> + * http://www.opensource.org/licenses/gpl-license.html\n> + * http://www.gnu.org/copyleft/gpl.html\n> + */\n> +\n> +#include \"skeleton.dtsi\"\n> +#include \n> +#include \n> +\n> +/ {\n> + #address-cells = <1>;\n> + #size-cells = <1>;\n> + interrupt-parent = <&gic>;\n> +\n> + cpus {\n> + #address-cells = <1>;\n> + #size-cells = <0>;\n> +\n> + cpu@0 {\n> + device_type = \"cpu\";\n> + compatible = \"arm,cortex-a9\";\n> + clocks = <&clk NPCM7XX_CLK_CPU>;\n> + clock-names = \"clk_cpu\";\n> + reg = <0>;\n> + next-level-cache = <&l2>;\n> + };\n> +\n> + cpu@1 {\n> + device_type = \"cpu\";\n> + compatible = \"arm,cortex-a9\";\n> + clocks = <&clk NPCM7XX_CLK_CPU>;\n> + clock-names = \"clk_cpu\";\n> + reg = <1>;\n> + next-level-cache = <&l2>;\n> + };\n> + };\n> +\n> + gcr: gcr@f0800000 {\n> + compatible = \"nuvoton,npcm750-gcr\", \"syscon\",\n> + \"simple-mfd\";\n> + reg = <0xf0800000 0x1000>;\n> + };\n> +\n> + scu: scu@f03fe000 {\n> + compatible = \"arm,cortex-a9-scu\";\n> + reg = <0xf03fe000 0x1000>;\n> + };\n> +\n> + l2: l2-cache@f03fc000 {\n> + compatible = \"arm,pl310-cache\";\n> + reg = <0xf03fc000 0x1000>;\n> + interrupts = <0 21 4>;\n> + cache-unified;\n> + cache-level = <2>;\n> + clocks = <&clk NPCM7XX_CLK_AXI>;\n> + };\n> +\n> + gic: interrupt-controller@f03ff000 {\n> + compatible = \"arm,cortex-a9-gic\";\n> + interrupt-controller;\n> + #interrupt-cells = <3>;\n> + reg = <0xf03ff000 0x1000>,\n> + <0xf03fe100 0x100>;\n> + };\n> +\n> + clk: clock-controller@f0801000 {\n> + compatible = \"nuvoton,npcm750-clk\";\n> + #clock-cells = <1>;\n> + reg = <0xf0801000 0x1000>;\n> + };\n> +\n> + /* external clock signal rg1refck, supplied by the phy */\n> + clk-rg1refck {\n> + compatible = \"fixed-clock\";\n> + #clock-cells = <0>;\n> + clock-frequency = <125000000>;\n> + };\n> +\n> + /* external clock signal rg2refck, supplied by the phy */\n> + clk-rg2refck {\n> + compatible = \"fixed-clock\";\n> + #clock-cells = <0>;\n> + clock-frequency = <125000000>;\n> + };\n> +\n> + clk-xin {\n> + compatible = \"fixed-clock\";\n> + #clock-cells = <0>;\n> + clock-frequency = <50000000>;\n> + };\n> +\n> + timer@f03fe600 {\n> + compatible = \"arm,cortex-a9-twd-timer\";\n> + reg = <0xf03fe600 0x20>;\n> + interrupts = <1 13 0x304>;\n> + clocks = <&clk NPCM7XX_CLK_TIMER>;\n> + };\n> +\n> + apb {\n> + #address-cells = <1>;\n> + #size-cells = <1>;\n> + compatible = \"simple-bus\";\n> + interrupt-parent = <&gic>;\n> + ranges;\n> +\n> + timer0: timer@f0000000 {\n> + compatible = \"nuvoton,npcm750-timer\";\n> + interrupts = <0 32 4>;\n> + reg = <0xf0000000 0x1000>;\n> + clocks = <&clk NPCM7XX_CLK_TIMER>;\n> + };\n> +\n> + watchdog0: watchdog@f0008000 {\n> + compatible = \"nuvoton,npcm750-wdt\";\n> + interrupts = <0 47 4>;\n> + reg = <0xf0008000 0x1000>;\n> + status = \"disabled\";\n> + clocks = <&clk NPCM7XX_CLK_TIMER>;\n> + };\n> +\n> + watchdog1: watchdog@f0009000 {\n> + compatible = \"nuvoton,npcm750-wdt\";\n> + interrupts = <0 48 4>;\n> + reg = <0xf0009000 0x1000>;\n> + status = \"disabled\";\n> + clocks = <&clk NPCM7XX_CLK_TIMER>;\n> + };\n> +\n> + watchdog2: watchdog@f000a000 {\n> + compatible = \"nuvoton,npcm750-wdt\";\n> + interrupts = <0 49 4>;\n> + reg = <0xf000a000 0x1000>;\n> + status = \"disabled\";\n> + clocks = <&clk NPCM7XX_CLK_TIMER>;\n> + };\n> +\n> + serial0: serial0@f0001000 {\n> + compatible = \"nuvoton,npcm750-uart\";\n> + reg = <0xf0001000 0x1000>;\n> + clocks = <&clk NPCM7XX_CLK_UART_CORE>;\n> + interrupts = <0 2 4>;\n> + status = \"disabled\";\n> + };\n> +\n> + serial1: serial1@f0002000 {\n> + compatible = \"nuvoton,npcm750-uart\";\n> + reg = <0xf0002000 0x1000>;\n> + clocks = <&clk NPCM7XX_CLK_UART_CORE>;\n> + interrupts = <0 3 4>;\n> + status = \"disabled\";\n> + };\n> +\n> + serial2: serial2@f0003000 {\n> + compatible = \"nuvoton,npcm750-uart\";\n> + reg = <0xf0003000 0x1000>;\n> + clocks = <&clk NPCM7XX_CLK_UART_CORE>;\n> + interrupts = <0 4 4>;\n> + status = \"disabled\";\n> + };\n> +\n> + serial3: serial3@f0004000 {\n> + compatible = \"nuvoton,npcm750-uart\";\n> + reg = <0xf0004000 0x1000>;\n> + clocks = <&clk NPCM7XX_CLK_UART_CORE>;\n> + interrupts = <0 5 4>;\n> + status = \"disabled\";\n> + };\n> + };\n> +};\n> diff --git a/include/dt-bindings/clock/nuvoton,npcm7xx-clks.h b/include/dt-bindings/clock/nuvoton,npcm7xx-clks.h\n> new file mode 100644\n> index 000000000000..c69d3bbf7e42\n> --- /dev/null\n> +++ b/include/dt-bindings/clock/nuvoton,npcm7xx-clks.h\n> @@ -0,0 +1,39 @@\n> +/*\n> + * Copyright (C) 2016 Nuvoton Technologies, tali.perry@nuvoton.com\n> + *\n> + * This software is licensed under the terms of the GNU General Public\n> + * License version 2, as published by the Free Software Foundation, and\n> + * may be copied, distributed, and modified under those terms.\n> + */\n> +\n> +#ifndef _DT_BINDINGS_CLK_NPCM7XX_H\n> +#define _DT_BINDINGS_CLK_NPCM7XX_H\n> +\n> +#define NPCM7XX_CLK_PLL0 0\n> +#define NPCM7XX_CLK_PLL1 1\n> +#define NPCM7XX_CLK_PLL2 2\n> +#define NPCM7XX_CLK_GFX 3\n> +#define NPCM7XX_CLK_APB1 4\n> +#define NPCM7XX_CLK_APB2 5\n> +#define NPCM7XX_CLK_APB3 6\n> +#define NPCM7XX_CLK_APB4 7\n> +#define NPCM7XX_CLK_APB5 8\n> +#define NPCM7XX_CLK_MC 9\n> +#define NPCM7XX_CLK_CPU 10\n> +#define NPCM7XX_CLK_SPI0 11\n> +#define NPCM7XX_CLK_SPI3 12\n> +#define NPCM7XX_CLK_SPIX 13\n> +#define NPCM7XX_CLK_UART_CORE 14\n> +#define NPCM7XX_CLK_TIMER 15\n> +#define NPCM7XX_CLK_HOST_UART 16\n> +#define NPCM7XX_CLK_MMC 17\n> +#define NPCM7XX_CLK_SDHC 18\n> +#define NPCM7XX_CLK_ADC 19\n> +#define NPCM7XX_CLK_GFX_MEM 20\n> +#define NPCM7XX_CLK_USB_BRIDGE 21\n> +#define NPCM7XX_CLK_AXI 22\n> +#define NPCM7XX_CLK_AHB 23\n> +#define NPCM7XX_CLK_EMC 24\n> +#define NPCM7XX_CLK_GMAC 25\n> +\n> +#endif\n> --\n> 2.14.1.581.gf28d330327-goog\n>\n\n\nReviewed-by: Tomer Maimon \nTested-by: Tomer Maimon \n\nReviewed-by: Avi Fishman \nTested-by: Avi Fishman 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(PDT)","MIME-Version":"1.0","In-Reply-To":"<20170831225400.19756-3-brendanhiggins@google.com>","References":"<20170831225400.19756-1-brendanhiggins@google.com>\n\t<20170831225400.19756-3-brendanhiggins@google.com>","From":"Tomer Maimon ","Date":"Mon, 4 Sep 2017 17:24:44 +0300","Message-ID":"","Subject":"Re: [PATCH v2 2/3] arm: dts: add Nuvoton NPCM750 device tree","To":"Brendan Higgins ","Content-Type":"text/plain; charset=\"UTF-8\"","X-Mailman-Approved-At":"Tue, 05 Sep 2017 09:10:20 +1000","X-BeenThere":"openbmc@lists.ozlabs.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"Development list for OpenBMC ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"mark.rutland@arm.com, devicetree@vger.kernel.org, avifishman70@gmail.com,\n\topenbmc@lists.ozlabs.org, linux@armlinux.org.uk,\n\tlinux-kernel@vger.kernel.org, \n\trobh+dt@kernel.org, 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