[{"id":1767883,"web_url":"http://patchwork.ozlabs.org/comment/1767883/","msgid":"<20170913133206.rwobtu7ft5nrsh4p@localhost>","list_archive_url":null,"date":"2017-09-13T13:32:06","subject":"Re: [PATCH v2 10/28] arm64/sve: Low-level CPU setup","submitter":{"id":938,"url":"http://patchwork.ozlabs.org/api/people/938/","name":"Catalin Marinas","email":"catalin.marinas@arm.com"},"content":"On Thu, Aug 31, 2017 at 06:00:42PM +0100, Dave P Martin wrote:\n> diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S\n> index 877d42f..dd22ef2 100644\n> --- a/arch/arm64/mm/proc.S\n> +++ b/arch/arm64/mm/proc.S\n> @@ -27,6 +27,7 @@\n> #include \n> #include \n> #include \n> +#include \n> \n> #ifdef CONFIG_ARM64_64K_PAGES\n> #define TCR_TG_FLAGS\tTCR_TG0_64K | TCR_TG1_64K\n> @@ -186,8 +187,17 @@ ENTRY(__cpu_setup)\n> \ttlbi\tvmalle1\t\t\t\t// Invalidate local TLB\n> \tdsb\tnsh\n> \n> -\tmov\tx0, #3 << 20\n> -\tmsr\tcpacr_el1, x0\t\t\t// Enable FP/ASIMD\n> +\tmov\tx0, #3 << 20\t\t\t// FEN\n> +\n> +\t/* SVE */\n> +\tmrs\tx5, id_aa64pfr0_el1\n> +\tubfx\tx5, x5, #ID_AA64PFR0_SVE_SHIFT, #4\n> +\tcbz\tx5, 1f\n> +\n> +\tbic\tx0, x0, #CPACR_EL1_ZEN\n> +\torr\tx0, x0, #CPACR_EL1_ZEN_EL1EN\t// SVE: trap for EL0, not EL1\n> +1:\tmsr\tcpacr_el1, x0\t\t\t// Enable FP/ASIMD\n\nFor EL1, I wonder whether we could move this later to cpufeature.c. IIRC\nI tried to do the same with FPSIMD but hit an issue with EFI run-time\nservices (I may be wrong though).","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list libc-alpha@sourceware.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=sourceware.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=libc-alpha-return-84552-incoming=patchwork.ozlabs.org@sourceware.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tsecure) header.d=sourceware.org header.i=@sourceware.org\n\theader.b=\"Ld1J27ld\"; dkim-atps=neutral","sourceware.org; auth=none"],"Received":["from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xsjJM4tGLz9sNr\n\tfor ;\n\tWed, 13 Sep 2017 23:32:19 +1000 (AEST)","(qmail 119103 invoked by alias); 13 Sep 2017 13:32:13 -0000","(qmail 119087 invoked by uid 89); 13 Sep 2017 13:32:12 -0000"],"DomainKey-Signature":"a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:date:from:to:cc:subject:message-id:references\n\t:mime-version:content-type:in-reply-to; q=dns; s=default; b=pH8S\n\t5X1xCWwnThBS8ZcYqVGOLdQoW/EA0vYnuRFP2FmsqLmmASG76efPmpBtWFnyEjJO\n\tIFcOKKw1jlvXSzp5oid9xSXlyucXXN4TpYTXSIRtVPj8IJ8M96cEvFXjp583hgCx\n\tSti117TykYWELQrWoXFj/42HIThe/GreFbFv0XA=","DKIM-Signature":"v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:date:from:to:cc:subject:message-id:references\n\t:mime-version:content-type:in-reply-to; s=default; bh=41MYnL+NA5\n\tK0uqIM4a3fnZAYeoY=; b=Ld1J27ldmo+zwMbRvriB+vdASnD+DBmngZ6ifeV21+\n\tJdP9276xC5/EiGhAl2yyQlBb8oooZ+xxr948L1suxmvLaZAjUlV0atB1nnSxLI+k\n\tXlFG7wAw0JncPKJ3O0WwjpezjQdBGy0fQes6YRMzVHAQJpAfrtsvSpmZIxZAuz6e\n\tI=","Mailing-List":"contact libc-alpha-help@sourceware.org; run by ezmlm","Precedence":"bulk","List-Id":"","List-Unsubscribe":"","List-Subscribe":"","List-Archive":"","List-Post":"","List-Help":",\n\t","Sender":"libc-alpha-owner@sourceware.org","X-Virus-Found":"No","X-Spam-SWARE-Status":"No, score=-26.9 required=5.0 tests=BAYES_00, GIT_PATCH_0,\n\tGIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RP_MATCHES_RCVD,\n\tSPF_PASS autolearn=ham version=3.3.2 spammy=Hx-languages-length:1112,\n\torr, mrs, services","X-HELO":"foss.arm.com","Date":"Wed, 13 Sep 2017 06:32:06 -0700","From":"Catalin Marinas ","To":"Dave Martin ","Cc":"linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org,\n\tlibc-alpha@sourceware.org, \tArd Biesheuvel ,\n\tSzabolcs Nagy , \n\tWill Deacon , Richard Sandiford\n\t, Alex =?iso-8859-1?q?Benn=E9e?=\n\t, \tkvmarm@lists.cs.columbia.edu","Subject":"Re: [PATCH v2 10/28] arm64/sve: Low-level CPU setup","Message-ID":"<20170913133206.rwobtu7ft5nrsh4p@localhost>","References":"<1504198860-12951-1-git-send-email-Dave.Martin@arm.com>\n\t<1504198860-12951-11-git-send-email-Dave.Martin@arm.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<1504198860-12951-11-git-send-email-Dave.Martin@arm.com>","User-Agent":"NeoMutt/20170113 (1.7.2)"}},{"id":1768097,"web_url":"http://patchwork.ozlabs.org/comment/1768097/","msgid":"<20170913192110.GE23415@e103592.cambridge.arm.com>","list_archive_url":null,"date":"2017-09-13T19:21:11","subject":"Re: [PATCH v2 10/28] arm64/sve: Low-level CPU setup","submitter":{"id":26612,"url":"http://patchwork.ozlabs.org/api/people/26612/","name":"Dave Martin","email":"Dave.Martin@arm.com"},"content":"On Wed, Sep 13, 2017 at 06:32:06AM -0700, Catalin Marinas wrote:\n> On Thu, Aug 31, 2017 at 06:00:42PM +0100, Dave P Martin wrote:\n> > diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S\n> > index 877d42f..dd22ef2 100644\n> > --- a/arch/arm64/mm/proc.S\n> > +++ b/arch/arm64/mm/proc.S\n> > @@ -27,6 +27,7 @@\n> > #include \n> > #include \n> > #include \n> > +#include \n> > \n> > #ifdef CONFIG_ARM64_64K_PAGES\n> > #define TCR_TG_FLAGS\tTCR_TG0_64K | TCR_TG1_64K\n> > @@ -186,8 +187,17 @@ ENTRY(__cpu_setup)\n> > \ttlbi\tvmalle1\t\t\t\t// Invalidate local TLB\n> > \tdsb\tnsh\n> > \n> > -\tmov\tx0, #3 << 20\n> > -\tmsr\tcpacr_el1, x0\t\t\t// Enable FP/ASIMD\n> > +\tmov\tx0, #3 << 20\t\t\t// FEN\n> > +\n> > +\t/* SVE */\n> > +\tmrs\tx5, id_aa64pfr0_el1\n> > +\tubfx\tx5, x5, #ID_AA64PFR0_SVE_SHIFT, #4\n> > +\tcbz\tx5, 1f\n> > +\n> > +\tbic\tx0, x0, #CPACR_EL1_ZEN\n> > +\torr\tx0, x0, #CPACR_EL1_ZEN_EL1EN\t// SVE: trap for EL0, not EL1\n> > +1:\tmsr\tcpacr_el1, x0\t\t\t// Enable FP/ASIMD\n> \n> For EL1, I wonder whether we could move this later to cpufeature.c. IIRC\n> I tried to do the same with FPSIMD but hit an issue with EFI run-time\n> services (I may be wrong though).\n\nI'll take a look at this -- I believe it should be safe to disable this\ntrap for EL1 relatively late. This is needed before probing for\navailable vector lengths, but apart from that the kernel shouldn't touch\nSVE until/unless some user task uses SVE.\n\nThis would change if we eventually enable kernel-mode SVE, but I wouldn't\nexpect that to get used in early boot before the cpufeatures code runs.\n\nArd may have a view on this.\n\nCheers\n---Dave","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list libc-alpha@sourceware.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=sourceware.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=libc-alpha-return-84572-incoming=patchwork.ozlabs.org@sourceware.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tsecure) header.d=sourceware.org header.i=@sourceware.org\n\theader.b=\"i7I6jnY4\"; dkim-atps=neutral","sourceware.org; auth=none"],"Received":["from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xss3B1FcLz9sNw\n\tfor ;\n\tThu, 14 Sep 2017 05:21:25 +1000 (AEST)","(qmail 93668 invoked by alias); 13 Sep 2017 19:21:18 -0000","(qmail 93099 invoked by uid 89); 13 Sep 2017 19:21:17 -0000"],"DomainKey-Signature":"a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:date:from:to:cc:subject:message-id:references\n\t:mime-version:content-type:in-reply-to; q=dns; s=default; b=P2y0\n\tKtprxDr3v+a4giiJofGTy+4ZNL7Bm2mnIqFir71NQeTjQianb4JyOahaZmlvBWqu\n\tn782BWi6oHOQqRtrqz1dTv1S6+katdPuVhzurwqWS6XVnSd/tQu24PaZomjbQJVm\n\tq1rqtY5HGxlR0eHTJBF4A2FYqXNxuUOabIbw0N8=","DKIM-Signature":"v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:date:from:to:cc:subject:message-id:references\n\t:mime-version:content-type:in-reply-to; s=default; bh=xeLS6lZry5\n\tZxq8cOPS/P/Zy8+ZY=; b=i7I6jnY4tlH8zxYS3JW5AwyEhJaoZQD4dstS5+A8IP\n\tKxmz2adAQ09KPisIh3cgNMHKRM1H7V3a6CACo2qhhTQ0XC6KzqiGDPF+ZMFwn9d0\n\tBN8tdKgj0eoMpQICImt5EhKF/4ZFWsNZqBMinNj4hgaoFsrURU1SRio65aszWRnU\n\tg=","Mailing-List":"contact libc-alpha-help@sourceware.org; run by ezmlm","Precedence":"bulk","List-Id":"","List-Unsubscribe":"","List-Subscribe":"","List-Archive":"","List-Post":"","List-Help":",\n\t","Sender":"libc-alpha-owner@sourceware.org","X-Virus-Found":"No","X-Spam-SWARE-Status":"No, score=-26.9 required=5.0 tests=BAYES_00, GIT_PATCH_0,\n\tGIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RP_MATCHES_RCVD,\n\tSPF_PASS autolearn=ham version=3.3.2 spammy=","X-HELO":"foss.arm.com","Date":"Wed, 13 Sep 2017 20:21:11 +0100","From":"Dave Martin ","To":"Catalin Marinas ","Cc":"linux-arch@vger.kernel.org, libc-alpha@sourceware.org, Ard Biesheuvel\n\t, \tSzabolcs Nagy ,\n\tRichard Sandiford , \n\tWill Deacon , Alex =?iso-8859-1?q?Benn=E9e?=\n\t, kvmarm@lists.cs.columbia.edu,\n\tlinux-arm-kernel@lists.infradead.org","Subject":"Re: [PATCH v2 10/28] arm64/sve: Low-level CPU setup","Message-ID":"<20170913192110.GE23415@e103592.cambridge.arm.com>","References":"<1504198860-12951-1-git-send-email-Dave.Martin@arm.com>\n\t<1504198860-12951-11-git-send-email-Dave.Martin@arm.com>\n\t<20170913133206.rwobtu7ft5nrsh4p@localhost>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170913133206.rwobtu7ft5nrsh4p@localhost>","User-Agent":"Mutt/1.5.23 (2014-03-12)"}},{"id":1780454,"web_url":"http://patchwork.ozlabs.org/comment/1780454/","msgid":"<20171005104716.GV3611@e103592.cambridge.arm.com>","list_archive_url":null,"date":"2017-10-05T10:47:17","subject":"Re: [PATCH v2 10/28] arm64/sve: Low-level CPU setup","submitter":{"id":26612,"url":"http://patchwork.ozlabs.org/api/people/26612/","name":"Dave Martin","email":"Dave.Martin@arm.com"},"content":"On Wed, Sep 13, 2017 at 08:21:11PM +0100, Dave Martin wrote:\n> On Wed, Sep 13, 2017 at 06:32:06AM -0700, Catalin Marinas wrote:\n> > On Thu, Aug 31, 2017 at 06:00:42PM +0100, Dave P Martin wrote:\n> > > diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S\n> > > index 877d42f..dd22ef2 100644\n> > > --- a/arch/arm64/mm/proc.S\n> > > +++ b/arch/arm64/mm/proc.S\n> > > @@ -27,6 +27,7 @@\n> > > #include \n> > > #include \n> > > #include \n> > > +#include \n> > > \n> > > #ifdef CONFIG_ARM64_64K_PAGES\n> > > #define TCR_TG_FLAGS\tTCR_TG0_64K | TCR_TG1_64K\n> > > @@ -186,8 +187,17 @@ ENTRY(__cpu_setup)\n> > > \ttlbi\tvmalle1\t\t\t\t// Invalidate local TLB\n> > > \tdsb\tnsh\n> > > \n> > > -\tmov\tx0, #3 << 20\n> > > -\tmsr\tcpacr_el1, x0\t\t\t// Enable FP/ASIMD\n> > > +\tmov\tx0, #3 << 20\t\t\t// FEN\n> > > +\n> > > +\t/* SVE */\n> > > +\tmrs\tx5, id_aa64pfr0_el1\n> > > +\tubfx\tx5, x5, #ID_AA64PFR0_SVE_SHIFT, #4\n> > > +\tcbz\tx5, 1f\n> > > +\n> > > +\tbic\tx0, x0, #CPACR_EL1_ZEN\n> > > +\torr\tx0, x0, #CPACR_EL1_ZEN_EL1EN\t// SVE: trap for EL0, not EL1\n> > > +1:\tmsr\tcpacr_el1, x0\t\t\t// Enable FP/ASIMD\n> > \n> > For EL1, I wonder whether we could move this later to cpufeature.c. IIRC\n> > I tried to do the same with FPSIMD but hit an issue with EFI run-time\n> > services (I may be wrong though).\n> \n> I'll take a look at this -- I believe it should be safe to disable this\n> trap for EL1 relatively late. This is needed before probing for\n> available vector lengths, but apart from that the kernel shouldn't touch\n> SVE until/unless some user task uses SVE.\n> \n> This would change if we eventually enable kernel-mode SVE, but I wouldn't\n> expect that to get used in early boot before the cpufeatures code runs.\n> \n> Ard may have a view on this.\n\nI've had a go at this, but there's a lot of splatter.\n\nI can add a helper el1_enable_sve() say, and call it before probing\nZCR_EL1 in the cpufeatures code.\n\nThis makes enabling SVE a side-effect of the cpufeatures code, which\nI'm not that comfortable with -- it feels like something that later\nrefactoring could easily break.\n\nI can also add an explicit call to el1_enable_sve() in sve_setup(),\nbut this only works on the boot cpu.\n\nFor secondaries, I could add something in secondary_start_kernel(),\nbut this looks incongruous since there's no other call to do something\nsimilar yet.\n\n\n** Suzuki, do we have any other case where the trap for a CPU feature is\nturned off by the cpufeatures code? If there's already a template for\nthis then I'm happy to follow it.\n\nOtherwise, maybe it's simpler to keep it in __cpu_setup after all\nsince that's a common path that all CPUs pass through.\n\nCheers\n---Dave","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list libc-alpha@sourceware.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=sourceware.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=libc-alpha-return-85410-incoming=patchwork.ozlabs.org@sourceware.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tsecure) header.d=sourceware.org header.i=@sourceware.org\n\theader.b=\"IS62bXw0\"; dkim-atps=neutral","sourceware.org; auth=none"],"Received":["from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y78c82Y8Lz9t44\n\tfor ;\n\tThu, 5 Oct 2017 21:47:36 +1100 (AEDT)","(qmail 86588 invoked by alias); 5 Oct 2017 10:47:29 -0000","(qmail 80695 invoked by uid 89); 5 Oct 2017 10:47:27 -0000"],"DomainKey-Signature":"a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:date:from:to:cc:subject:message-id:references\n\t:mime-version:content-type:in-reply-to; q=dns; s=default; b=mp2j\n\tHZe60OUittAPF/gVT+8sOdc+ad9Hm+BfkcrtLXPVTHGqM5PKF/c5T4UhzAklJYQp\n\tzGuh7y53djthz80pAEWYJScR0HuCItSDKDCMVDNzNfnJf187Qa3yL8jY5Fdl7WPD\n\tTD3nT5tEhtftbO7eFgq99unFJM5IN+v8tsi8Bpk=","DKIM-Signature":"v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:date:from:to:cc:subject:message-id:references\n\t:mime-version:content-type:in-reply-to; s=default; bh=p5Ezf1zyut\n\t7i8NTmtklqeYZOoCg=; b=IS62bXw0gAtQHn3apzbmmRqm/eKK+D2GjoFwk0rJN8\n\tOPDQgoTSVyRcGkv8woe1eQoua1ZIBMOdi1hBtwiTvMg7p6FPxhqEHSA3P6g96p0v\n\tt2HGLu3/6PwKe1UgNglGBG8ycqu4UqDbF97unFeR4f22eK6XTrCsfRepw6ib8kGc\n\tI=","Mailing-List":"contact libc-alpha-help@sourceware.org; run by ezmlm","Precedence":"bulk","List-Id":"","List-Unsubscribe":"","List-Subscribe":"","List-Archive":"","List-Post":"","List-Help":",\n\t","Sender":"libc-alpha-owner@sourceware.org","X-Virus-Found":"No","X-Spam-SWARE-Status":"No, score=-26.9 required=5.0 tests=BAYES_00, GIT_PATCH_0,\n\tGIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RP_MATCHES_RCVD,\n\tSPF_PASS autolearn=ham version=3.3.2 spammy=ard, efi,\n\tH*Ad:D*columbia.edu, Hx-languages-length:2707","X-HELO":"foss.arm.com","Date":"Thu, 5 Oct 2017 11:47:17 +0100","From":"Dave Martin ","To":"Catalin Marinas ,\n\tSuzuki Poulose ","Cc":"linux-arch@vger.kernel.org, libc-alpha@sourceware.org, Ard Biesheuvel\n\t, \tSzabolcs Nagy ,\n\tRichard Sandiford , \n\tWill Deacon , Alex =?iso-8859-1?q?Benn=E9e?=\n\t, kvmarm@lists.cs.columbia.edu,\n\tlinux-arm-kernel@lists.infradead.org","Subject":"Re: [PATCH v2 10/28] arm64/sve: Low-level CPU setup","Message-ID":"<20171005104716.GV3611@e103592.cambridge.arm.com>","References":"<1504198860-12951-1-git-send-email-Dave.Martin@arm.com>\n\t<1504198860-12951-11-git-send-email-Dave.Martin@arm.com>\n\t<20170913133206.rwobtu7ft5nrsh4p@localhost>\n\t<20170913192110.GE23415@e103592.cambridge.arm.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170913192110.GE23415@e103592.cambridge.arm.com>","User-Agent":"Mutt/1.5.23 (2014-03-12)"}},{"id":1780468,"web_url":"http://patchwork.ozlabs.org/comment/1780468/","msgid":"<76020d51-a971-e73e-9fba-1e2ec97985dc@arm.com>","list_archive_url":null,"date":"2017-10-05T11:04:12","subject":"Re: [PATCH v2 10/28] arm64/sve: Low-level CPU setup","submitter":{"id":65822,"url":"http://patchwork.ozlabs.org/api/people/65822/","name":"Suzuki K Poulose","email":"suzuki.poulose@arm.com"},"content":"On 05/10/17 11:47, Dave Martin wrote:\n> On Wed, Sep 13, 2017 at 08:21:11PM +0100, Dave Martin wrote:\n>> On Wed, Sep 13, 2017 at 06:32:06AM -0700, Catalin Marinas wrote:\n>>> On Thu, Aug 31, 2017 at 06:00:42PM +0100, Dave P Martin wrote:\n>>>> diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S\n>>>> index 877d42f..dd22ef2 100644\n>>>> --- a/arch/arm64/mm/proc.S\n>>>> +++ b/arch/arm64/mm/proc.S\n>>>> @@ -27,6 +27,7 @@\n>>>> #include \n>>>> #include \n>>>> #include \n>>>> +#include \n>>>> \n>>>> #ifdef CONFIG_ARM64_64K_PAGES\n>>>> #define TCR_TG_FLAGS\tTCR_TG0_64K | TCR_TG1_64K\n>>>> @@ -186,8 +187,17 @@ ENTRY(__cpu_setup)\n>>>> \ttlbi\tvmalle1\t\t\t\t// Invalidate local TLB\n>>>> \tdsb\tnsh\n>>>> \n>>>> -\tmov\tx0, #3 << 20\n>>>> -\tmsr\tcpacr_el1, x0\t\t\t// Enable FP/ASIMD\n>>>> +\tmov\tx0, #3 << 20\t\t\t// FEN\n>>>> +\n>>>> +\t/* SVE */\n>>>> +\tmrs\tx5, id_aa64pfr0_el1\n>>>> +\tubfx\tx5, x5, #ID_AA64PFR0_SVE_SHIFT, #4\n>>>> +\tcbz\tx5, 1f\n>>>> +\n>>>> +\tbic\tx0, x0, #CPACR_EL1_ZEN\n>>>> +\torr\tx0, x0, #CPACR_EL1_ZEN_EL1EN\t// SVE: trap for EL0, not EL1\n>>>> +1:\tmsr\tcpacr_el1, x0\t\t\t// Enable FP/ASIMD\n>>>\n>>> For EL1, I wonder whether we could move this later to cpufeature.c. IIRC\n>>> I tried to do the same with FPSIMD but hit an issue with EFI run-time\n>>> services (I may be wrong though).\n>>\n>> I'll take a look at this -- I believe it should be safe to disable this\n>> trap for EL1 relatively late. This is needed before probing for\n>> available vector lengths, but apart from that the kernel shouldn't touch\n>> SVE until/unless some user task uses SVE.\n>>\n>> This would change if we eventually enable kernel-mode SVE, but I wouldn't\n>> expect that to get used in early boot before the cpufeatures code runs.\n>>\n>> Ard may have a view on this.\n> \n> I've had a go at this, but there's a lot of splatter.\n> \n> I can add a helper el1_enable_sve() say, and call it before probing\n> ZCR_EL1 in the cpufeatures code.\n> \n> This makes enabling SVE a side-effect of the cpufeatures code, which\n> I'm not that comfortable with -- it feels like something that later\n> refactoring could easily break.\n> \n> I can also add an explicit call to el1_enable_sve() in sve_setup(),\n> but this only works on the boot cpu.\n> \n> For secondaries, I could add something in secondary_start_kernel(),\n> but this looks incongruous since there's no other call to do something\n> similar yet.\n> \n> \n> ** Suzuki, do we have any other case where the trap for a CPU feature is\n> turned off by the cpufeatures code? If there's already a template for\n> this then I'm happy to follow it.\n\nThe closest thing you have is an \"enable\" callback for each \"available\"\ncapability, which gets invoked on all CPUs (boot time active CPUs and the\nones which are brought up later). This is used by things like, PAN to\ndo some CPU specific setups.\n\nSee :\n enable_cpu_capabilities() // For all boot time active CPUs\n and\n verify_local_cpu_features() // For CPUs brought up later\n\nCheers\nSuzuki","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list libc-alpha@sourceware.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=sourceware.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=libc-alpha-return-85416-incoming=patchwork.ozlabs.org@sourceware.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tsecure) header.d=sourceware.org header.i=@sourceware.org\n\theader.b=\"WfZjzkRu\"; dkim-atps=neutral","sourceware.org; auth=none"],"Received":["from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y78zf3TCGz9t2Z\n\tfor ;\n\tThu, 5 Oct 2017 22:04:30 +1100 (AEDT)","(qmail 37395 invoked by alias); 5 Oct 2017 11:04:20 -0000","(qmail 37252 invoked by uid 89); 5 Oct 2017 11:04:19 -0000"],"DomainKey-Signature":"a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:subject:to:cc:references:from:message-id:date\n\t:mime-version:in-reply-to:content-type\n\t:content-transfer-encoding; q=dns; s=default; b=nOByH8BOUnddNgs8\n\tElShY0Q60is8Nli5Xut1jxCssp3ortfONjpAoLB/oAJRhusOab0TszDFlR3BUO1p\n\t0tYe6X8AKwfdP9UYViB9spr4VCAgu7EWX3gUq95x7bk3Z49t0snRJqttJDEWfhX2\n\tb7o/U8DPxsIPSVMFxj129K90ifg=","DKIM-Signature":"v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:subject:to:cc:references:from:message-id:date\n\t:mime-version:in-reply-to:content-type\n\t:content-transfer-encoding; s=default; bh=nX07677iqr7te3at/OE0lB\n\t8Eg+g=; b=WfZjzkRuZNtt5Huma2LcaSynQNFpwoe0zDBPToQlhtUTa9qBjRA8jb\n\t3zbz8YIM/sbEihwFT4zJaa8wf+K+NqdSQm8r+rCVSTBSW2vJp/3KiXKPhJGWInwt\n\tq0uF2ul5y2QVwN9JsN6l7Gy7ALbGePiRbN9jSemo4qiOIOBfCjfB4=","Mailing-List":"contact libc-alpha-help@sourceware.org; run by ezmlm","Precedence":"bulk","List-Id":"","List-Unsubscribe":"","List-Subscribe":"","List-Archive":"","List-Post":"","List-Help":",\n\t","Sender":"libc-alpha-owner@sourceware.org","X-Virus-Found":"No","X-Spam-SWARE-Status":"No, score=-26.9 required=5.0 tests=BAYES_00, GIT_PATCH_0,\n\tGIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RP_MATCHES_RCVD,\n\tSPF_PASS autolearn=ham version=3.3.2 spammy=pan","X-HELO":"foss.arm.com","Subject":"Re: [PATCH v2 10/28] arm64/sve: Low-level CPU setup","To":"Dave Martin ,\n\tCatalin Marinas ","Cc":"linux-arch@vger.kernel.org, libc-alpha@sourceware.org, Ard Biesheuvel\n\t, Szabolcs Nagy ,\n\tRichard Sandiford\n\t, Will Deacon ,\n\t=?utf-8?q?Alex_Benn=C3=A9e?= ,\n\tkvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org","References":"<1504198860-12951-1-git-send-email-Dave.Martin@arm.com>\n\t<1504198860-12951-11-git-send-email-Dave.Martin@arm.com>\n\t<20170913133206.rwobtu7ft5nrsh4p@localhost>\n\t<20170913192110.GE23415@e103592.cambridge.arm.com>\n\t<20171005104716.GV3611@e103592.cambridge.arm.com>","From":"Suzuki K Poulose ","Message-ID":"<76020d51-a971-e73e-9fba-1e2ec97985dc@arm.com>","Date":"Thu, 5 Oct 2017 12:04:12 +0100","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<20171005104716.GV3611@e103592.cambridge.arm.com>","Content-Type":"text/plain; charset=us-ascii; format=flowed","Content-Transfer-Encoding":"7bit"}},{"id":1780490,"web_url":"http://patchwork.ozlabs.org/comment/1780490/","msgid":"<20171005112217.GW3611@e103592.cambridge.arm.com>","list_archive_url":null,"date":"2017-10-05T11:22:18","subject":"Re: [PATCH v2 10/28] arm64/sve: Low-level CPU setup","submitter":{"id":26612,"url":"http://patchwork.ozlabs.org/api/people/26612/","name":"Dave Martin","email":"Dave.Martin@arm.com"},"content":"On Thu, Oct 05, 2017 at 12:04:12PM +0100, Suzuki K Poulose wrote:\n> On 05/10/17 11:47, Dave Martin wrote:\n\n[...]\n\n> >>>On Thu, Aug 31, 2017 at 06:00:42PM +0100, Dave P Martin wrote:\n> >>>>diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S\n> >>>>index 877d42f..dd22ef2 100644\n> >>>>--- a/arch/arm64/mm/proc.S\n> >>>>+++ b/arch/arm64/mm/proc.S\n> >>>>@@ -27,6 +27,7 @@\n> >>>> #include \n> >>>> #include \n> >>>> #include \n> >>>>+#include \n> >>>> #ifdef CONFIG_ARM64_64K_PAGES\n> >>>> #define TCR_TG_FLAGS\tTCR_TG0_64K | TCR_TG1_64K\n> >>>>@@ -186,8 +187,17 @@ ENTRY(__cpu_setup)\n> >>>> \ttlbi\tvmalle1\t\t\t\t// Invalidate local TLB\n> >>>> \tdsb\tnsh\n> >>>>-\tmov\tx0, #3 << 20\n> >>>>-\tmsr\tcpacr_el1, x0\t\t\t// Enable FP/ASIMD\n> >>>>+\tmov\tx0, #3 << 20\t\t\t// FEN\n> >>>>+\n> >>>>+\t/* SVE */\n> >>>>+\tmrs\tx5, id_aa64pfr0_el1\n> >>>>+\tubfx\tx5, x5, #ID_AA64PFR0_SVE_SHIFT, #4\n> >>>>+\tcbz\tx5, 1f\n> >>>>+\n> >>>>+\tbic\tx0, x0, #CPACR_EL1_ZEN\n> >>>>+\torr\tx0, x0, #CPACR_EL1_ZEN_EL1EN\t// SVE: trap for EL0, not EL1\n> >>>>+1:\tmsr\tcpacr_el1, x0\t\t\t// Enable FP/ASIMD\n\n[..]\n\n> >I can add a helper el1_enable_sve() say, and call it before probing\n> >ZCR_EL1 in the cpufeatures code.\n> >\n> >This makes enabling SVE a side-effect of the cpufeatures code, which\n> >I'm not that comfortable with -- it feels like something that later\n> >refactoring could easily break.\n> >\n> >I can also add an explicit call to el1_enable_sve() in sve_setup(),\n> >but this only works on the boot cpu.\n> >\n> >For secondaries, I could add something in secondary_start_kernel(),\n> >but this looks incongruous since there's no other call to do something\n> >similar yet.\n> >\n> >\n> >** Suzuki, do we have any other case where the trap for a CPU feature is\n> >turned off by the cpufeatures code? If there's already a template for\n> >this then I'm happy to follow it.\n> \n> The closest thing you have is an \"enable\" callback for each \"available\"\n> capability, which gets invoked on all CPUs (boot time active CPUs and the\n> ones which are brought up later). This is used by things like, PAN to\n> do some CPU specific setups.\n> \n> See :\n> enable_cpu_capabilities() // For all boot time active CPUs\n> and\n> verify_local_cpu_features() // For CPUs brought up later\n\nThat may allow me to do something tidier, provided the enable method is\ncalled early enough.\n\nI'll take a look.\n\nCheers\n---Dave","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list libc-alpha@sourceware.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=sourceware.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=libc-alpha-return-85418-incoming=patchwork.ozlabs.org@sourceware.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tsecure) header.d=sourceware.org header.i=@sourceware.org\n\theader.b=\"XzncKu8P\"; dkim-atps=neutral","sourceware.org; auth=none"],"Received":["from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y79NS0pgZz9t2h\n\tfor ;\n\tThu, 5 Oct 2017 22:22:31 +1100 (AEDT)","(qmail 76752 invoked by alias); 5 Oct 2017 11:22:25 -0000","(qmail 75777 invoked by uid 89); 5 Oct 2017 11:22:25 -0000"],"DomainKey-Signature":"a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:date:from:to:cc:subject:message-id:references\n\t:mime-version:content-type:in-reply-to; q=dns; s=default; b=J5Et\n\tzi/mjvEzFXmKrSx2D9JhtDl6m8JjMy5zIAZlSB+5YYtxLaX96rS+F5bL3+T1WsKp\n\tvkiQqaB5CnxbsVfxjRkCvr/0S6QHxZ40OTF17Rk5V0BZEjeisjd33szumpkU0NZK\n\t00vlRY0v56fKIrvagY9ZfcyUYkq9At3cZpRsFWw=","DKIM-Signature":"v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:date:from:to:cc:subject:message-id:references\n\t:mime-version:content-type:in-reply-to; s=default; bh=V7LM7Vd5O4\n\ttW5eHMvbbMyAhWbPo=; b=XzncKu8P6plojcPUo54zoLidKMx8xXvZyN4j8NiJ9B\n\tjesDl2I+kh7ZqfJ7knxngX4misv5+NWcHQ+z5IMhpHr6Mfe3cQBjg4DCW/71KRl+\n\tMZz803wygXCIxEh3/3Ca3iak/uC2wf3EwzJLFe4BLc+pE8VDt8FT8KbejMLLNKdd\n\t0=","Mailing-List":"contact libc-alpha-help@sourceware.org; run by ezmlm","Precedence":"bulk","List-Id":"","List-Unsubscribe":"","List-Subscribe":"","List-Archive":"","List-Post":"","List-Help":",\n\t","Sender":"libc-alpha-owner@sourceware.org","X-Virus-Found":"No","X-Spam-SWARE-Status":"No, score=-26.9 required=5.0 tests=BAYES_00, GIT_PATCH_0,\n\tGIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RP_MATCHES_RCVD,\n\tSPF_PASS autolearn=ham version=3.3.2 spammy=","X-HELO":"foss.arm.com","Date":"Thu, 5 Oct 2017 12:22:18 +0100","From":"Dave Martin ","To":"Suzuki K Poulose ","Cc":"Catalin Marinas , linux-arch@vger.kernel.org,\n\tlibc-alpha@sourceware.org, \tArd Biesheuvel ,\n\tSzabolcs Nagy , \n\tRichard Sandiford , Will Deacon\n\t, Alex =?iso-8859-1?q?Benn=E9e?=\n\t, kvmarm@lists.cs.columbia.edu,\n\tlinux-arm-kernel@lists.infradead.org","Subject":"Re: [PATCH v2 10/28] arm64/sve: Low-level CPU setup","Message-ID":"<20171005112217.GW3611@e103592.cambridge.arm.com>","References":"<1504198860-12951-1-git-send-email-Dave.Martin@arm.com>\n\t<1504198860-12951-11-git-send-email-Dave.Martin@arm.com>\n\t<20170913133206.rwobtu7ft5nrsh4p@localhost>\n\t<20170913192110.GE23415@e103592.cambridge.arm.com>\n\t<20171005104716.GV3611@e103592.cambridge.arm.com>\n\t<76020d51-a971-e73e-9fba-1e2ec97985dc@arm.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<76020d51-a971-e73e-9fba-1e2ec97985dc@arm.com>","User-Agent":"Mutt/1.5.23 (2014-03-12)"}}]