[{"id":1764239,"web_url":"http://patchwork.ozlabs.org/comment/1764239/","msgid":"<5FA513F682BE7F4EAAB8EE035D5B08E44109DFE8@G01JPEXMBKW02>","list_archive_url":null,"date":"2017-09-06T16:21:50","subject":"RE: [PATCH v2 19/28] arm64/sve: ptrace and ELF coredump support","submitter":{"id":72310,"url":"http://patchwork.ozlabs.org/api/people/72310/","name":"Okamoto, Takayuki","email":"tokamoto@jp.fujitsu.com"},"content":"Hi Dave,\r\n\r\nI am an engineer of the postK computer from Fujitsu.\r\n\r\nWhen I tried to read \"max_vl\" by ptrace with this patch on our local SVE \r\nsimulator, it was read as zero.\r\nI think the cause of this incident is that \"max_vl\" is set as \"header->vl\" \r\nonly on warning case in sve_init_header_from_task().\r\n\"max_vl\" should be set up also on normal case, like the following patch.\r\n\r\n\r\n--- a/arch/arm64/kernel/ptrace.c\r\n+++ b/arch/arm64/kernel/ptrace.c\r\n@@ -755,6 +755,8 @@ static void sve_init_header_from_task(struct user_sve_header *header,\r\n\r\n if (WARN_ON(!sve_vl_valid(sve_max_vl)))\r\n header->max_vl = header->vl;\r\n+ else\r\n+ header->max_vl = sve_max_vl;\r\n\r\n header->size = SVE_PT_SIZE(vq, header->flags);\r\n header->max_size = SVE_PT_SIZE(sve_vq_from_vl(header->max_vl),\r\n\r\n\r\nBest regards,\r\nTakayuki Okamoto\r\n\r\n-----Original Message-----\r\nFrom: gdb-owner@sourceware.org [mailto:gdb-owner@sourceware.org] On Behalf Of Dave Martin\r\nSent: Friday, September 1, 2017 2:01 AM\r\nTo: linux-arm-kernel@lists.infradead.org\r\nCc: Catalin Marinas ; Will Deacon ; Ard Biesheuvel ; Alex Bennée ; Szabolcs Nagy ; Richard Sandiford ; kvmarm@lists.cs.columbia.edu; libc-alpha@sourceware.org; linux-arch@vger.kernel.org; gdb@sourceware.org; Alan Hayward ; Yao Qi ; Oleg Nesterov ; Alexander Viro \r\nSubject: [PATCH v2 19/28] arm64/sve: ptrace and ELF coredump support\r\n\r\nThis patch defines and implements a new regset NT_ARM_SVE, which\r\ndescribes a thread's SVE register state. This allows a debugger to\r\nmanipulate the SVE state, as well as being included in ELF\r\ncoredumps for post-mortem debugging.\r\n\r\nBecause the regset size and layout are dependent on the thread's\r\ncurrent vector length, it is not possible to define a C struct to\r\ndescribe the regset contents as is done for existing regsets.\r\nInstead, and for the same reasons, NT_ARM_SVE is based on the\r\nfreeform variable-layout approach used for the SVE signal frame.\r\n\r\nAdditionally, to reduce debug overhead when debugging threads that\r\nmight or might not have live SVE register state, NT_ARM_SVE may be\r\npresented in one of two different formats: the old struct\r\nuser_fpsimd_state format is embedded for describing the state of a\r\nthread with no live SVE state, whereas a new variable-layout\r\nstructure is embedded for describing live SVE state. This avoids a\r\ndebugger needing to poll NT_PRFPREG in addition to NT_ARM_SVE, and\r\nallows existing userspace code to handle the non-SVE case without\r\ntoo much modification.\r\n\r\nFor this to work, NT_ARM_SVE is defined with a fixed-format header\r\nof type struct user_sve_header, which the recipient can use to\r\nfigure out the content, size and layout of the reset of the regset.\r\nAccessor macros are defined to allow the vector-length-dependent\r\nparts of the regset to be manipulated.\r\n\r\nSigned-off-by: Alan Hayward \r\nSigned-off-by: Dave Martin \r\nCc: Alex Bennée \r\n\r\n---\r\n\r\nChanges since v1\r\n----------------\r\n\r\nOther changes related to Alex Bennée's comments:\r\n\r\n* Migrate to SVE_VQ_BYTES instead of magic numbers.\r\n\r\nRequested by Alex Bennée:\r\n\r\n* Thin out BUG_ON()s:\r\nRedundant BUG_ON()s and ones that just check invariants are removed.\r\nImportant sanity-checks are migrated to WARN_ON()s, with some\r\nminimal best-effort patch-up code.\r\n\r\nOther:\r\n\r\n* [ABI fix] Bail out with -EIO if attempting to set the\r\nSVE regs for an unsupported VL, instead of misparsing the regset data.\r\n\r\n* Replace some in-kernel open-coded arithmetic with ALIGN()/\r\nDIV_ROUND_UP().\r\n---\r\n arch/arm64/include/asm/fpsimd.h | 13 +-\r\n arch/arm64/include/uapi/asm/ptrace.h | 135 ++++++++++++++++++\r\n arch/arm64/kernel/fpsimd.c | 40 +++++-\r\n arch/arm64/kernel/ptrace.c | 270 +++++++++++++++++++++++++++++++++--\r\n include/uapi/linux/elf.h | 1 +\r\n 5 files changed, 449 insertions(+), 10 deletions(-)\r\n\r\ndiff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsimd.h\r\nindex 6c22624..2723cca 100644\r\n--- a/arch/arm64/include/asm/fpsimd.h\r\n+++ b/arch/arm64/include/asm/fpsimd.h\r\n@@ -38,13 +38,16 @@ struct fpsimd_state {\r\n \t\t\t__uint128_t vregs[32];\r\n \t\t\tu32 fpsr;\r\n \t\t\tu32 fpcr;\r\n+\t\t\t/*\r\n+\t\t\t * For ptrace compatibility, pad to next 128-bit\r\n+\t\t\t * boundary here if extending this struct.\r\n+\t\t\t */\r\n \t\t};\r\n \t};\r\n \t/* the id of the last cpu to have restored this state */\r\n \tunsigned int cpu;\r\n };\r\n \r\n-\r\n #if defined(__KERNEL__) && defined(CONFIG_COMPAT)\r\n /* Masks for extracting the FPSR and FPCR from the FPSCR */\r\n #define VFP_FPSCR_STAT_MASK\t0xf800009f\r\n@@ -89,6 +92,10 @@ extern void sve_alloc(struct task_struct *task);\r\n extern void fpsimd_release_thread(struct task_struct *task);\r\n extern void fpsimd_dup_sve(struct task_struct *dst,\r\n \t\t\t struct task_struct const *src);\r\n+extern void fpsimd_sync_to_sve(struct task_struct *task);\r\n+extern void sve_sync_to_fpsimd(struct task_struct *task);\r\n+extern void sve_sync_from_fpsimd_zeropad(struct task_struct *task);\r\n+\r\n extern int sve_set_vector_length(struct task_struct *task,\r\n \t\t\t\t unsigned long vl, unsigned long flags);\r\n \r\n@@ -103,6 +110,10 @@ static void __maybe_unused sve_alloc(struct task_struct *task) { }\r\n static void __maybe_unused fpsimd_release_thread(struct task_struct *task) { }\r\n static void __maybe_unused fpsimd_dup_sve(struct task_struct *dst,\r\n \t\t\t\t\t struct task_struct const *src) { }\r\n+static void __maybe_unused sve_sync_to_fpsimd(struct task_struct *task) { }\r\n+static void __maybe_unused sve_sync_from_fpsimd_zeropad(\r\n+\tstruct task_struct *task) { }\r\n+\r\n static void __maybe_unused sve_init_vq_map(void) { }\r\n static void __maybe_unused sve_update_vq_map(void) { }\r\n static int __maybe_unused sve_verify_vq_map(void) { return 0; }\r\ndiff --git a/arch/arm64/include/uapi/asm/ptrace.h b/arch/arm64/include/uapi/asm/ptrace.h\r\nindex d1ff83d..1915ab0 100644\r\n--- a/arch/arm64/include/uapi/asm/ptrace.h\r\n+++ b/arch/arm64/include/uapi/asm/ptrace.h\r\n@@ -22,6 +22,7 @@\r\n #include \r\n \r\n #include \r\n+#include \r\n \r\n \r\n /*\r\n@@ -63,6 +64,8 @@\r\n \r\n #ifndef __ASSEMBLY__\r\n \r\n+#include \r\n+\r\n /*\r\n * User structures for general purpose, floating point and debug registers.\r\n */\r\n@@ -90,6 +93,138 @@ struct user_hwdebug_state {\r\n \t}\t\tdbg_regs[16];\r\n };\r\n \r\n+/* SVE/FP/SIMD state (NT_ARM_SVE) */\r\n+\r\n+struct user_sve_header {\r\n+\t__u32 size; /* total meaningful regset content in bytes */\r\n+\t__u32 max_size; /* maxmium possible size for this thread */\r\n+\t__u16 vl; /* current vector length */\r\n+\t__u16 max_vl; /* maximum possible vector length */\r\n+\t__u16 flags;\r\n+\t__u16 __reserved;\r\n+};\r\n+\r\n+/* Definitions for user_sve_header.flags: */\r\n+#define SVE_PT_REGS_MASK\t\t(1 << 0)\r\n+\r\n+/* Flags: must be kept in sync with prctl interface in */\r\n+#define SVE_PT_REGS_FPSIMD\t\t0\r\n+#define SVE_PT_REGS_SVE\t\t\tSVE_PT_REGS_MASK\r\n+\r\n+#define SVE_PT_VL_INHERIT\t\t(PR_SVE_VL_INHERIT >> 16)\r\n+#define SVE_PT_VL_ONEXEC\t\t(PR_SVE_SET_VL_ONEXEC >> 16)\r\n+\r\n+\r\n+/*\r\n+ * The remainder of the SVE state follows struct user_sve_header. The\r\n+ * total size of the SVE state (including header) depends on the\r\n+ * metadata in the header: SVE_PT_SIZE(vq, flags) gives the total size\r\n+ * of the state in bytes, including the header.\r\n+ *\r\n+ * Refer to for details of how to pass the correct\r\n+ * \"vq\" argument to these macros.\r\n+ */\r\n+\r\n+/* Offset from the start of struct user_sve_header to the register data */\r\n+#define SVE_PT_REGS_OFFSET\t\t\t\t\t\\\r\n+\t((sizeof(struct sve_context) + (SVE_VQ_BYTES - 1))\t\\\r\n+\t\t/ SVE_VQ_BYTES * SVE_VQ_BYTES)\r\n+\r\n+/*\r\n+ * The register data content and layout depends on the value of the\r\n+ * flags field.\r\n+ */\r\n+\r\n+/*\r\n+ * (flags & SVE_PT_REGS_MASK) == SVE_PT_REGS_FPSIMD case:\r\n+ *\r\n+ * The payload starts at offset SVE_PT_FPSIMD_OFFSET, and is of type\r\n+ * struct user_fpsimd_state. Additional data might be appended in the\r\n+ * future: use SVE_PT_FPSIMD_SIZE(vq, flags) to compute the total size.\r\n+ * SVE_PT_FPSIMD_SIZE(vq, flags) will never be less than\r\n+ * sizeof(struct user_fpsimd_state).\r\n+ */\r\n+\r\n+#define SVE_PT_FPSIMD_OFFSET\t\tSVE_PT_REGS_OFFSET\r\n+\r\n+#define SVE_PT_FPSIMD_SIZE(vq, flags)\t(sizeof(struct user_fpsimd_state))\r\n+\r\n+/*\r\n+ * (flags & SVE_PT_REGS_MASK) == SVE_PT_REGS_SVE case:\r\n+ *\r\n+ * The payload starts at offset SVE_PT_SVE_OFFSET, and is of size\r\n+ * SVE_PT_SVE_SIZE(vq, flags).\r\n+ *\r\n+ * Additional macros describe the contents and layout of the payload.\r\n+ * For each, SVE_PT_SVE_x_OFFSET(args) is the start offset relative to\r\n+ * the start of struct user_sve_header, and SVE_PT_SVE_x_SIZE(args) is\r\n+ * the size in bytes:\r\n+ *\r\n+ *\tx\ttype\t\t\t\tdescription\r\n+ *\t-\t----\t\t\t\t-----------\r\n+ *\tZREGS\t\t\\\r\n+ *\tZREG\t\t|\r\n+ *\tPREGS\t\t| refer to \r\n+ *\tPREG\t\t|\r\n+ *\tFFR\t\t/\r\n+ *\r\n+ *\tFPSR\tuint32_t\t\t\tFPSR\r\n+ *\tFPCR\tuint32_t\t\t\tFPCR\r\n+ *\r\n+ * Additional data might be appended in the future.\r\n+ */\r\n+\r\n+#define SVE_PT_SVE_ZREG_SIZE(vq)\tSVE_SIG_ZREG_SIZE(vq)\r\n+#define SVE_PT_SVE_PREG_SIZE(vq)\tSVE_SIG_PREG_SIZE(vq)\r\n+#define SVE_PT_SVE_FFR_SIZE(vq)\t\tSVE_SIG_FFR_SIZE(vq)\r\n+#define SVE_PT_SVE_FPSR_SIZE\t\tsizeof(__u32)\r\n+#define SVE_PT_SVE_FPCR_SIZE\t\tsizeof(__u32)\r\n+\r\n+#define __SVE_SIG_TO_PT(offset) \\\r\n+\t((offset) - SVE_SIG_REGS_OFFSET + SVE_PT_REGS_OFFSET)\r\n+\r\n+#define SVE_PT_SVE_OFFSET\t\tSVE_PT_REGS_OFFSET\r\n+\r\n+#define SVE_PT_SVE_ZREGS_OFFSET \\\r\n+\t__SVE_SIG_TO_PT(SVE_SIG_ZREGS_OFFSET)\r\n+#define SVE_PT_SVE_ZREG_OFFSET(vq, n) \\\r\n+\t__SVE_SIG_TO_PT(SVE_SIG_ZREG_OFFSET(vq, n))\r\n+#define SVE_PT_SVE_ZREGS_SIZE(vq) \\\r\n+\t(SVE_PT_SVE_ZREG_OFFSET(vq, SVE_NUM_ZREGS) - SVE_PT_SVE_ZREGS_OFFSET)\r\n+\r\n+#define SVE_PT_SVE_PREGS_OFFSET(vq) \\\r\n+\t__SVE_SIG_TO_PT(SVE_SIG_PREGS_OFFSET(vq))\r\n+#define SVE_PT_SVE_PREG_OFFSET(vq, n) \\\r\n+\t__SVE_SIG_TO_PT(SVE_SIG_PREG_OFFSET(vq, n))\r\n+#define SVE_PT_SVE_PREGS_SIZE(vq) \\\r\n+\t(SVE_PT_SVE_PREG_OFFSET(vq, SVE_NUM_PREGS) - \\\r\n+\t\tSVE_PT_SVE_PREGS_OFFSET(vq))\r\n+\r\n+#define SVE_PT_SVE_FFR_OFFSET(vq) \\\r\n+\t__SVE_SIG_TO_PT(SVE_SIG_FFR_OFFSET(vq))\r\n+\r\n+#define SVE_PT_SVE_FPSR_OFFSET(vq)\t\t\t\t\\\r\n+\t((SVE_PT_SVE_FFR_OFFSET(vq) + SVE_PT_SVE_FFR_SIZE(vq) +\t\\\r\n+\t\t\t(SVE_VQ_BYTES - 1))\t\t\t\\\r\n+\t\t/ SVE_VQ_BYTES * SVE_VQ_BYTES)\r\n+#define SVE_PT_SVE_FPCR_OFFSET(vq) \\\r\n+\t(SVE_PT_SVE_FPSR_OFFSET(vq) + SVE_PT_SVE_FPSR_SIZE)\r\n+\r\n+/*\r\n+ * Any future extension appended after FPCR must be aligned to the next\r\n+ * 128-bit boundary.\r\n+ */\r\n+\r\n+#define SVE_PT_SVE_SIZE(vq, flags)\t\t\t\t\t\\\r\n+\t((SVE_PT_SVE_FPCR_OFFSET(vq) + SVE_PT_SVE_FPCR_SIZE\t\t\\\r\n+\t\t\t- SVE_PT_SVE_OFFSET + (SVE_VQ_BYTES - 1))\t\\\r\n+\t\t/ SVE_VQ_BYTES * SVE_VQ_BYTES)\r\n+\r\n+#define SVE_PT_SIZE(vq, flags)\t\t\t\t\t\t\\\r\n+\t (((flags) & SVE_PT_REGS_MASK) == SVE_PT_REGS_SVE ?\t\t\\\r\n+\t\t SVE_PT_SVE_OFFSET + SVE_PT_SVE_SIZE(vq, flags)\t\\\r\n+\t\t: SVE_PT_FPSIMD_OFFSET + SVE_PT_FPSIMD_SIZE(vq, flags))\r\n+\r\n #endif /* __ASSEMBLY__ */\r\n \r\n #endif /* _UAPI__ASM_PTRACE_H */\r\ndiff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c\r\nindex fff9fcf..361c019 100644\r\n--- a/arch/arm64/kernel/fpsimd.c\r\n+++ b/arch/arm64/kernel/fpsimd.c\r\n@@ -303,6 +303,37 @@ void sve_alloc(struct task_struct *task)\r\n \tBUG_ON(!task->thread.sve_state);\r\n }\r\n \r\n+void fpsimd_sync_to_sve(struct task_struct *task)\r\n+{\r\n+\tif (!test_tsk_thread_flag(task, TIF_SVE))\r\n+\t\tfpsimd_to_sve(task);\r\n+}\r\n+\r\n+void sve_sync_to_fpsimd(struct task_struct *task)\r\n+{\r\n+\tif (test_tsk_thread_flag(task, TIF_SVE))\r\n+\t\tsve_to_fpsimd(task);\r\n+}\r\n+\r\n+void sve_sync_from_fpsimd_zeropad(struct task_struct *task)\r\n+{\r\n+\tunsigned int vq;\r\n+\tvoid *sst = task->thread.sve_state;\r\n+\tstruct fpsimd_state const *fst = &task->thread.fpsimd_state;\r\n+\tunsigned int i;\r\n+\r\n+\tif (!test_tsk_thread_flag(task, TIF_SVE))\r\n+\t\treturn;\r\n+\r\n+\tvq = sve_vq_from_vl(task->thread.sve_vl);\r\n+\r\n+\tmemset(sst, 0, SVE_SIG_REGS_SIZE(vq));\r\n+\r\n+\tfor (i = 0; i < 32; ++i)\r\n+\t\tmemcpy(ZREG(sst, vq, i), &fst->vregs[i],\r\n+\t\t sizeof(fst->vregs[i]));\r\n+}\r\n+\r\n /*\r\n * Handle SVE state across fork():\r\n *\r\n@@ -459,10 +490,17 @@ static void __init sve_efi_setup(void)\r\n \t * This is evidence of a crippled system and we are returning void,\r\n \t * so no attempt is made to handle this situation here.\r\n \t */\r\n-\tBUG_ON(!sve_vl_valid(sve_max_vl));\r\n+\tif (!sve_vl_valid(sve_max_vl))\r\n+\t\tgoto fail;\r\n+\r\n \tefi_sve_state = __alloc_percpu(\r\n \t\tSVE_SIG_REGS_SIZE(sve_vq_from_vl(sve_max_vl)), SVE_VQ_BYTES);\r\n \tif (!efi_sve_state)\r\n+\t\tgoto fail;\r\n+\r\n+\treturn;\r\n+\r\n+fail:\r\n \t\tpanic(\"Cannot allocate percpu memory for EFI SVE save/restore\");\r\n }\r\n \r\ndiff --git a/arch/arm64/kernel/ptrace.c b/arch/arm64/kernel/ptrace.c\r\nindex 9cbb612..5ef4735b 100644\r\n--- a/arch/arm64/kernel/ptrace.c\r\n+++ b/arch/arm64/kernel/ptrace.c\r\n@@ -32,6 +32,7 @@\r\n #include \r\n #include \r\n #include \r\n+#include \r\n #include \r\n #include \r\n #include \r\n@@ -40,6 +41,7 @@\r\n #include \r\n \r\n #include \r\n+#include \r\n #include \r\n #include \r\n #include \r\n@@ -618,33 +620,66 @@ static int gpr_set(struct task_struct *target, const struct user_regset *regset,\r\n /*\r\n * TODO: update fp accessors for lazy context switching (sync/flush hwstate)\r\n */\r\n-static int fpr_get(struct task_struct *target, const struct user_regset *regset,\r\n-\t\t unsigned int pos, unsigned int count,\r\n-\t\t void *kbuf, void __user *ubuf)\r\n+static int __fpr_get(struct task_struct *target,\r\n+\t\t const struct user_regset *regset,\r\n+\t\t unsigned int pos, unsigned int count,\r\n+\t\t void *kbuf, void __user *ubuf, unsigned int start_pos)\r\n {\r\n \tstruct user_fpsimd_state *uregs;\r\n+\r\n+\tsve_sync_to_fpsimd(target);\r\n+\r\n \turegs = &target->thread.fpsimd_state.user_fpsimd;\r\n \r\n+\treturn user_regset_copyout(&pos, &count, &kbuf, &ubuf, uregs,\r\n+\t\t\t\t start_pos, start_pos + sizeof(*uregs));\r\n+}\r\n+\r\n+static int fpr_get(struct task_struct *target, const struct user_regset *regset,\r\n+\t\t unsigned int pos, unsigned int count,\r\n+\t\t void *kbuf, void __user *ubuf)\r\n+{\r\n \tif (target == current)\r\n \t\tfpsimd_preserve_current_state();\r\n \r\n-\treturn user_regset_copyout(&pos, &count, &kbuf, &ubuf, uregs, 0, -1);\r\n+\treturn __fpr_get(target, regset, pos, count, kbuf, ubuf, 0);\r\n }\r\n \r\n-static int fpr_set(struct task_struct *target, const struct user_regset *regset,\r\n-\t\t unsigned int pos, unsigned int count,\r\n-\t\t const void *kbuf, const void __user *ubuf)\r\n+static int __fpr_set(struct task_struct *target,\r\n+\t\t const struct user_regset *regset,\r\n+\t\t unsigned int pos, unsigned int count,\r\n+\t\t const void *kbuf, const void __user *ubuf,\r\n+\t\t unsigned int start_pos)\r\n {\r\n \tint ret;\r\n \tstruct user_fpsimd_state newstate =\r\n \t\ttarget->thread.fpsimd_state.user_fpsimd;\r\n \r\n-\tret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &newstate, 0, -1);\r\n+\tsve_sync_to_fpsimd(target);\r\n+\r\n+\tret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &newstate,\r\n+\t\t\t\t start_pos, start_pos + sizeof(newstate));\r\n \tif (ret)\r\n \t\treturn ret;\r\n \r\n \ttarget->thread.fpsimd_state.user_fpsimd = newstate;\r\n+\r\n+\treturn ret;\r\n+}\r\n+\r\n+static int fpr_set(struct task_struct *target, const struct user_regset *regset,\r\n+\t\t unsigned int pos, unsigned int count,\r\n+\t\t const void *kbuf, const void __user *ubuf)\r\n+{\r\n+\tint ret;\r\n+\r\n+\tret = __fpr_set(target, regset, pos, count, kbuf, ubuf, 0);\r\n+\tif (ret)\r\n+\t\treturn ret;\r\n+\r\n+\tsve_sync_from_fpsimd_zeropad(target);\r\n \tfpsimd_flush_task_state(target);\r\n+\r\n \treturn ret;\r\n }\r\n \r\n@@ -702,6 +737,210 @@ static int system_call_set(struct task_struct *target,\r\n \treturn ret;\r\n }\r\n \r\n+#ifdef CONFIG_ARM64_SVE\r\n+\r\n+static void sve_init_header_from_task(struct user_sve_header *header,\r\n+\t\t\t\t struct task_struct *target)\r\n+{\r\n+\tunsigned int vq;\r\n+\r\n+\tmemset(header, 0, sizeof(*header));\r\n+\r\n+\theader->flags = test_tsk_thread_flag(target, TIF_SVE) ?\r\n+\t\tSVE_PT_REGS_SVE : SVE_PT_REGS_FPSIMD;\r\n+\tif (test_tsk_thread_flag(target, TIF_SVE_VL_INHERIT))\r\n+\t\theader->flags |= SVE_PT_VL_INHERIT;\r\n+\r\n+\theader->vl = target->thread.sve_vl;\r\n+\tvq = sve_vq_from_vl(header->vl);\r\n+\r\n+\tif (WARN_ON(!sve_vl_valid(sve_max_vl)))\r\n+\t\theader->max_vl = header->vl;\r\n+\r\n+\theader->size = SVE_PT_SIZE(vq, header->flags);\r\n+\theader->max_size = SVE_PT_SIZE(sve_vq_from_vl(header->max_vl),\r\n+\t\t\t\t SVE_PT_REGS_SVE);\r\n+}\r\n+\r\n+static unsigned int sve_size_from_header(struct user_sve_header const *header)\r\n+{\r\n+\treturn ALIGN(header->size, SVE_VQ_BYTES);\r\n+}\r\n+\r\n+static unsigned int sve_get_size(struct task_struct *target,\r\n+\t\t\t\t const struct user_regset *regset)\r\n+{\r\n+\tstruct user_sve_header header;\r\n+\r\n+\tif (!system_supports_sve())\r\n+\t\treturn 0;\r\n+\r\n+\tsve_init_header_from_task(&header, target);\r\n+\treturn sve_size_from_header(&header);\r\n+}\r\n+\r\n+static int sve_get(struct task_struct *target,\r\n+\t\t const struct user_regset *regset,\r\n+\t\t unsigned int pos, unsigned int count,\r\n+\t\t void *kbuf, void __user *ubuf)\r\n+{\r\n+\tint ret;\r\n+\tstruct user_sve_header header;\r\n+\tunsigned int vq;\r\n+\tunsigned long start, end;\r\n+\r\n+\tif (!system_supports_sve())\r\n+\t\treturn -EINVAL;\r\n+\r\n+\t/* Header */\r\n+\tsve_init_header_from_task(&header, target);\r\n+\tvq = sve_vq_from_vl(header.vl);\r\n+\r\n+\tret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &header,\r\n+\t\t\t\t 0, sizeof(header));\r\n+\tif (ret)\r\n+\t\treturn ret;\r\n+\r\n+\tif (target == current)\r\n+\t\tfpsimd_preserve_current_state();\r\n+\r\n+\t/* Registers: FPSIMD-only case */\r\n+\r\n+\tBUILD_BUG_ON(SVE_PT_FPSIMD_OFFSET != sizeof(header));\r\n+\tif ((header.flags & SVE_PT_REGS_MASK) == SVE_PT_REGS_FPSIMD)\r\n+\t\treturn __fpr_get(target, regset, pos, count, kbuf, ubuf,\r\n+\t\t\t\t SVE_PT_FPSIMD_OFFSET);\r\n+\r\n+\t/* Otherwise: full SVE case */\r\n+\r\n+\tBUILD_BUG_ON(SVE_PT_SVE_OFFSET != sizeof(header));\r\n+\tstart = SVE_PT_SVE_OFFSET;\r\n+\tend = SVE_PT_SVE_FFR_OFFSET(vq) + SVE_PT_SVE_FFR_SIZE(vq);\r\n+\tret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,\r\n+\t\t\t\t target->thread.sve_state,\r\n+\t\t\t\t start, end);\r\n+\tif (ret)\r\n+\t\treturn ret;\r\n+\r\n+\tstart = end;\r\n+\tend = SVE_PT_SVE_FPSR_OFFSET(vq);\r\n+\tret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,\r\n+\t\t\t\t start, end);\r\n+\tif (ret)\r\n+\t\treturn ret;\r\n+\r\n+\t/*\r\n+\t * Copy fpsr, and fpcr which must follow contiguously in\r\n+\t * struct fpsimd_state:\r\n+\t */\r\n+\tstart = end;\r\n+\tend = SVE_PT_SVE_FPCR_OFFSET(vq) + SVE_PT_SVE_FPCR_SIZE;\r\n+\tret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,\r\n+\t\t\t\t &target->thread.fpsimd_state.fpsr,\r\n+\t\t\t\t start, end);\r\n+\tif (ret)\r\n+\t\treturn ret;\r\n+\r\n+\tstart = end;\r\n+\tend = sve_size_from_header(&header);\r\n+\treturn user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,\r\n+\t\t\t\t\tstart, end);\r\n+}\r\n+\r\n+static int sve_set(struct task_struct *target,\r\n+\t\t const struct user_regset *regset,\r\n+\t\t unsigned int pos, unsigned int count,\r\n+\t\t const void *kbuf, const void __user *ubuf)\r\n+{\r\n+\tint ret;\r\n+\tstruct user_sve_header header;\r\n+\tunsigned int vq;\r\n+\tunsigned long start, end;\r\n+\r\n+\tif (!system_supports_sve())\r\n+\t\treturn -EINVAL;\r\n+\r\n+\t/* Header */\r\n+\tif (count < sizeof(header))\r\n+\t\treturn -EINVAL;\r\n+\tret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &header,\r\n+\t\t\t\t 0, sizeof(header));\r\n+\tif (ret)\r\n+\t\tgoto out;\r\n+\r\n+\t/*\r\n+\t * Apart from PT_SVE_REGS_MASK, all PT_SVE_* flags are consumed by\r\n+\t * sve_set_vector_length(), which will also validate them for us:\r\n+\t */\r\n+\tret = sve_set_vector_length(target, header.vl,\r\n+\t\t\t\t header.flags & ~SVE_PT_REGS_MASK);\r\n+\tif (ret)\r\n+\t\tgoto out;\r\n+\r\n+\t/* Actual VL set may be less than the user asked for: */\r\n+\tvq = sve_vq_from_vl(target->thread.sve_vl);\r\n+\r\n+\t/* Registers: FPSIMD-only case */\r\n+\r\n+\tBUILD_BUG_ON(SVE_PT_FPSIMD_OFFSET != sizeof(header));\r\n+\tif ((header.flags & SVE_PT_REGS_MASK) == SVE_PT_REGS_FPSIMD) {\r\n+\t\tsve_sync_to_fpsimd(target);\r\n+\r\n+\t\tret = __fpr_set(target, regset, pos, count, kbuf, ubuf,\r\n+\t\t\t\tSVE_PT_FPSIMD_OFFSET);\r\n+\t\tclear_tsk_thread_flag(target, TIF_SVE);\r\n+\t\tgoto out;\r\n+\t}\r\n+\r\n+\t/* Otherwise: full SVE case */\r\n+\r\n+\t/*\r\n+\t * If setting a different VL from the requested VL and there is\r\n+\t * register data, the data layout will be wrong: don't even\r\n+\t * try to set the registers in this case.\r\n+\t */\r\n+\tif (count && vq != sve_vq_from_vl(header.vl)) {\r\n+\t\tret = -EIO;\r\n+\t\tgoto out;\r\n+\t}\r\n+\r\n+\tsve_alloc(target);\r\n+\tfpsimd_sync_to_sve(target);\r\n+\tset_tsk_thread_flag(target, TIF_SVE);\r\n+\r\n+\tBUILD_BUG_ON(SVE_PT_SVE_OFFSET != sizeof(header));\r\n+\tstart = SVE_PT_SVE_OFFSET;\r\n+\tend = SVE_PT_SVE_FFR_OFFSET(vq) + SVE_PT_SVE_FFR_SIZE(vq);\r\n+\tret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,\r\n+\t\t\t\t target->thread.sve_state,\r\n+\t\t\t\t start, end);\r\n+\tif (ret)\r\n+\t\tgoto out;\r\n+\r\n+\tstart = end;\r\n+\tend = SVE_PT_SVE_FPSR_OFFSET(vq);\r\n+\tret = user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf,\r\n+\t\t\t\t\tstart, end);\r\n+\tif (ret)\r\n+\t\tgoto out;\r\n+\r\n+\t/*\r\n+\t * Copy fpsr, and fpcr which must follow contiguously in\r\n+\t * struct fpsimd_state:\r\n+\t */\r\n+\tstart = end;\r\n+\tend = SVE_PT_SVE_FPCR_OFFSET(vq) + SVE_PT_SVE_FPCR_SIZE;\r\n+\tret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,\r\n+\t\t\t\t &target->thread.fpsimd_state.fpsr,\r\n+\t\t\t\t start, end);\r\n+\r\n+out:\r\n+\tfpsimd_flush_task_state(target);\r\n+\treturn ret;\r\n+}\r\n+\r\n+#endif /* CONFIG_ARM64_SVE */\r\n+\r\n enum aarch64_regset {\r\n \tREGSET_GPR,\r\n \tREGSET_FPR,\r\n@@ -711,6 +950,9 @@ enum aarch64_regset {\r\n \tREGSET_HW_WATCH,\r\n #endif\r\n \tREGSET_SYSTEM_CALL,\r\n+#ifdef CONFIG_ARM64_SVE\r\n+\tREGSET_SVE,\r\n+#endif\r\n };\r\n \r\n static const struct user_regset aarch64_regsets[] = {\r\n@@ -768,6 +1010,18 @@ static const struct user_regset aarch64_regsets[] = {\r\n \t\t.get = system_call_get,\r\n \t\t.set = system_call_set,\r\n \t},\r\n+#ifdef CONFIG_ARM64_SVE\r\n+\t[REGSET_SVE] = { /* Scalable Vector Extension */\r\n+\t\t.core_note_type = NT_ARM_SVE,\r\n+\t\t.n = DIV_ROUND_UP(SVE_PT_SIZE(SVE_VQ_MAX, SVE_PT_REGS_SVE),\r\n+\t\t\t\t SVE_VQ_BYTES),\r\n+\t\t.size = SVE_VQ_BYTES,\r\n+\t\t.align = SVE_VQ_BYTES,\r\n+\t\t.get = sve_get,\r\n+\t\t.set = sve_set,\r\n+\t\t.get_size = sve_get_size,\r\n+\t},\r\n+#endif\r\n };\r\n \r\n static const struct user_regset_view user_aarch64_view = {\r\ndiff --git a/include/uapi/linux/elf.h b/include/uapi/linux/elf.h\r\nindex b5280db..735b8f4 100644\r\n--- a/include/uapi/linux/elf.h\r\n+++ b/include/uapi/linux/elf.h\r\n@@ -416,6 +416,7 @@ typedef struct elf64_shdr {\r\n #define NT_ARM_HW_BREAK\t0x402\t\t/* ARM hardware breakpoint registers */\r\n #define NT_ARM_HW_WATCH\t0x403\t\t/* ARM hardware watchpoint registers */\r\n #define NT_ARM_SYSTEM_CALL\t0x404\t/* ARM system call number */\r\n+#define NT_ARM_SVE\t0x405\t\t/* ARM Scalable Vector Extension registers */\r\n #define NT_METAG_CBUF\t0x500\t\t/* Metag catch buffer registers */\r\n #define NT_METAG_RPIPE\t0x501\t\t/* Metag read pipeline state */\r\n #define NT_METAG_TLS\t0x502\t\t/* Metag TLS pointer */\r\n-- \r\n2.1.4","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"fSZ9lyHN\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xnTQB3k7lz9s7F\n\tfor ;\n\tThu, 7 Sep 2017 02:22:39 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp 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by\n\tg01jpexchkw17 ([10.0.194.56]) with mapi id 14.03.0352.000;\n\tThu, 7 Sep 2017 01:21:50 +0900"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:MIME-Version:In-Reply-To:References:\n\tMessage-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=yvzD1ZbUvqUYdWftQ8ez8Iu4oMrQkllrI/t/j/QVbiw=;\n\tb=fSZ9lyHNliOxJq\n\tK07eFF9+l718SyOo2HeZg2QQ/gAcBKVosVRJR64D8vbZMxf3ByAhNSJSqF67i2o+YjuqMGSwFJtsN\n\tnpoxMePq8otj5ID+FuxIk0b5TKay29RSD9esfyqHLThgEaRlvkdy0qCg7a5hBtrvu4KhpKj7ErxYs\n\t5Lsn/3ffyl1da40qxXVrd70DVDtmqg1VtHzk2mSSG5OC7kcYwTJe7WHq5d3JJUPNa+yzgapYYvLJz\n\tKRX3XWtTPR/McsyIYnu6kmCZg5qrdAoypXlZoHh91FaRZk1G7/tMTefhfM7m82gUkkkhkDBA8WvU2\n\tSBVjwjkOUaE3qpkX2jcQ==;","From":"\"Okamoto, Takayuki\" ","To":"'Dave Martin' ,\n\t\"linux-arm-kernel@lists.infradead.org\"\n\t","Subject":"RE: [PATCH v2 19/28] arm64/sve: ptrace and ELF coredump support","Thread-Topic":"[PATCH v2 19/28] arm64/sve: ptrace and ELF coredump support","Thread-Index":"AQHTIn0iPyv6mgoawEiV8zGiJ7XUo6KoEjMw","Date":"Wed, 6 Sep 2017 16:21:50 +0000","Message-ID":"<5FA513F682BE7F4EAAB8EE035D5B08E44109DFE8@G01JPEXMBKW02>","References":"<1504198860-12951-1-git-send-email-Dave.Martin@arm.com>\n\t<1504198860-12951-20-git-send-email-Dave.Martin@arm.com>","In-Reply-To":"<1504198860-12951-20-git-send-email-Dave.Martin@arm.com>","Accept-Language":"ja-JP, en-US","Content-Language":"ja-JP","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","x-securitypolicycheck":"OK by SHieldMailChecker v2.4.6","x-shieldmailcheckerpolicyversion":"FJ-ISEC-20160315","x-shieldmailcheckermailid":"4d1366ccb9ed4978b85333ddc83656de","x-originating-ip":"[10.18.70.173]","MIME-Version":"1.0","X-SecurityPolicyCheck-GC":"OK by FENCE-Mail","X-TM-AS-MML":"disable","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170906_092224_291573_78BD56FE ","X-CRM114-Status":"GOOD ( 20.67 )","X-Spam-Score":"-4.2 (----)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-4.2 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/,\n\tmedium trust [202.219.69.169 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"\"linux-arch@vger.kernel.org\" ,\n\t\"libc-alpha@sourceware.org\" , \n\t\"gdb@sourceware.org\" , Ard Biesheuvel\n\t, Szabolcs Nagy ,\n\tCatalin Marinas , Yao Qi , \n\tAlan Hayward , Will Deacon , \n\tOleg Nesterov\n\t, Alexander Viro , Richard\n\tSandiford , =?utf-8?q?Alex_Benn=C3=A9e?=\n\t, \"kvmarm@lists.cs.columbia.edu\"\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1764302,"web_url":"http://patchwork.ozlabs.org/comment/1764302/","msgid":"<20170906181634.GF6321@e103592.cambridge.arm.com>","list_archive_url":null,"date":"2017-09-06T18:16:35","subject":"Re: [PATCH v2 19/28] arm64/sve: ptrace and ELF coredump support","submitter":{"id":26612,"url":"http://patchwork.ozlabs.org/api/people/26612/","name":"Dave Martin","email":"Dave.Martin@arm.com"},"content":"On Wed, Sep 06, 2017 at 04:21:50PM +0000, Okamoto, Takayuki wrote:\n> Hi Dave,\n> \n> I am an engineer of the postK computer from Fujitsu.\n> \n> When I tried to read \"max_vl\" by ptrace with this patch on our local SVE \n> simulator, it was read as zero.\n> I think the cause of this incident is that \"max_vl\" is set as \"header->vl\" \n> only on warning case in sve_init_header_from_task().\n> \"max_vl\" should be set up also on normal case, like the following patch.\n> \n> \n> --- a/arch/arm64/kernel/ptrace.c\n> +++ b/arch/arm64/kernel/ptrace.c\n> @@ -755,6 +755,8 @@ static void sve_init_header_from_task(struct user_sve_header *header,\n> \n> if (WARN_ON(!sve_vl_valid(sve_max_vl)))\n> header->max_vl = header->vl;\n> + else\n> + header->max_vl = sve_max_vl;\n> \n> header->size = SVE_PT_SIZE(vq, header->flags);\n> header->max_size = SVE_PT_SIZE(sve_vq_from_vl(header->max_vl),\n\nHi, thanks for reporting this.\n\nIt looks like a refactoring mistake I made while removing BUG_ON()s,\nwhich I missed in my testing.\n\nYour fix looks correct and seems to work. For stylistic reasons, I may\nwrite it like this instead, but the effect should be the same:\n\n\theader->max_vl = sve_max_vl;\n\tif (WARN_ON(!sve_vl_valid(sve_max_vl))\n\t\theader->max_vl = header->vl;\n\nCheers\n---Dave\n\n> \n> \n> Best regards,\n> Takayuki Okamoto\n> \n> -----Original Message-----\n> From: gdb-owner@sourceware.org [mailto:gdb-owner@sourceware.org] On Behalf Of Dave Martin\n> Sent: Friday, September 1, 2017 2:01 AM\n> To: linux-arm-kernel@lists.infradead.org\n> Cc: Catalin Marinas ; Will Deacon ; Ard Biesheuvel ; Alex Bennée ; Szabolcs Nagy ; Richard Sandiford ; kvmarm@lists.cs.columbia.edu; libc-alpha@sourceware.org; linux-arch@vger.kernel.org; gdb@sourceware.org; Alan Hayward ; Yao Qi ; Oleg Nesterov ; Alexander Viro \n> Subject: [PATCH v2 19/28] arm64/sve: ptrace and ELF coredump support\n> \n\n[...]\n\n> @@ -702,6 +737,210 @@ static int system_call_set(struct task_struct *target,\n> \treturn ret;\n> }\n> \n> +#ifdef CONFIG_ARM64_SVE\n> +\n> +static void sve_init_header_from_task(struct user_sve_header *header,\n> +\t\t\t\t struct task_struct *target)\n> +{\n> +\tunsigned int vq;\n> +\n> +\tmemset(header, 0, sizeof(*header));\n> +\n> +\theader->flags = test_tsk_thread_flag(target, TIF_SVE) ?\n> +\t\tSVE_PT_REGS_SVE : SVE_PT_REGS_FPSIMD;\n> +\tif (test_tsk_thread_flag(target, TIF_SVE_VL_INHERIT))\n> +\t\theader->flags |= SVE_PT_VL_INHERIT;\n> +\n> +\theader->vl = target->thread.sve_vl;\n> +\tvq = sve_vq_from_vl(header->vl);\n> +\n> +\tif (WARN_ON(!sve_vl_valid(sve_max_vl)))\n> +\t\theader->max_vl = header->vl;\n> +\n> +\theader->size = SVE_PT_SIZE(vq, header->flags);\n> +\theader->max_size = SVE_PT_SIZE(sve_vq_from_vl(header->max_vl),\n> +\t\t\t\t SVE_PT_REGS_SVE);\n> +}\n\n[...]","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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Wed, 6 Sep 2017 11:16:38 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:\n\tMessage-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=rknrFo8mkIISuNBCnD/wEtgUfMdkKDOShoN2dejMOCc=;\n\tb=R7f9CGf1UThWgn\n\teVV7eFHrKNCq2zA4khCbg9Yny/y5TFGjEsFL/Evj4oM890KUn2t+yTwh0hu9FkWIT/vVJoFIu+KsK\n\tbkw+rrCoKvVYAkkcKytVOkRRzr45NX+KWBTRxViyQcmPNFfg9D8u+hPRWtdtyd1vaMuCL7GeU+CbP\n\tpHZy3GkyHIX79FTZg2nWnlBwnyelq6tGUO7AuPdXN/P1Tp/jrwZaxN07mFQIHQ6GIVn4fc1Iwlen0\n\t58Rfb6Pz6/cmnbLCzUo0KNpmrnApK8df5F5TAHi9zRxi8l5UO1QVcRsFWKlhFlQ7sBs/9cUi1iOXg\n\t2GLAImMNbYTTTeG+kbJg==;","Date":"Wed, 6 Sep 2017 19:16:35 +0100","From":"Dave Martin ","To":"\"Okamoto, Takayuki\" ","Subject":"Re: [PATCH v2 19/28] arm64/sve: ptrace and ELF coredump support","Message-ID":"<20170906181634.GF6321@e103592.cambridge.arm.com>","References":"<1504198860-12951-1-git-send-email-Dave.Martin@arm.com>\n\t<1504198860-12951-20-git-send-email-Dave.Martin@arm.com>\n\t<5FA513F682BE7F4EAAB8EE035D5B08E44109DFE8@G01JPEXMBKW02>","MIME-Version":"1.0","Content-Disposition":"inline","In-Reply-To":"<5FA513F682BE7F4EAAB8EE035D5B08E44109DFE8@G01JPEXMBKW02>","User-Agent":"Mutt/1.5.23 (2014-03-12)","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170906_111703_559935_61159D1F ","X-CRM114-Status":"GOOD ( 16.43 )","X-Spam-Score":"-6.9 (------)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-6.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/,\n\thigh trust [217.140.101.70 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"\"linux-arch@vger.kernel.org\" ,\n\t\"libc-alpha@sourceware.org\" , Ard Biesheuvel\n\t, Szabolcs Nagy ,\n\t\"gdb@sourceware.org\" , Yao Qi , \n\tAlan Hayward , Will Deacon , \n\tOleg Nesterov ,\n\tRichard Sandiford , Alexander Viro\n\t, Catalin Marinas ,\n\tAlex =?iso-8859-1?q?Benn=E9e?= ,\n\t\"kvmarm@lists.cs.columbia.edu\" , \n\t\"linux-arm-kernel@lists.infradead.org\"\n\t","Content-Type":"text/plain; charset=\"iso-8859-1\"","Content-Transfer-Encoding":"quoted-printable","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1764506,"web_url":"http://patchwork.ozlabs.org/comment/1764506/","msgid":"<5FA513F682BE7F4EAAB8EE035D5B08E44109EBDF@G01JPEXMBKW02>","list_archive_url":null,"date":"2017-09-07T05:11:45","subject":"RE: [PATCH v2 19/28] arm64/sve: ptrace and ELF coredump support","submitter":{"id":72310,"url":"http://patchwork.ozlabs.org/api/people/72310/","name":"Okamoto, Takayuki","email":"tokamoto@jp.fujitsu.com"},"content":"Hi Dave,\r\n\r\nThank you for your reply.\r\n\r\n> Your fix looks correct and seems to work. For stylistic reasons, I may\r\n> write it like this instead, but the effect should be the same:\r\n> \r\n> \theader->max_vl = sve_max_vl;\r\n> \tif (WARN_ON(!sve_vl_valid(sve_max_vl))\r\n> \t\theader->max_vl = header->vl;\r\n\r\nIt is better than my fix.\r\nPlease, apply it at next version.\r\n\r\nBest regards,\r\nTakayuki Okamoto\r\n\r\n> -----Original Message-----\r\n> From: linux-arm-kernel\r\n> [mailto:linux-arm-kernel-bounces@lists.infradead.org] On Behalf Of Dave\r\n> Martin\r\n> Sent: Thursday, September 7, 2017 3:17 AM\r\n> To: Okamoto, Takayuki \r\n> Cc: linux-arch@vger.kernel.org; libc-alpha@sourceware.org; Ard\r\n> Biesheuvel ; Szabolcs Nagy\r\n> ; gdb@sourceware.org; Yao Qi ;\r\n> Alan Hayward ; Will Deacon ;\r\n> Oleg Nesterov ; Richard Sandiford\r\n> ; Alexander Viro ;\r\n> Catalin Marinas ; Alex Bennée\r\n> ; kvmarm@lists.cs.columbia.edu;\r\n> linux-arm-kernel@lists.infradead.org\r\n> Subject: Re: [PATCH v2 19/28] arm64/sve: ptrace and ELF coredump support\r\n> \r\n> On Wed, Sep 06, 2017 at 04:21:50PM +0000, Okamoto, Takayuki wrote:\r\n> > Hi Dave,\r\n> >\r\n> > I am an engineer of the postK computer from Fujitsu.\r\n> >\r\n> > When I tried to read \"max_vl\" by ptrace with this patch on our local SVE\r\n> > simulator, it was read as zero.\r\n> > I think the cause of this incident is that \"max_vl\" is set as \"header->vl\"\r\n> > only on warning case in sve_init_header_from_task().\r\n> > \"max_vl\" should be set up also on normal case, like the following patch.\r\n> >\r\n> >\r\n> > --- a/arch/arm64/kernel/ptrace.c\r\n> > +++ b/arch/arm64/kernel/ptrace.c\r\n> > @@ -755,6 +755,8 @@ static void sve_init_header_from_task(struct\r\n> user_sve_header *header,\r\n> >\r\n> > if (WARN_ON(!sve_vl_valid(sve_max_vl)))\r\n> > header->max_vl = header->vl;\r\n> > + else\r\n> > + header->max_vl = sve_max_vl;\r\n> >\r\n> > header->size = SVE_PT_SIZE(vq, header->flags);\r\n> > header->max_size =\r\n> SVE_PT_SIZE(sve_vq_from_vl(header->max_vl),\r\n> \r\n> Hi, thanks for reporting this.\r\n> \r\n> It looks like a refactoring mistake I made while removing BUG_ON()s,\r\n> which I missed in my testing.\r\n> \r\n> Your fix looks correct and seems to work. For stylistic reasons, I may\r\n> write it like this instead, but the effect should be the same:\r\n> \r\n> \theader->max_vl = sve_max_vl;\r\n> \tif (WARN_ON(!sve_vl_valid(sve_max_vl))\r\n> \t\theader->max_vl = header->vl;\r\n> \r\n> Cheers\r\n> ---Dave\r\n> \r\n> >\r\n> >\r\n> > Best regards,\r\n> > Takayuki Okamoto\r\n> >\r\n> > -----Original Message-----\r\n> > From: gdb-owner@sourceware.org [mailto:gdb-owner@sourceware.org] On\r\n> Behalf Of Dave Martin\r\n> > Sent: Friday, September 1, 2017 2:01 AM\r\n> > To: linux-arm-kernel@lists.infradead.org\r\n> > Cc: Catalin Marinas ; Will Deacon\r\n> ; Ard Biesheuvel ; Alex\r\n> Bennée ; Szabolcs Nagy ;\r\n> Richard Sandiford ;\r\n> kvmarm@lists.cs.columbia.edu; libc-alpha@sourceware.org;\r\n> linux-arch@vger.kernel.org; gdb@sourceware.org; Alan Hayward\r\n> ; Yao Qi ; Oleg Nesterov\r\n> ; Alexander Viro \r\n> > Subject: [PATCH v2 19/28] arm64/sve: ptrace and ELF coredump support\r\n> >\r\n> \r\n> [...]\r\n> \r\n> > @@ -702,6 +737,210 @@ static int system_call_set(struct task_struct\r\n> *target,\r\n> > \treturn ret;\r\n> > }\r\n> >\r\n> > +#ifdef CONFIG_ARM64_SVE\r\n> > +\r\n> > +static void sve_init_header_from_task(struct user_sve_header *header,\r\n> > +\t\t\t\t struct task_struct *target)\r\n> > +{\r\n> > +\tunsigned int vq;\r\n> > +\r\n> > +\tmemset(header, 0, sizeof(*header));\r\n> > +\r\n> > +\theader->flags = test_tsk_thread_flag(target, TIF_SVE) ?\r\n> > +\t\tSVE_PT_REGS_SVE : SVE_PT_REGS_FPSIMD;\r\n> > +\tif (test_tsk_thread_flag(target, TIF_SVE_VL_INHERIT))\r\n> > +\t\theader->flags |= SVE_PT_VL_INHERIT;\r\n> > +\r\n> > +\theader->vl = target->thread.sve_vl;\r\n> > +\tvq = sve_vq_from_vl(header->vl);\r\n> > +\r\n> > +\tif (WARN_ON(!sve_vl_valid(sve_max_vl)))\r\n> > +\t\theader->max_vl = header->vl;\r\n> > +\r\n> > +\theader->size = SVE_PT_SIZE(vq, header->flags);\r\n> > +\theader->max_size = SVE_PT_SIZE(sve_vq_from_vl(header->max_vl),\r\n> > +\t\t\t\t SVE_PT_REGS_SVE);\r\n> > +}\r\n> \r\n> [...]\r\n> \r\n> _______________________________________________\r\n> linux-arm-kernel mailing list\r\n> linux-arm-kernel@lists.infradead.org\r\n> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"cxLbZmyR\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xnpVH0hbKz9s8J\n\tfor ;\n\tThu, 7 Sep 2017 15:12:23 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dpp6v-0002ID-Vz; Thu, 07 Sep 2017 05:12:18 +0000","from mgwkm01.jp.fujitsu.com ([202.219.69.168])\n\tby bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dpp6q-0002AU-Fx for linux-arm-kernel@lists.infradead.org;\n\tThu, 07 Sep 2017 05:12:15 +0000","from kw-mxoi2.gw.nic.fujitsu.com (unknown [192.168.231.133]) by\n\tmgwkm01.jp.fujitsu.com with smtp\n\tid 11e6_b6e3_0fd4a8d4_ed1a_4d1b_b9ca_91c468d85215;\n\tThu, 07 Sep 2017 14:11:48 +0900","from g01jpfmpwkw02.exch.g01.fujitsu.local\n\t(g01jpfmpwkw02.exch.g01.fujitsu.local [10.0.193.56])\n\tby kw-mxoi2.gw.nic.fujitsu.com (Postfix) with ESMTP id 3DBBFAC008E\n\tfor ;\n\tThu, 7 Sep 2017 14:11:48 +0900 (JST)","from G01JPEXCHKW18.g01.fujitsu.local\n\t(G01JPEXCHKW18.g01.fujitsu.local [10.0.194.57])\n\tby g01jpfmpwkw02.exch.g01.fujitsu.local (Postfix) with ESMTP id\n\tA811B328477; Thu, 7 Sep 2017 14:11:46 +0900 (JST)","from G01JPEXMBKW02.g01.fujitsu.local ([10.0.194.66]) by\n\tg01jpexchkw18 ([10.0.194.57]) with mapi id 14.03.0352.000;\n\tThu, 7 Sep 2017 14:11:47 +0900"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:MIME-Version:In-Reply-To:References:\n\tMessage-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=aog+gBsIbxooOGXny8Ck9hkgavQlSVBoWECnhN6bhYs=;\n\tb=cxLbZmyR/bvVuf\n\tlFPNAfv89DyjIC4A+VWNYUr8CLVGuLXgyQwipvCr8X8KgNUxqfUBPkuI5dEbqVV8sD8xfEqTs9Yrq\n\tbEW74b0Obou8S5m5528G4QTHHSaFZHFt3Fsl+/ErAIO6rgdDNWg/T8SyZhXMcFJ8UMmPpcVLXDEvu\n\thulR/FSJcctpaNGPmZDK9uiZQgNkdE6SETfWulaDzEYcUJGMptS05kTTQQu6lsxIl3TC/gtJVjhHQ\n\t43Ec8cXF2CoU59XZfjWNf3yIkkZhuubOfZ0ayIpANt7ANw1Ia/qvAI6A4ldRQaURw8SZ0ISlQIMh6\n\tbtTBEgYdaWBDyUbt+T6A==;","From":"\"Okamoto, Takayuki\" ","To":"'Dave Martin' ","Subject":"RE: [PATCH v2 19/28] arm64/sve: ptrace and ELF coredump support","Thread-Topic":"[PATCH v2 19/28] arm64/sve: ptrace and ELF coredump support","Thread-Index":"AQHTIn0iPyv6mgoawEiV8zGiJ7XUo6KoEjMw//+KfoCAAUm8sA==","Date":"Thu, 7 Sep 2017 05:11:45 +0000","Message-ID":"<5FA513F682BE7F4EAAB8EE035D5B08E44109EBDF@G01JPEXMBKW02>","References":"<1504198860-12951-1-git-send-email-Dave.Martin@arm.com>\n\t<1504198860-12951-20-git-send-email-Dave.Martin@arm.com>\n\t<5FA513F682BE7F4EAAB8EE035D5B08E44109DFE8@G01JPEXMBKW02>\n\t<20170906181634.GF6321@e103592.cambridge.arm.com>","In-Reply-To":"<20170906181634.GF6321@e103592.cambridge.arm.com>","Accept-Language":"ja-JP, en-US","Content-Language":"ja-JP","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","x-securitypolicycheck":"OK by SHieldMailChecker v2.4.6","x-shieldmailcheckerpolicyversion":"FJ-ISEC-20160315","x-shieldmailcheckermailid":"a96d12fce9af45d0a94000d6f54939cb","x-originating-ip":"[10.18.70.173]","MIME-Version":"1.0","X-SecurityPolicyCheck-GC":"OK by FENCE-Mail","X-TM-AS-MML":"disable","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170906_221212_964900_BED15F96 ","X-CRM114-Status":"GOOD ( 21.46 )","X-Spam-Score":"-4.2 (----)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-4.2 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/,\n\tmedium trust [202.219.69.168 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"\"linux-arch@vger.kernel.org\" ,\n\t\"libc-alpha@sourceware.org\" , Ard Biesheuvel\n\t, Szabolcs Nagy ,\n\t\"gdb@sourceware.org\" , Yao Qi , \n\tWill Deacon , Oleg Nesterov , \n\t=?gb2312?b?QWxleCBCZW5uqKZl?= ,\n\tRichard Sandiford , Alexander Viro\n\t, Alan Hayward ,\n\tCatalin Marinas , \n\t\"kvmarm@lists.cs.columbia.edu\" ,\n\t\"linux-arm-kernel@lists.infradead.org\"\n\t","Content-Type":"text/plain; charset=\"gb2312\"","Content-Transfer-Encoding":"base64","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1765339,"web_url":"http://patchwork.ozlabs.org/comment/1765339/","msgid":"<20170908131136.GG6321@e103592.cambridge.arm.com>","list_archive_url":null,"date":"2017-09-08T13:11:40","subject":"Re: [PATCH v2 19/28] arm64/sve: ptrace and ELF coredump support","submitter":{"id":26612,"url":"http://patchwork.ozlabs.org/api/people/26612/","name":"Dave Martin","email":"Dave.Martin@arm.com"},"content":"On Thu, Sep 07, 2017 at 05:11:45AM +0000, Okamoto, Takayuki wrote:\n> Hi Dave,\n> \n> Thank you for your reply.\n> \n> > Your fix looks correct and seems to work. For stylistic reasons, I may\n> > write it like this instead, but the effect should be the same:\n> > \n> > \theader->max_vl = sve_max_vl;\n> > \tif (WARN_ON(!sve_vl_valid(sve_max_vl))\n> > \t\theader->max_vl = header->vl;\n> \n> It is better than my fix.\n> Please, apply it at next version.\n\nI've rebased to v4.13 and pushed a branch to track fixes against v2,\nhere:\n\n * http://linux-arm.org/git?p=linux-dm.git;a=shortlog;h=refs/heads/sve/v2%2Bfixes\n\n * git://linux-arm.org/linux-dm.git sve/v2+fixes\n\nCheers\n---Dave","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"hKxDaman\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xpd5V6SVpz9ryk\n\tfor ;\n\tFri, 8 Sep 2017 23:12:14 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dqJ4t-0001bt-8t; Fri, 08 Sep 2017 13:12:11 +0000","from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]\n\thelo=foss.arm.com)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dqJ4p-0001Lg-Jd for linux-arm-kernel@lists.infradead.org;\n\tFri, 08 Sep 2017 13:12:09 +0000","from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249])\n\tby usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C16CD13D5;\n\tFri, 8 Sep 2017 06:11:45 -0700 (PDT)","from e103592.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com\n\t[10.72.51.249])\n\tby usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id\n\t1D1203F578; Fri, 8 Sep 2017 06:11:42 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:\n\tMessage-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=M+uN1EpCJ/Klz23VcIxJ+Tqt1RceCBPqjc/ls3GID28=;\n\tb=hKxDamanl4qKJH\n\to2nshpfGhdeuLkJ0xDs8axGoM4KmE3mhwLWbBED4e0OgAXLSbHK0/n3c6u28Ius2xmzolDiLC8Jwk\n\tfU+Vi0OZRSrklF1ysmqc02cqPWdTW/fsOpKrW+TROf+4l9Vq38j5+6s6C4WLKapgBvt1i8f+bKJ4n\n\tiIV8I6Wurmpm90IvStl3TmIWhfwlnCA5M5bs7M+QEGQNVrVwd/SCIbIPvYeaQxJDrGCgIqpB0vnxO\n\txr/5NdR+OrPUcoYOUO8gr1bsHyEFQDZb9kSHLCZ3ncJdVQtyCIhGaXzSEZunhCL6LNIP5G7N5SN+w\n\tF20cTiGsjpmQE3ttwtjg==;","Date":"Fri, 8 Sep 2017 14:11:40 +0100","From":"Dave Martin ","To":"\"Okamoto, Takayuki\" ","Subject":"Re: [PATCH v2 19/28] arm64/sve: ptrace and ELF coredump support","Message-ID":"<20170908131136.GG6321@e103592.cambridge.arm.com>","References":"<1504198860-12951-1-git-send-email-Dave.Martin@arm.com>\n\t<1504198860-12951-20-git-send-email-Dave.Martin@arm.com>\n\t<5FA513F682BE7F4EAAB8EE035D5B08E44109DFE8@G01JPEXMBKW02>\n\t<20170906181634.GF6321@e103592.cambridge.arm.com>\n\t<5FA513F682BE7F4EAAB8EE035D5B08E44109EBDF@G01JPEXMBKW02>","MIME-Version":"1.0","Content-Disposition":"inline","In-Reply-To":"<5FA513F682BE7F4EAAB8EE035D5B08E44109EBDF@G01JPEXMBKW02>","User-Agent":"Mutt/1.5.23 (2014-03-12)","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170908_061207_656535_E8B35A9B ","X-CRM114-Status":"GOOD ( 11.63 )","X-Spam-Score":"-6.9 (------)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-6.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/,\n\thigh trust [217.140.101.70 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"\"linux-arch@vger.kernel.org\" ,\n\t\"libc-alpha@sourceware.org\" , Ard Biesheuvel\n\t, Szabolcs Nagy ,\n\t\"gdb@sourceware.org\" , Yao Qi , \n\tAlan Hayward , Will Deacon , \n\tOleg Nesterov\n\t, Catalin Marinas , Alexander\n\tViro , Richard Sandiford\n\t, Alex =?iso-8859-1?q?Benn=E9e?=\n\t, \"kvmarm@lists.cs.columbia.edu\"\n\t, \"linux-arm-kernel@lists.infradead.org\"\n\t","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1768574,"web_url":"http://patchwork.ozlabs.org/comment/1768574/","msgid":"<87bmmda15n.fsf@linaro.org>","list_archive_url":null,"date":"2017-09-14T12:57:08","subject":"Re: [PATCH v2 19/28] arm64/sve: ptrace and ELF coredump support","submitter":{"id":39532,"url":"http://patchwork.ozlabs.org/api/people/39532/","name":"Alex Bennée","email":"alex.bennee@linaro.org"},"content":"Dave Martin writes:\n\n> This patch defines and implements a new regset NT_ARM_SVE, which\n> describes a thread's SVE register state. This allows a debugger to\n> manipulate the SVE state, as well as being included in ELF\n> coredumps for post-mortem debugging.\n>\n> Because the regset size and layout are dependent on the thread's\n> current vector length, it is not possible to define a C struct to\n> describe the regset contents as is done for existing regsets.\n> Instead, and for the same reasons, NT_ARM_SVE is based on the\n> freeform variable-layout approach used for the SVE signal frame.\n>\n> Additionally, to reduce debug overhead when debugging threads that\n> might or might not have live SVE register state, NT_ARM_SVE may be\n> presented in one of two different formats: the old struct\n> user_fpsimd_state format is embedded for describing the state of a\n> thread with no live SVE state, whereas a new variable-layout\n> structure is embedded for describing live SVE state. This avoids a\n> debugger needing to poll NT_PRFPREG in addition to NT_ARM_SVE, and\n> allows existing userspace code to handle the non-SVE case without\n> too much modification.\n>\n> For this to work, NT_ARM_SVE is defined with a fixed-format header\n> of type struct user_sve_header, which the recipient can use to\n> figure out the content, size and layout of the reset of the regset.\n> Accessor macros are defined to allow the vector-length-dependent\n> parts of the regset to be manipulated.\n>\n> Signed-off-by: Alan Hayward \n> Signed-off-by: Dave Martin \n> Cc: Alex Bennée \n>\n> ---\n>\n> Changes since v1\n> ----------------\n>\n> Other changes related to Alex Bennée's comments:\n>\n> * Migrate to SVE_VQ_BYTES instead of magic numbers.\n>\n> Requested by Alex Bennée:\n>\n> * Thin out BUG_ON()s:\n> Redundant BUG_ON()s and ones that just check invariants are removed.\n> Important sanity-checks are migrated to WARN_ON()s, with some\n> minimal best-effort patch-up code.\n>\n> Other:\n>\n> * [ABI fix] Bail out with -EIO if attempting to set the\n> SVE regs for an unsupported VL, instead of misparsing the regset data.\n>\n> * Replace some in-kernel open-coded arithmetic with ALIGN()/\n> DIV_ROUND_UP().\n> ---\n> arch/arm64/include/asm/fpsimd.h | 13 +-\n> arch/arm64/include/uapi/asm/ptrace.h | 135 ++++++++++++++++++\n> arch/arm64/kernel/fpsimd.c | 40 +++++-\n> arch/arm64/kernel/ptrace.c | 270 +++++++++++++++++++++++++++++++++--\n> include/uapi/linux/elf.h | 1 +\n> 5 files changed, 449 insertions(+), 10 deletions(-)\n>\n> diff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsimd.h\n> index 6c22624..2723cca 100644\n> --- a/arch/arm64/include/asm/fpsimd.h\n> +++ b/arch/arm64/include/asm/fpsimd.h\n> @@ -38,13 +38,16 @@ struct fpsimd_state {\n> \t\t\t__uint128_t vregs[32];\n> \t\t\tu32 fpsr;\n> \t\t\tu32 fpcr;\n> +\t\t\t/*\n> +\t\t\t * For ptrace compatibility, pad to next 128-bit\n> +\t\t\t * boundary here if extending this struct.\n> +\t\t\t */\n> \t\t};\n> \t};\n> \t/* the id of the last cpu to have restored this state */\n> \tunsigned int cpu;\n> };\n>\n> -\n> #if defined(__KERNEL__) && defined(CONFIG_COMPAT)\n> /* Masks for extracting the FPSR and FPCR from the FPSCR */\n> #define VFP_FPSCR_STAT_MASK\t0xf800009f\n> @@ -89,6 +92,10 @@ extern void sve_alloc(struct task_struct *task);\n> extern void fpsimd_release_thread(struct task_struct *task);\n> extern void fpsimd_dup_sve(struct task_struct *dst,\n> \t\t\t struct task_struct const *src);\n> +extern void fpsimd_sync_to_sve(struct task_struct *task);\n> +extern void sve_sync_to_fpsimd(struct task_struct *task);\n> +extern void sve_sync_from_fpsimd_zeropad(struct task_struct *task);\n> +\n> extern int sve_set_vector_length(struct task_struct *task,\n> \t\t\t\t unsigned long vl, unsigned long flags);\n>\n> @@ -103,6 +110,10 @@ static void __maybe_unused sve_alloc(struct task_struct *task) { }\n> static void __maybe_unused fpsimd_release_thread(struct task_struct *task) { }\n> static void __maybe_unused fpsimd_dup_sve(struct task_struct *dst,\n> \t\t\t\t\t struct task_struct const *src) { }\n> +static void __maybe_unused sve_sync_to_fpsimd(struct task_struct *task) { }\n> +static void __maybe_unused sve_sync_from_fpsimd_zeropad(\n> +\tstruct task_struct *task) { }\n> +\n> static void __maybe_unused sve_init_vq_map(void) { }\n> static void __maybe_unused sve_update_vq_map(void) { }\n> static int __maybe_unused sve_verify_vq_map(void) { return 0; }\n> diff --git a/arch/arm64/include/uapi/asm/ptrace.h b/arch/arm64/include/uapi/asm/ptrace.h\n> index d1ff83d..1915ab0 100644\n> --- a/arch/arm64/include/uapi/asm/ptrace.h\n> +++ b/arch/arm64/include/uapi/asm/ptrace.h\n> @@ -22,6 +22,7 @@\n> #include \n>\n> #include \n> +#include \n>\n>\n> /*\n> @@ -63,6 +64,8 @@\n>\n> #ifndef __ASSEMBLY__\n>\n> +#include \n> +\n> /*\n> * User structures for general purpose, floating point and debug registers.\n> */\n> @@ -90,6 +93,138 @@ struct user_hwdebug_state {\n> \t}\t\tdbg_regs[16];\n> };\n>\n> +/* SVE/FP/SIMD state (NT_ARM_SVE) */\n> +\n> +struct user_sve_header {\n> +\t__u32 size; /* total meaningful regset content in bytes */\n> +\t__u32 max_size; /* maxmium possible size for this thread */\n> +\t__u16 vl; /* current vector length */\n> +\t__u16 max_vl; /* maximum possible vector length */\n> +\t__u16 flags;\n> +\t__u16 __reserved;\n> +};\n> +\n> +/* Definitions for user_sve_header.flags: */\n> +#define SVE_PT_REGS_MASK\t\t(1 << 0)\n> +\n> +/* Flags: must be kept in sync with prctl interface in\n> */\n\nWhich flags? We base some on PR_foo flags but we seem to shift them\nanyway so where is the requirement for them to match from?\n\n> +#define SVE_PT_REGS_FPSIMD\t\t0\n> +#define SVE_PT_REGS_SVE\t\t\tSVE_PT_REGS_MASK\n> +\n> +#define SVE_PT_VL_INHERIT\t\t(PR_SVE_VL_INHERIT >> 16)\n> +#define SVE_PT_VL_ONEXEC\t\t(PR_SVE_SET_VL_ONEXEC >> 16)\n> +\n> +\n> +/*\n> + * The remainder of the SVE state follows struct user_sve_header. The\n> + * total size of the SVE state (including header) depends on the\n> + * metadata in the header: SVE_PT_SIZE(vq, flags) gives the total size\n> + * of the state in bytes, including the header.\n> + *\n> + * Refer to for details of how to pass the correct\n> + * \"vq\" argument to these macros.\n> + */\n> +\n> +/* Offset from the start of struct user_sve_header to the register data */\n> +#define SVE_PT_REGS_OFFSET\t\t\t\t\t\\\n> +\t((sizeof(struct sve_context) + (SVE_VQ_BYTES - 1))\t\\\n> +\t\t/ SVE_VQ_BYTES * SVE_VQ_BYTES)\n> +\n> +/*\n> + * The register data content and layout depends on the value of the\n> + * flags field.\n> + */\n> +\n> +/*\n> + * (flags & SVE_PT_REGS_MASK) == SVE_PT_REGS_FPSIMD case:\n> + *\n> + * The payload starts at offset SVE_PT_FPSIMD_OFFSET, and is of type\n> + * struct user_fpsimd_state. Additional data might be appended in the\n> + * future: use SVE_PT_FPSIMD_SIZE(vq, flags) to compute the total size.\n> + * SVE_PT_FPSIMD_SIZE(vq, flags) will never be less than\n> + * sizeof(struct user_fpsimd_state).\n> + */\n> +\n> +#define SVE_PT_FPSIMD_OFFSET\t\tSVE_PT_REGS_OFFSET\n> +\n> +#define SVE_PT_FPSIMD_SIZE(vq, flags)\t(sizeof(struct user_fpsimd_state))\n> +\n> +/*\n> + * (flags & SVE_PT_REGS_MASK) == SVE_PT_REGS_SVE case:\n> + *\n> + * The payload starts at offset SVE_PT_SVE_OFFSET, and is of size\n> + * SVE_PT_SVE_SIZE(vq, flags).\n> + *\n> + * Additional macros describe the contents and layout of the payload.\n> + * For each, SVE_PT_SVE_x_OFFSET(args) is the start offset relative to\n> + * the start of struct user_sve_header, and SVE_PT_SVE_x_SIZE(args) is\n> + * the size in bytes:\n> + *\n> + *\tx\ttype\t\t\t\tdescription\n> + *\t-\t----\t\t\t\t-----------\n> + *\tZREGS\t\t\\\n> + *\tZREG\t\t|\n> + *\tPREGS\t\t| refer to \n> + *\tPREG\t\t|\n> + *\tFFR\t\t/\n> + *\n> + *\tFPSR\tuint32_t\t\t\tFPSR\n> + *\tFPCR\tuint32_t\t\t\tFPCR\n> + *\n> + * Additional data might be appended in the future.\n> + */\n> +\n> +#define SVE_PT_SVE_ZREG_SIZE(vq)\tSVE_SIG_ZREG_SIZE(vq)\n> +#define SVE_PT_SVE_PREG_SIZE(vq)\tSVE_SIG_PREG_SIZE(vq)\n> +#define SVE_PT_SVE_FFR_SIZE(vq)\t\tSVE_SIG_FFR_SIZE(vq)\n> +#define SVE_PT_SVE_FPSR_SIZE\t\tsizeof(__u32)\n> +#define SVE_PT_SVE_FPCR_SIZE\t\tsizeof(__u32)\n> +\n> +#define __SVE_SIG_TO_PT(offset) \\\n> +\t((offset) - SVE_SIG_REGS_OFFSET + SVE_PT_REGS_OFFSET)\n> +\n> +#define SVE_PT_SVE_OFFSET\t\tSVE_PT_REGS_OFFSET\n> +\n> +#define SVE_PT_SVE_ZREGS_OFFSET \\\n> +\t__SVE_SIG_TO_PT(SVE_SIG_ZREGS_OFFSET)\n> +#define SVE_PT_SVE_ZREG_OFFSET(vq, n) \\\n> +\t__SVE_SIG_TO_PT(SVE_SIG_ZREG_OFFSET(vq, n))\n> +#define SVE_PT_SVE_ZREGS_SIZE(vq) \\\n> +\t(SVE_PT_SVE_ZREG_OFFSET(vq, SVE_NUM_ZREGS) - SVE_PT_SVE_ZREGS_OFFSET)\n> +\n> +#define SVE_PT_SVE_PREGS_OFFSET(vq) \\\n> +\t__SVE_SIG_TO_PT(SVE_SIG_PREGS_OFFSET(vq))\n> +#define SVE_PT_SVE_PREG_OFFSET(vq, n) \\\n> +\t__SVE_SIG_TO_PT(SVE_SIG_PREG_OFFSET(vq, n))\n> +#define SVE_PT_SVE_PREGS_SIZE(vq) \\\n> +\t(SVE_PT_SVE_PREG_OFFSET(vq, SVE_NUM_PREGS) - \\\n> +\t\tSVE_PT_SVE_PREGS_OFFSET(vq))\n> +\n> +#define SVE_PT_SVE_FFR_OFFSET(vq) \\\n> +\t__SVE_SIG_TO_PT(SVE_SIG_FFR_OFFSET(vq))\n> +\n> +#define SVE_PT_SVE_FPSR_OFFSET(vq)\t\t\t\t\\\n> +\t((SVE_PT_SVE_FFR_OFFSET(vq) + SVE_PT_SVE_FFR_SIZE(vq) +\t\\\n> +\t\t\t(SVE_VQ_BYTES - 1))\t\t\t\\\n> +\t\t/ SVE_VQ_BYTES * SVE_VQ_BYTES)\n> +#define SVE_PT_SVE_FPCR_OFFSET(vq) \\\n> +\t(SVE_PT_SVE_FPSR_OFFSET(vq) + SVE_PT_SVE_FPSR_SIZE)\n> +\n> +/*\n> + * Any future extension appended after FPCR must be aligned to the next\n> + * 128-bit boundary.\n> + */\n> +\n> +#define SVE_PT_SVE_SIZE(vq, flags)\t\t\t\t\t\\\n> +\t((SVE_PT_SVE_FPCR_OFFSET(vq) + SVE_PT_SVE_FPCR_SIZE\t\t\\\n> +\t\t\t- SVE_PT_SVE_OFFSET + (SVE_VQ_BYTES - 1))\t\\\n> +\t\t/ SVE_VQ_BYTES * SVE_VQ_BYTES)\n> +\n> +#define SVE_PT_SIZE(vq, flags)\t\t\t\t\t\t\\\n> +\t (((flags) & SVE_PT_REGS_MASK) == SVE_PT_REGS_SVE ?\t\t\\\n> +\t\t SVE_PT_SVE_OFFSET + SVE_PT_SVE_SIZE(vq, flags)\t\\\n> +\t\t: SVE_PT_FPSIMD_OFFSET + SVE_PT_FPSIMD_SIZE(vq, flags))\n> +\n> #endif /* __ASSEMBLY__ */\n>\n> #endif /* _UAPI__ASM_PTRACE_H */\n> diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c\n> index fff9fcf..361c019 100644\n> --- a/arch/arm64/kernel/fpsimd.c\n> +++ b/arch/arm64/kernel/fpsimd.c\n> @@ -303,6 +303,37 @@ void sve_alloc(struct task_struct *task)\n> \tBUG_ON(!task->thread.sve_state);\n> }\n>\n> +void fpsimd_sync_to_sve(struct task_struct *task)\n> +{\n> +\tif (!test_tsk_thread_flag(task, TIF_SVE))\n> +\t\tfpsimd_to_sve(task);\n> +}\n> +\n> +void sve_sync_to_fpsimd(struct task_struct *task)\n> +{\n> +\tif (test_tsk_thread_flag(task, TIF_SVE))\n> +\t\tsve_to_fpsimd(task);\n> +}\n> +\n> +void sve_sync_from_fpsimd_zeropad(struct task_struct *task)\n> +{\n> +\tunsigned int vq;\n> +\tvoid *sst = task->thread.sve_state;\n> +\tstruct fpsimd_state const *fst = &task->thread.fpsimd_state;\n> +\tunsigned int i;\n> +\n> +\tif (!test_tsk_thread_flag(task, TIF_SVE))\n> +\t\treturn;\n> +\n> +\tvq = sve_vq_from_vl(task->thread.sve_vl);\n> +\n> +\tmemset(sst, 0, SVE_SIG_REGS_SIZE(vq));\n> +\n> +\tfor (i = 0; i < 32; ++i)\n> +\t\tmemcpy(ZREG(sst, vq, i), &fst->vregs[i],\n> +\t\t sizeof(fst->vregs[i]));\n> +}\n> +\n> /*\n> * Handle SVE state across fork():\n> *\n> @@ -459,10 +490,17 @@ static void __init sve_efi_setup(void)\n> \t * This is evidence of a crippled system and we are returning void,\n> \t * so no attempt is made to handle this situation here.\n> \t */\n> -\tBUG_ON(!sve_vl_valid(sve_max_vl));\n> +\tif (!sve_vl_valid(sve_max_vl))\n> +\t\tgoto fail;\n> +\n> \tefi_sve_state = __alloc_percpu(\n> \t\tSVE_SIG_REGS_SIZE(sve_vq_from_vl(sve_max_vl)), SVE_VQ_BYTES);\n> \tif (!efi_sve_state)\n> +\t\tgoto fail;\n> +\n> +\treturn;\n> +\n> +fail:\n> \t\tpanic(\"Cannot allocate percpu memory for EFI SVE save/restore\");\n> }\n>\n> diff --git a/arch/arm64/kernel/ptrace.c b/arch/arm64/kernel/ptrace.c\n> index 9cbb612..5ef4735b 100644\n> --- a/arch/arm64/kernel/ptrace.c\n> +++ b/arch/arm64/kernel/ptrace.c\n> @@ -32,6 +32,7 @@\n> #include \n> #include \n> #include \n> +#include \n> #include \n> #include \n> #include \n> @@ -40,6 +41,7 @@\n> #include \n>\n> #include \n> +#include \n> #include \n> #include \n> #include \n> @@ -618,33 +620,66 @@ static int gpr_set(struct task_struct *target, const struct user_regset *regset,\n> /*\n> * TODO: update fp accessors for lazy context switching (sync/flush hwstate)\n> */\n> -static int fpr_get(struct task_struct *target, const struct user_regset *regset,\n> -\t\t unsigned int pos, unsigned int count,\n> -\t\t void *kbuf, void __user *ubuf)\n> +static int __fpr_get(struct task_struct *target,\n> +\t\t const struct user_regset *regset,\n> +\t\t unsigned int pos, unsigned int count,\n> +\t\t void *kbuf, void __user *ubuf, unsigned int start_pos)\n> {\n> \tstruct user_fpsimd_state *uregs;\n> +\n> +\tsve_sync_to_fpsimd(target);\n> +\n> \turegs = &target->thread.fpsimd_state.user_fpsimd;\n>\n> +\treturn user_regset_copyout(&pos, &count, &kbuf, &ubuf, uregs,\n> +\t\t\t\t start_pos, start_pos + sizeof(*uregs));\n> +}\n> +\n> +static int fpr_get(struct task_struct *target, const struct user_regset *regset,\n> +\t\t unsigned int pos, unsigned int count,\n> +\t\t void *kbuf, void __user *ubuf)\n> +{\n> \tif (target == current)\n> \t\tfpsimd_preserve_current_state();\n>\n> -\treturn user_regset_copyout(&pos, &count, &kbuf, &ubuf, uregs, 0, -1);\n> +\treturn __fpr_get(target, regset, pos, count, kbuf, ubuf, 0);\n> }\n>\n> -static int fpr_set(struct task_struct *target, const struct user_regset *regset,\n> -\t\t unsigned int pos, unsigned int count,\n> -\t\t const void *kbuf, const void __user *ubuf)\n> +static int __fpr_set(struct task_struct *target,\n> +\t\t const struct user_regset *regset,\n> +\t\t unsigned int pos, unsigned int count,\n> +\t\t const void *kbuf, const void __user *ubuf,\n> +\t\t unsigned int start_pos)\n> {\n> \tint ret;\n> \tstruct user_fpsimd_state newstate =\n> \t\ttarget->thread.fpsimd_state.user_fpsimd;\n>\n> -\tret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &newstate, 0, -1);\n> +\tsve_sync_to_fpsimd(target);\n> +\n> +\tret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &newstate,\n> +\t\t\t\t start_pos, start_pos + sizeof(newstate));\n> \tif (ret)\n> \t\treturn ret;\n>\n> \ttarget->thread.fpsimd_state.user_fpsimd = newstate;\n> +\n> +\treturn ret;\n> +}\n> +\n> +static int fpr_set(struct task_struct *target, const struct user_regset *regset,\n> +\t\t unsigned int pos, unsigned int count,\n> +\t\t const void *kbuf, const void __user *ubuf)\n> +{\n> +\tint ret;\n> +\n> +\tret = __fpr_set(target, regset, pos, count, kbuf, ubuf, 0);\n> +\tif (ret)\n> +\t\treturn ret;\n> +\n> +\tsve_sync_from_fpsimd_zeropad(target);\n> \tfpsimd_flush_task_state(target);\n> +\n> \treturn ret;\n> }\n>\n> @@ -702,6 +737,210 @@ static int system_call_set(struct task_struct *target,\n> \treturn ret;\n> }\n>\n> +#ifdef CONFIG_ARM64_SVE\n> +\n> +static void sve_init_header_from_task(struct user_sve_header *header,\n> +\t\t\t\t struct task_struct *target)\n> +{\n> +\tunsigned int vq;\n> +\n> +\tmemset(header, 0, sizeof(*header));\n> +\n> +\theader->flags = test_tsk_thread_flag(target, TIF_SVE) ?\n> +\t\tSVE_PT_REGS_SVE : SVE_PT_REGS_FPSIMD;\n> +\tif (test_tsk_thread_flag(target, TIF_SVE_VL_INHERIT))\n> +\t\theader->flags |= SVE_PT_VL_INHERIT;\n> +\n> +\theader->vl = target->thread.sve_vl;\n> +\tvq = sve_vq_from_vl(header->vl);\n> +\n> +\tif (WARN_ON(!sve_vl_valid(sve_max_vl)))\n> +\t\theader->max_vl = header->vl;\n> +\n> +\theader->size = SVE_PT_SIZE(vq, header->flags);\n> +\theader->max_size = SVE_PT_SIZE(sve_vq_from_vl(header->max_vl),\n> +\t\t\t\t SVE_PT_REGS_SVE);\n> +}\n> +\n> +static unsigned int sve_size_from_header(struct user_sve_header const *header)\n> +{\n> +\treturn ALIGN(header->size, SVE_VQ_BYTES);\n> +}\n> +\n> +static unsigned int sve_get_size(struct task_struct *target,\n> +\t\t\t\t const struct user_regset *regset)\n> +{\n> +\tstruct user_sve_header header;\n> +\n> +\tif (!system_supports_sve())\n> +\t\treturn 0;\n> +\n> +\tsve_init_header_from_task(&header, target);\n> +\treturn sve_size_from_header(&header);\n> +}\n> +\n> +static int sve_get(struct task_struct *target,\n> +\t\t const struct user_regset *regset,\n> +\t\t unsigned int pos, unsigned int count,\n> +\t\t void *kbuf, void __user *ubuf)\n> +{\n> +\tint ret;\n> +\tstruct user_sve_header header;\n> +\tunsigned int vq;\n> +\tunsigned long start, end;\n> +\n> +\tif (!system_supports_sve())\n> +\t\treturn -EINVAL;\n> +\n> +\t/* Header */\n> +\tsve_init_header_from_task(&header, target);\n> +\tvq = sve_vq_from_vl(header.vl);\n> +\n> +\tret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &header,\n> +\t\t\t\t 0, sizeof(header));\n> +\tif (ret)\n> +\t\treturn ret;\n> +\n> +\tif (target == current)\n> +\t\tfpsimd_preserve_current_state();\n> +\n> +\t/* Registers: FPSIMD-only case */\n> +\n> +\tBUILD_BUG_ON(SVE_PT_FPSIMD_OFFSET != sizeof(header));\n> +\tif ((header.flags & SVE_PT_REGS_MASK) == SVE_PT_REGS_FPSIMD)\n> +\t\treturn __fpr_get(target, regset, pos, count, kbuf, ubuf,\n> +\t\t\t\t SVE_PT_FPSIMD_OFFSET);\n> +\n> +\t/* Otherwise: full SVE case */\n> +\n> +\tBUILD_BUG_ON(SVE_PT_SVE_OFFSET != sizeof(header));\n> +\tstart = SVE_PT_SVE_OFFSET;\n> +\tend = SVE_PT_SVE_FFR_OFFSET(vq) + SVE_PT_SVE_FFR_SIZE(vq);\n> +\tret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,\n> +\t\t\t\t target->thread.sve_state,\n> +\t\t\t\t start, end);\n> +\tif (ret)\n> +\t\treturn ret;\n> +\n> +\tstart = end;\n> +\tend = SVE_PT_SVE_FPSR_OFFSET(vq);\n> +\tret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,\n> +\t\t\t\t start, end);\n> +\tif (ret)\n> +\t\treturn ret;\n> +\n> +\t/*\n> +\t * Copy fpsr, and fpcr which must follow contiguously in\n> +\t * struct fpsimd_state:\n> +\t */\n> +\tstart = end;\n> +\tend = SVE_PT_SVE_FPCR_OFFSET(vq) + SVE_PT_SVE_FPCR_SIZE;\n> +\tret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,\n> +\t\t\t\t &target->thread.fpsimd_state.fpsr,\n> +\t\t\t\t start, end);\n> +\tif (ret)\n> +\t\treturn ret;\n> +\n> +\tstart = end;\n> +\tend = sve_size_from_header(&header);\n> +\treturn user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,\n> +\t\t\t\t\tstart, end);\n> +}\n> +\n> +static int sve_set(struct task_struct *target,\n> +\t\t const struct user_regset *regset,\n> +\t\t unsigned int pos, unsigned int count,\n> +\t\t const void *kbuf, const void __user *ubuf)\n> +{\n> +\tint ret;\n> +\tstruct user_sve_header header;\n> +\tunsigned int vq;\n> +\tunsigned long start, end;\n> +\n> +\tif (!system_supports_sve())\n> +\t\treturn -EINVAL;\n> +\n> +\t/* Header */\n> +\tif (count < sizeof(header))\n> +\t\treturn -EINVAL;\n> +\tret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &header,\n> +\t\t\t\t 0, sizeof(header));\n> +\tif (ret)\n> +\t\tgoto out;\n> +\n> +\t/*\n> +\t * Apart from PT_SVE_REGS_MASK, all PT_SVE_* flags are consumed by\n> +\t * sve_set_vector_length(), which will also validate them for us:\n> +\t */\n> +\tret = sve_set_vector_length(target, header.vl,\n> +\t\t\t\t header.flags & ~SVE_PT_REGS_MASK);\n> +\tif (ret)\n> +\t\tgoto out;\n> +\n> +\t/* Actual VL set may be less than the user asked for: */\n> +\tvq = sve_vq_from_vl(target->thread.sve_vl);\n> +\n> +\t/* Registers: FPSIMD-only case */\n> +\n> +\tBUILD_BUG_ON(SVE_PT_FPSIMD_OFFSET != sizeof(header));\n> +\tif ((header.flags & SVE_PT_REGS_MASK) == SVE_PT_REGS_FPSIMD) {\n> +\t\tsve_sync_to_fpsimd(target);\n> +\n> +\t\tret = __fpr_set(target, regset, pos, count, kbuf, ubuf,\n> +\t\t\t\tSVE_PT_FPSIMD_OFFSET);\n> +\t\tclear_tsk_thread_flag(target, TIF_SVE);\n> +\t\tgoto out;\n> +\t}\n> +\n> +\t/* Otherwise: full SVE case */\n> +\n> +\t/*\n> +\t * If setting a different VL from the requested VL and there is\n> +\t * register data, the data layout will be wrong: don't even\n> +\t * try to set the registers in this case.\n> +\t */\n> +\tif (count && vq != sve_vq_from_vl(header.vl)) {\n> +\t\tret = -EIO;\n> +\t\tgoto out;\n> +\t}\n> +\n> +\tsve_alloc(target);\n> +\tfpsimd_sync_to_sve(target);\n> +\tset_tsk_thread_flag(target, TIF_SVE);\n> +\n> +\tBUILD_BUG_ON(SVE_PT_SVE_OFFSET != sizeof(header));\n> +\tstart = SVE_PT_SVE_OFFSET;\n> +\tend = SVE_PT_SVE_FFR_OFFSET(vq) + SVE_PT_SVE_FFR_SIZE(vq);\n> +\tret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,\n> +\t\t\t\t target->thread.sve_state,\n> +\t\t\t\t start, end);\n> +\tif (ret)\n> +\t\tgoto out;\n> +\n> +\tstart = end;\n> +\tend = SVE_PT_SVE_FPSR_OFFSET(vq);\n> +\tret = user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf,\n> +\t\t\t\t\tstart, end);\n> +\tif (ret)\n> +\t\tgoto out;\n> +\n> +\t/*\n> +\t * Copy fpsr, and fpcr which must follow contiguously in\n> +\t * struct fpsimd_state:\n> +\t */\n> +\tstart = end;\n> +\tend = SVE_PT_SVE_FPCR_OFFSET(vq) + SVE_PT_SVE_FPCR_SIZE;\n> +\tret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,\n> +\t\t\t\t &target->thread.fpsimd_state.fpsr,\n> +\t\t\t\t start, end);\n> +\n> +out:\n> +\tfpsimd_flush_task_state(target);\n> +\treturn ret;\n> +}\n> +\n> +#endif /* CONFIG_ARM64_SVE */\n> +\n> enum aarch64_regset {\n> \tREGSET_GPR,\n> \tREGSET_FPR,\n> @@ -711,6 +950,9 @@ enum aarch64_regset {\n> \tREGSET_HW_WATCH,\n> #endif\n> \tREGSET_SYSTEM_CALL,\n> +#ifdef CONFIG_ARM64_SVE\n> +\tREGSET_SVE,\n> +#endif\n> };\n>\n> static const struct user_regset aarch64_regsets[] = {\n> @@ -768,6 +1010,18 @@ static const struct user_regset aarch64_regsets[] = {\n> \t\t.get = system_call_get,\n> \t\t.set = system_call_set,\n> \t},\n> +#ifdef CONFIG_ARM64_SVE\n> +\t[REGSET_SVE] = { /* Scalable Vector Extension */\n> +\t\t.core_note_type = NT_ARM_SVE,\n> +\t\t.n = DIV_ROUND_UP(SVE_PT_SIZE(SVE_VQ_MAX, SVE_PT_REGS_SVE),\n> +\t\t\t\t SVE_VQ_BYTES),\n> +\t\t.size = SVE_VQ_BYTES,\n> +\t\t.align = SVE_VQ_BYTES,\n> +\t\t.get = sve_get,\n> +\t\t.set = sve_set,\n> +\t\t.get_size = sve_get_size,\n> +\t},\n> +#endif\n> };\n>\n> static const struct user_regset_view user_aarch64_view = {\n> diff --git a/include/uapi/linux/elf.h b/include/uapi/linux/elf.h\n> index b5280db..735b8f4 100644\n> --- a/include/uapi/linux/elf.h\n> +++ b/include/uapi/linux/elf.h\n> @@ -416,6 +416,7 @@ typedef struct elf64_shdr {\n> #define NT_ARM_HW_BREAK\t0x402\t\t/* ARM hardware breakpoint registers */\n> #define NT_ARM_HW_WATCH\t0x403\t\t/* ARM hardware watchpoint registers */\n> #define NT_ARM_SYSTEM_CALL\t0x404\t/* ARM system call number */\n> +#define NT_ARM_SVE\t0x405\t\t/* ARM Scalable Vector Extension registers */\n> #define NT_METAG_CBUF\t0x500\t\t/* Metag catch buffer registers */\n> #define NT_METAG_RPIPE\t0x501\t\t/* Metag read pipeline state */\n> #define NT_METAG_TLS\t0x502\t\t/* Metag TLS pointer */\n\nOtherwise:\n\nReviewed-by: Alex Bennée \n\n--\nAlex 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[PATCH v2 19/28] arm64/sve: ptrace and ELF coredump support","In-reply-to":"<1504198860-12951-20-git-send-email-Dave.Martin@arm.com>","Date":"Thu, 14 Sep 2017 13:57:08 +0100","Message-ID":"<87bmmda15n.fsf@linaro.org>","MIME-Version":"1.0","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170914_055733_821828_D457FB4B ","X-CRM114-Status":"GOOD ( 31.50 )","X-Spam-Score":"-2.7 (--)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-2.7 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/,\n\tlow\n\ttrust [2a00:1450:400c:c09:0:0:0:235 listed in] [list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or 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","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1777082,"web_url":"http://patchwork.ozlabs.org/comment/1777082/","msgid":"<20170928145717.GD3611@e103592.cambridge.arm.com>","list_archive_url":null,"date":"2017-09-28T14:57:18","subject":"Re: [PATCH v2 19/28] arm64/sve: ptrace and ELF coredump support","submitter":{"id":26612,"url":"http://patchwork.ozlabs.org/api/people/26612/","name":"Dave Martin","email":"Dave.Martin@arm.com"},"content":"On Thu, Sep 14, 2017 at 01:57:08PM +0100, Alex Bennée wrote:\n> \n> Dave Martin writes:\n> \n> > This patch defines and implements a new regset NT_ARM_SVE, which\n> > describes a thread's SVE register state. This allows a debugger to\n> > manipulate the SVE state, as well as being included in ELF\n> > coredumps for post-mortem debugging.\n> >\n> > Because the regset size and layout are dependent on the thread's\n> > current vector length, it is not possible to define a C struct to\n> > describe the regset contents as is done for existing regsets.\n> > Instead, and for the same reasons, NT_ARM_SVE is based on the\n> > freeform variable-layout approach used for the SVE signal frame.\n> >\n> > Additionally, to reduce debug overhead when debugging threads that\n> > might or might not have live SVE register state, NT_ARM_SVE may be\n> > presented in one of two different formats: the old struct\n> > user_fpsimd_state format is embedded for describing the state of a\n> > thread with no live SVE state, whereas a new variable-layout\n> > structure is embedded for describing live SVE state. This avoids a\n> > debugger needing to poll NT_PRFPREG in addition to NT_ARM_SVE, and\n> > allows existing userspace code to handle the non-SVE case without\n> > too much modification.\n> >\n> > For this to work, NT_ARM_SVE is defined with a fixed-format header\n> > of type struct user_sve_header, which the recipient can use to\n> > figure out the content, size and layout of the reset of the regset.\n> > Accessor macros are defined to allow the vector-length-dependent\n> > parts of the regset to be manipulated.\n> >\n> > Signed-off-by: Alan Hayward \n> > Signed-off-by: Dave Martin \n> > Cc: Alex Bennée \n> >\n> > ---\n> >\n> > Changes since v1\n> > ----------------\n> >\n> > Other changes related to Alex Bennée's comments:\n> >\n> > * Migrate to SVE_VQ_BYTES instead of magic numbers.\n> >\n> > Requested by Alex Bennée:\n> >\n> > * Thin out BUG_ON()s:\n> > Redundant BUG_ON()s and ones that just check invariants are removed.\n> > Important sanity-checks are migrated to WARN_ON()s, with some\n> > minimal best-effort patch-up code.\n> >\n> > Other:\n> >\n> > * [ABI fix] Bail out with -EIO if attempting to set the\n> > SVE regs for an unsupported VL, instead of misparsing the regset data.\n> >\n> > * Replace some in-kernel open-coded arithmetic with ALIGN()/\n> > DIV_ROUND_UP().\n> > ---\n\n[...]\n\n> > diff --git a/arch/arm64/include/uapi/asm/ptrace.h b/arch/arm64/include/uapi/asm/ptrace.h\n> > index d1ff83d..1915ab0 100644\n> > --- a/arch/arm64/include/uapi/asm/ptrace.h\n> > +++ b/arch/arm64/include/uapi/asm/ptrace.h\n> > @@ -22,6 +22,7 @@\n> > #include \n> >\n> > #include \n> > +#include \n> >\n> >\n> > /*\n> > @@ -63,6 +64,8 @@\n> >\n> > #ifndef __ASSEMBLY__\n> >\n> > +#include \n> > +\n> > /*\n> > * User structures for general purpose, floating point and debug registers.\n> > */\n> > @@ -90,6 +93,138 @@ struct user_hwdebug_state {\n> > \t}\t\tdbg_regs[16];\n> > };\n> >\n> > +/* SVE/FP/SIMD state (NT_ARM_SVE) */\n> > +\n> > +struct user_sve_header {\n> > +\t__u32 size; /* total meaningful regset content in bytes */\n> > +\t__u32 max_size; /* maxmium possible size for this thread */\n> > +\t__u16 vl; /* current vector length */\n> > +\t__u16 max_vl; /* maximum possible vector length */\n> > +\t__u16 flags;\n> > +\t__u16 __reserved;\n> > +};\n> > +\n> > +/* Definitions for user_sve_header.flags: */\n> > +#define SVE_PT_REGS_MASK\t\t(1 << 0)\n> > +\n> > +/* Flags: must be kept in sync with prctl interface in\n> > */\n> \n> Which flags? We base some on PR_foo flags but we seem to shift them\n\nAll the prctl flags that have equivalents here, because they're part of\nthe internal API to sve_set_vector_length(). It didn't quite seem\nappropriate to document that in a userspace header, but it's probably\nbetter to say something here than not. I'll improve the comment.\n\n> anyway so where is the requirement for them to match from?\n\nThere is a bug here though: sve_set() in ptrace.c is supposed to shift\nthe flags from header.flags (which is a u16) back into the\nPR_SVE_SET_VL position (<< 16) for the flags argument of\nsve_set_vector_length(). But this isn't done, so attempting to set (or\nrestore) those flags through ptrace may resulting EINVALs from\nsve_set_vector_length().\n\nI'll write a test for this case and implement a fix, something like...\n\n-8<-\n\n static int sve_set(struct task_struct *target,\n[...]\n \tret = sve_set_vector_length(target, header.vl,\n-\t\t\t\t header.flags & ~SVE_PT_REGS_MASK);\n+\t\t\t\t (header.flags & ~SVE_PT_REGS_MASK) << 16UL);\n\n\n->8-\n\nWhat do you think?\n\n[...]\n\n> Reviewed-by: Alex Bennée \n\nAgain, I'll wait for your feedback first.\n\nCheers\n---Dave","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"jWBfEvqw\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y2yV96GFbz9t66\n\tfor ;\n\tFri, 29 Sep 2017 00:57:53 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dxaG4-0006ax-5g; Thu, 28 Sep 2017 14:57:48 +0000","from foss.arm.com ([217.140.101.70])\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dxaFz-0006SC-Fa for linux-arm-kernel@lists.infradead.org;\n\tThu, 28 Sep 2017 14:57:46 +0000","from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249])\n\tby usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 271F41435;\n\tThu, 28 Sep 2017 07:57:23 -0700 (PDT)","from e103592.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com\n\t[10.72.51.249])\n\tby usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id\n\t9CAA03F483; Thu, 28 Sep 2017 07:57:20 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:\n\tMessage-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=Ngh+bQXAKrQVr1UV8gdTqXsSQ437Ctykm9ZEn4r111A=;\n\tb=jWBfEvqw5AB7Ft\n\tjJDt8KguxT/YERix5zo/Y4/nOpHyhg5Fx/J4M3dc6Slspdz8IHo0DP9WrUq+Rlnyi9/Au3Nx414S+\n\tmK4cTrhvgmaR/NBbyHq6gmsH7ppMv6rVrdNWpzz5vTHfQeFAZM3WOAUK9W7Vjz6Zaj2m8VynsyaJD\n\t4zJtjIabeleh19VG8GtopVpHp9JUgmhAoYltsiUlt96m7PJQ2N3iEkoAsSBqpboiZpT3SFpCCpf40\n\tpu2MRnvI/fGJXIhuiVEOdD9nfYHmqSBu5kFcQkOGWUT6mftsOpPTjvkztWtrSAJHwdvA7yYTuMdPW\n\ts7CMEBzlOifTEGA228vQ==;","Date":"Thu, 28 Sep 2017 15:57:18 +0100","From":"Dave Martin ","To":"Alex =?iso-8859-1?q?Benn=E9e?= ","Subject":"Re: [PATCH v2 19/28] arm64/sve: ptrace and ELF coredump support","Message-ID":"<20170928145717.GD3611@e103592.cambridge.arm.com>","References":"<1504198860-12951-1-git-send-email-Dave.Martin@arm.com>\n\t<1504198860-12951-20-git-send-email-Dave.Martin@arm.com>\n\t<87bmmda15n.fsf@linaro.org>","MIME-Version":"1.0","Content-Disposition":"inline","In-Reply-To":"<87bmmda15n.fsf@linaro.org>","User-Agent":"Mutt/1.5.23 (2014-03-12)","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170928_075743_542301_77012C57 ","X-CRM114-Status":"GOOD ( 23.12 )","X-Spam-Score":"-6.9 (------)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-6.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/,\n\thigh trust [217.140.101.70 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"linux-arch@vger.kernel.org, libc-alpha@sourceware.org,\n\tArd Biesheuvel ,\n\tSzabolcs Nagy , gdb@sourceware.org,\n\tYao Qi , Alan Hayward ,\n\tWill Deacon , Oleg Nesterov ,\n\tRichard Sandiford ,\n\tAlexander Viro ,\n\tCatalin Marinas , kvmarm@lists.cs.columbia.edu, \n\tlinux-arm-kernel@lists.infradead.org","Content-Type":"text/plain; charset=\"iso-8859-1\"","Content-Transfer-Encoding":"quoted-printable","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1777521,"web_url":"http://patchwork.ozlabs.org/comment/1777521/","msgid":"<20170929124605.GF3611@e103592.cambridge.arm.com>","list_archive_url":null,"date":"2017-09-29T12:46:06","subject":"Re: [PATCH v2 19/28] arm64/sve: ptrace and ELF coredump support","submitter":{"id":26612,"url":"http://patchwork.ozlabs.org/api/people/26612/","name":"Dave Martin","email":"Dave.Martin@arm.com"},"content":"On Thu, Sep 14, 2017 at 01:57:08PM +0100, Alex Bennée wrote:\n> \n> Dave Martin writes:\n> \n> > This patch defines and implements a new regset NT_ARM_SVE, which\n> > describes a thread's SVE register state. This allows a debugger to\n> > manipulate the SVE state, as well as being included in ELF\n> > coredumps for post-mortem debugging.\n> >\n> > Because the regset size and layout are dependent on the thread's\n> > current vector length, it is not possible to define a C struct to\n> > describe the regset contents as is done for existing regsets.\n> > Instead, and for the same reasons, NT_ARM_SVE is based on the\n> > freeform variable-layout approach used for the SVE signal frame.\n> >\n> > Additionally, to reduce debug overhead when debugging threads that\n> > might or might not have live SVE register state, NT_ARM_SVE may be\n> > presented in one of two different formats: the old struct\n> > user_fpsimd_state format is embedded for describing the state of a\n> > thread with no live SVE state, whereas a new variable-layout\n> > structure is embedded for describing live SVE state. This avoids a\n> > debugger needing to poll NT_PRFPREG in addition to NT_ARM_SVE, and\n> > allows existing userspace code to handle the non-SVE case without\n> > too much modification.\n> >\n> > For this to work, NT_ARM_SVE is defined with a fixed-format header\n> > of type struct user_sve_header, which the recipient can use to\n> > figure out the content, size and layout of the reset of the regset.\n> > Accessor macros are defined to allow the vector-length-dependent\n> > parts of the regset to be manipulated.\n> >\n> > Signed-off-by: Alan Hayward \n> > Signed-off-by: Dave Martin \n> > Cc: Alex Bennée \n> >\n> > ---\n> >\n> > Changes since v1\n> > ----------------\n> >\n> > Other changes related to Alex Bennée's comments:\n> >\n> > * Migrate to SVE_VQ_BYTES instead of magic numbers.\n> >\n> > Requested by Alex Bennée:\n> >\n> > * Thin out BUG_ON()s:\n> > Redundant BUG_ON()s and ones that just check invariants are removed.\n> > Important sanity-checks are migrated to WARN_ON()s, with some\n> > minimal best-effort patch-up code.\n> >\n> > Other:\n> >\n> > * [ABI fix] Bail out with -EIO if attempting to set the\n> > SVE regs for an unsupported VL, instead of misparsing the regset data.\n> >\n> > * Replace some in-kernel open-coded arithmetic with ALIGN()/\n> > DIV_ROUND_UP().\n> > ---\n\n[...]\n\n> > diff --git a/arch/arm64/include/uapi/asm/ptrace.h b/arch/arm64/include/uapi/asm/ptrace.h\n\n[...]\n\n> > +/* Definitions for user_sve_header.flags: */\n> > +#define SVE_PT_REGS_MASK\t\t(1 << 0)\n> > +\n> > +/* Flags: must be kept in sync with prctl interface in\n> > */\n> \n> Which flags? We base some on PR_foo flags but we seem to shift them\n> anyway so where is the requirement for them to match from?\n\nI've rearranged this as:\n\n-8<-\n\n/* Definitions for user_sve_header.flags: */\n#define SVE_PT_REGS_MASK\t\t(1 << 0)\n\n#define SVE_PT_REGS_FPSIMD\t\t0\n#define SVE_PT_REGS_SVE\t\t\tSVE_PT_REGS_MASK\n\n/*\n * Common SVE_PT_* flags:\n * These must be kept in sync with prctl interface in \n */\n#define SVE_PT_VL_INHERIT\t\t(PR_SVE_VL_INHERIT >> 16)\n#define SVE_PT_VL_ONEXEC\t\t(PR_SVE_SET_VL_ONEXEC >> 16)\n\n->8-\n\nThis avoids the suggestion that SVE_PT_REGS_{MASK,FPSIMD,SVE} are\nsupposed to have prctl counterparts.\n\nI don't really want to write more, in case it is misinterpreted as\nspecification of behaviour.\n\nThis comment is really only meant as a reminder to maintainers that\nthey should go look at prctl.h too, before blindly making changes\nhere.\n\n\nAny good? If you have a different suggestion, I'm all ears...\n\n[...]\n\nCheers\n---Dave","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"EmuzI6EJ\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y3WXN2jygz9t4R\n\tfor ;\n\tFri, 29 Sep 2017 22:46:42 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dxugd-000316-Q3; Fri, 29 Sep 2017 12:46:35 +0000","from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]\n\thelo=foss.arm.com)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dxugZ-0002wK-Ra for linux-arm-kernel@lists.infradead.org;\n\tFri, 29 Sep 2017 12:46:33 +0000","from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249])\n\tby usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7CD511529;\n\tFri, 29 Sep 2017 05:46:11 -0700 (PDT)","from e103592.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com\n\t[10.72.51.249])\n\tby usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id\n\tF148F3F53D; Fri, 29 Sep 2017 05:46:08 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:\n\tMessage-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=/rMTJn5PIQwPhaCqhMaG0t7ElpnsgWwoRTF9PzqXvWs=;\n\tb=EmuzI6EJw6wB3U\n\thTDWFajdghj6LAxtiNKGS1dAV627kWjhlqqLXaQZVRUaNO31LnNxEGJEp8HJq9R0ZfOD7UYlZpSYx\n\t5gzti/bImnX5O43hP5IRLmeQRgzivcCMdkQBuPY7We8DyqO26ptpno0qOLeNylhyaJ1JzKnWniSuL\n\thWfckbwKI51ELz2pVe0+Tf+9bJt6BRGr8j5dD1qJw/oEMOz/ptkbARlKSGbmpoEefJVksBovJY2YS\n\taPFPm+tyRkUDuDwT4z108x/uSlRv/1tuXcZA6zFVF4i8jBPBR8NqcdX2waxfXnLkd7OC5UZEpOa2C\n\t5BCT2FR8vqtPvfq5sTCQ==;","Date":"Fri, 29 Sep 2017 13:46:06 +0100","From":"Dave Martin ","To":"Alex =?iso-8859-1?q?Benn=E9e?= ","Subject":"Re: [PATCH v2 19/28] arm64/sve: ptrace and ELF coredump support","Message-ID":"<20170929124605.GF3611@e103592.cambridge.arm.com>","References":"<1504198860-12951-1-git-send-email-Dave.Martin@arm.com>\n\t<1504198860-12951-20-git-send-email-Dave.Martin@arm.com>\n\t<87bmmda15n.fsf@linaro.org>","MIME-Version":"1.0","Content-Disposition":"inline","In-Reply-To":"<87bmmda15n.fsf@linaro.org>","User-Agent":"Mutt/1.5.23 (2014-03-12)","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170929_054631_915651_8879B658 ","X-CRM114-Status":"GOOD ( 20.93 )","X-Spam-Score":"-6.9 (------)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-6.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/,\n\thigh trust [217.140.101.70 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"linux-arch@vger.kernel.org, libc-alpha@sourceware.org,\n\tArd Biesheuvel ,\n\tSzabolcs Nagy , gdb@sourceware.org,\n\tYao Qi , Alan Hayward ,\n\tWill Deacon , Oleg Nesterov ,\n\tRichard Sandiford ,\n\tAlexander Viro ,\n\tCatalin Marinas , kvmarm@lists.cs.columbia.edu, \n\tlinux-arm-kernel@lists.infradead.org","Content-Type":"text/plain; charset=\"iso-8859-1\"","Content-Transfer-Encoding":"quoted-printable","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}}]