[{"id":1768575,"web_url":"http://patchwork.ozlabs.org/comment/1768575/","msgid":"<87a81xa0w5.fsf@linaro.org>","list_archive_url":null,"date":"2017-09-14T13:02:50","subject":"Re: [PATCH v2 20/28] arm64/sve: Add prctl controls for userspace\n\tvector length management","submitter":{"id":39532,"url":"http://patchwork.ozlabs.org/api/people/39532/","name":"Alex Bennée","email":"alex.bennee@linaro.org"},"content":"Dave Martin <Dave.Martin@arm.com> writes:\n\n> This patch adds two arm64-specific prctls, to permit userspace to\n> control its vector length:\n>\n>  * PR_SVE_SET_VL: set the thread's SVE vector length and vector\n>    length inheritance mode.\n>\n>  * PR_SVE_GET_VL: get the same information.\n>\n> Although these calls shadow instruction set features in the SVE\n> architecture, these prctls provide additional control: the vector\n> length inheritance mode is Linux-specific and nothing to do with\n> the architecture, and the architecture does not permit EL0 to set\n> its own vector length directly.  Both can be used in portable tools\n> without requiring the use of SVE instructions.\n>\n> Signed-off-by: Dave Martin <Dave.Martin@arm.com>\n\nReviewed-by: Alex Bennée <alex.bennee@linaro.org>\n\n> ---\n>  arch/arm64/include/asm/fpsimd.h    | 14 ++++++++++++\n>  arch/arm64/include/asm/processor.h |  4 ++++\n>  arch/arm64/kernel/fpsimd.c         | 46 ++++++++++++++++++++++++++++++++++++++\n>  include/uapi/linux/prctl.h         |  4 ++++\n>  kernel/sys.c                       | 12 ++++++++++\n>  5 files changed, 80 insertions(+)\n>\n> diff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsimd.h\n> index 2723cca..d084968 100644\n> --- a/arch/arm64/include/asm/fpsimd.h\n> +++ b/arch/arm64/include/asm/fpsimd.h\n> @@ -17,6 +17,7 @@\n>  #define __ASM_FP_H\n>\n>  #include <asm/ptrace.h>\n> +#include <asm/errno.h>\n>\n>  #ifndef __ASSEMBLY__\n>\n> @@ -99,6 +100,9 @@ extern void sve_sync_from_fpsimd_zeropad(struct task_struct *task);\n>  extern int sve_set_vector_length(struct task_struct *task,\n>  \t\t\t\t unsigned long vl, unsigned long flags);\n>\n> +extern int sve_set_current_vl(unsigned long arg);\n> +extern int sve_get_current_vl(void);\n> +\n>  extern void __init sve_init_vq_map(void);\n>  extern void sve_update_vq_map(void);\n>  extern int sve_verify_vq_map(void);\n> @@ -114,6 +118,16 @@ static void __maybe_unused sve_sync_to_fpsimd(struct task_struct *task) { }\n>  static void __maybe_unused sve_sync_from_fpsimd_zeropad(\n>  \tstruct task_struct *task) { }\n>\n> +static int __maybe_unused sve_set_current_vl(unsigned long arg)\n> +{\n> +\treturn -EINVAL;\n> +}\n> +\n> +static int __maybe_unused sve_get_current_vl(void)\n> +{\n> +\treturn -EINVAL;\n> +}\n> +\n>  static void __maybe_unused sve_init_vq_map(void) { }\n>  static void __maybe_unused sve_update_vq_map(void) { }\n>  static int __maybe_unused sve_verify_vq_map(void) { return 0; }\n> diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h\n> index 3faceac..df66452 100644\n> --- a/arch/arm64/include/asm/processor.h\n> +++ b/arch/arm64/include/asm/processor.h\n> @@ -197,4 +197,8 @@ static inline void spin_lock_prefetch(const void *ptr)\n>  int cpu_enable_pan(void *__unused);\n>  int cpu_enable_cache_maint_trap(void *__unused);\n>\n> +/* Userspace interface for PR_SVE_{SET,GET}_VL prctl()s: */\n> +#define SVE_SET_VL(arg)\tsve_set_current_vl(arg)\n> +#define SVE_GET_VL()\tsve_get_current_vl()\n> +\n>  #endif /* __ASM_PROCESSOR_H */\n> diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c\n> index 361c019..42e8331 100644\n> --- a/arch/arm64/kernel/fpsimd.c\n> +++ b/arch/arm64/kernel/fpsimd.c\n> @@ -27,6 +27,7 @@\n>  #include <linux/kernel.h>\n>  #include <linux/init.h>\n>  #include <linux/percpu.h>\n> +#include <linux/prctl.h>\n>  #include <linux/preempt.h>\n>  #include <linux/prctl.h>\n>  #include <linux/ptrace.h>\n> @@ -420,6 +421,51 @@ int sve_set_vector_length(struct task_struct *task,\n>  \treturn 0;\n>  }\n>\n> +/*\n> + * Encode the current vector length and flags for return.\n> + * This is only required for prctl(): ptrace has separate fields\n> + */\n> +static int sve_prctl_status(void)\n> +{\n> +\tint ret = current->thread.sve_vl;\n> +\n> +\tif (test_thread_flag(TIF_SVE_VL_INHERIT))\n> +\t\tret |= PR_SVE_VL_INHERIT;\n> +\n> +\treturn ret;\n> +}\n> +\n> +/* PR_SVE_SET_VL */\n> +int sve_set_current_vl(unsigned long arg)\n> +{\n> +\tunsigned long vl, flags;\n> +\tint ret;\n> +\n> +\tvl = arg & PR_SVE_VL_LEN_MASK;\n> +\tflags = arg & ~vl;\n> +\n> +\tif (!system_supports_sve())\n> +\t\treturn -EINVAL;\n> +\n> +\tpreempt_disable();\n> +\tret = sve_set_vector_length(current, vl, flags);\n> +\tpreempt_enable();\n> +\n> +\tif (ret)\n> +\t\treturn ret;\n> +\n> +\treturn sve_prctl_status();\n> +}\n> +\n> +/* PR_SVE_GET_VL */\n> +int sve_get_current_vl(void)\n> +{\n> +\tif (!system_supports_sve())\n> +\t\treturn -EINVAL;\n> +\n> +\treturn sve_prctl_status();\n> +}\n> +\n>  static unsigned long *sve_alloc_vq_map(void)\n>  {\n>  \treturn kzalloc(BITS_TO_LONGS(SVE_VQ_MAX) * sizeof(unsigned long),\n> diff --git a/include/uapi/linux/prctl.h b/include/uapi/linux/prctl.h\n> index 1b64901..1ef9370 100644\n> --- a/include/uapi/linux/prctl.h\n> +++ b/include/uapi/linux/prctl.h\n> @@ -198,7 +198,11 @@ struct prctl_mm_map {\n>  # define PR_CAP_AMBIENT_CLEAR_ALL\t4\n>\n>  /* arm64 Scalable Vector Extension controls */\n> +/* Flag values must be kept in sync with ptrace NT_ARM_SVE interface */\n> +#define PR_SVE_SET_VL\t\t\t48\t/* set task vector length */\n>  # define PR_SVE_SET_VL_ONEXEC\t\t(1 << 18) /* defer effect until exec */\n> +#define PR_SVE_GET_VL\t\t\t49\t/* get task vector length */\n> +/* Bits common to PR_SVE_SET_VL and PR_SVE_GET_VL */\n>  # define PR_SVE_VL_LEN_MASK\t\t0xffff\n>  # define PR_SVE_VL_INHERIT\t\t(1 << 17) /* inherit across exec */\n>\n> diff --git a/kernel/sys.c b/kernel/sys.c\n> index 2855ee7..f8215a6 100644\n> --- a/kernel/sys.c\n> +++ b/kernel/sys.c\n> @@ -110,6 +110,12 @@\n>  #ifndef SET_FP_MODE\n>  # define SET_FP_MODE(a,b)\t(-EINVAL)\n>  #endif\n> +#ifndef SVE_SET_VL\n> +# define SVE_SET_VL(a)\t\t(-EINVAL)\n> +#endif\n> +#ifndef SVE_GET_VL\n> +# define SVE_GET_VL()\t\t(-EINVAL)\n> +#endif\n>\n>  /*\n>   * this is where the system-wide overflow UID and GID are defined, for\n> @@ -2389,6 +2395,12 @@ SYSCALL_DEFINE5(prctl, int, option, unsigned long, arg2, unsigned long, arg3,\n>  \tcase PR_GET_FP_MODE:\n>  \t\terror = GET_FP_MODE(me);\n>  \t\tbreak;\n> +\tcase PR_SVE_SET_VL:\n> +\t\terror = SVE_SET_VL(arg2);\n> +\t\tbreak;\n> +\tcase PR_SVE_GET_VL:\n> +\t\terror = SVE_GET_VL();\n> +\t\tbreak;\n>  \tdefault:\n>  \t\terror = -EINVAL;\n>  \t\tbreak;\n\n\n--\nAlex Bennée","headers":{"Return-Path":"<libc-alpha-return-84612-incoming=patchwork.ozlabs.org@sourceware.org>","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list libc-alpha@sourceware.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=sourceware.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=libc-alpha-return-84612-incoming=patchwork.ozlabs.org@sourceware.org;\n\treceiver=<UNKNOWN>)","ozlabs.org; dkim=pass (1024-bit key;\n\tsecure) header.d=sourceware.org header.i=@sourceware.org\n\theader.b=\"nV7p7nWS\"; dkim-atps=neutral","sourceware.org; auth=none"],"Received":["from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xtJc72FZ9z9sPs\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 14 Sep 2017 23:03:03 +1000 (AEST)","(qmail 80975 invoked by alias); 14 Sep 2017 13:02:57 -0000","(qmail 80961 invoked by uid 89); 14 Sep 2017 13:02:56 -0000"],"DomainKey-Signature":"a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:references:from:to:cc:subject:in-reply-to:date\n\t:message-id:mime-version:content-type:content-transfer-encoding;\n\tq=dns; s=default; b=YVU7ABTGJP5LKgqVLB1f2lO7vRP2Cu1a/7/GhcycD2H\n\tPjtyG3b6JF8o8JbsJO+TPreQ2zSEuwaC0yS/gR+xO6Vi329OcQoburm3FH2WOhxA\n\to7BEu3w8RCs7KtoMk5txWAKUYvRqOR/l0fEQZaQ41KXWFLH4f0gIROYM7IdtyqCc\n\t=","DKIM-Signature":"v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:references:from:to:cc:subject:in-reply-to:date\n\t:message-id:mime-version:content-type:content-transfer-encoding;\n\ts=default; bh=HL4HX63k1qjshxyJCuf64nD3rDQ=; b=nV7p7nWSqojKDunY0\n\t174xUHs5cnQxkXpsh3flXTvvsC7GWYiDgEw/sCxPTzeEidQZfN6brI++jS0QLzuE\n\tEDQWxPviYnnkWdzaMBJMAr0y4UlKmcWtdrMwBOvU3I/CyHyt/XjwT1+lZ/vYhN3i\n\tlc8CubXqJo6hTkznN+cIck3ycg=","Mailing-List":"contact libc-alpha-help@sourceware.org; run by ezmlm","Precedence":"bulk","List-Id":"<libc-alpha.sourceware.org>","List-Unsubscribe":"<mailto:libc-alpha-unsubscribe-incoming=patchwork.ozlabs.org@sourceware.org>","List-Subscribe":"<mailto:libc-alpha-subscribe@sourceware.org>","List-Archive":"<http://sourceware.org/ml/libc-alpha/>","List-Post":"<mailto:libc-alpha@sourceware.org>","List-Help":"<mailto:libc-alpha-help@sourceware.org>,\n\t<http://sourceware.org/ml/#faqs>","Sender":"libc-alpha-owner@sourceware.org","X-Virus-Found":"No","X-Spam-SWARE-Status":"No, score=-26.4 required=5.0 tests=AWL, BAYES_00,\n\tGIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3,\n\tRCVD_IN_DNSWL_NONE,\n\tSPF_PASS autolearn=ham version=3.3.2 spammy=","X-HELO":"mail-wm0-f42.google.com","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:references:user-agent:from:to:cc:subject\n\t:in-reply-to:date:message-id:mime-version:content-transfer-encoding; \n\tbh=ku2lDE8yXMrIJrdDPaoYOtequ7cakMlp3GXKs95hWeg=;\n\tb=jkBNhnTC3cdWjCm2QGYIFN3BgYlHrREAwH8GiK11r8PLb9qGTVP8o+7EY6SkhuoFUE\n\tdOwEzVRyjZn0+OkjvmL/MdOCg3mcgNGUsbZuqBmSyyoXW9PlXRQZJRDY9fHatptigW/t\n\tsjKbNAsYWWCRXGpYST/uK+q49kaDlxTdb1Invfi9TYDkQL+Xzx8YnVvF53U8bdl4DG8Q\n\t+y+o51eBW5ju1SF4JyIwdzvEJU+/sgWP55D24RZUYhvgft4qkHLq3WHkToGv6hf2Ll2f\n\t1Ryqsoar84mnXzIvkEfPB2FEAy8H3ahdfXM1SFBwkRkGGpnl1zK8IhDy0Rn1pF3+PIJn\n\tLVcA==","X-Gm-Message-State":"AHPjjUj4P4ZkKlCi0siQz6z5U+b9NODuacSEUzIktVu7nrR8bCyOWNcc\n\tdMGo+1P6iLIqe+7g","X-Google-Smtp-Source":"AOwi7QBxnq2bklRyqHboAFdhoLqAjHgm14O+3SZu4c9HihcNlUoHLpjTi5bgQ5RlpZabkqYlHG6jGg==","X-Received":"by 10.28.125.205 with SMTP id y196mr2048384wmc.128.1505394171788;\n\tThu, 14 Sep 2017 06:02:51 -0700 (PDT)","References":"<1504198860-12951-1-git-send-email-Dave.Martin@arm.com>\n\t<1504198860-12951-21-git-send-email-Dave.Martin@arm.com>","User-agent":"mu4e 0.9.19; emacs 25.2.50.3","From":"Alex =?utf-8?q?Benn=C3=A9e?= <alex.bennee@linaro.org>","To":"Dave Martin <Dave.Martin@arm.com>","Cc":"linux-arm-kernel@lists.infradead.org,\n\tCatalin Marinas <catalin.marinas@arm.com>,\n\tWill Deacon <will.deacon@arm.com>,\n\tArd Biesheuvel <ard.biesheuvel@linaro.org>,\n\tSzabolcs Nagy <szabolcs.nagy@arm.com>,\n\tRichard Sandiford <richard.sandiford@arm.com>,\n\tkvmarm@lists.cs.columbia.edu, libc-alpha@sourceware.org,\n\tlinux-arch@vger.kernel.org, Andrew Morton <akpm@linux-foundation.org>","Subject":"Re: [PATCH v2 20/28] arm64/sve: Add prctl controls for userspace\n\tvector length management","In-reply-to":"<1504198860-12951-21-git-send-email-Dave.Martin@arm.com>","Date":"Thu, 14 Sep 2017 14:02:50 +0100","Message-ID":"<87a81xa0w5.fsf@linaro.org>","MIME-Version":"1.0","Content-Type":"text/plain; charset=utf-8","Content-Transfer-Encoding":"8bit"}}]