[{"id":1768425,"web_url":"http://patchwork.ozlabs.org/comment/1768425/","msgid":"<87k211acqe.fsf@linaro.org>","list_archive_url":null,"date":"2017-09-14T08:47:05","subject":"Re: [PATCH v2 12/28] arm64/sve: Support vector length resetting for\n\tnew processes","submitter":{"id":39532,"url":"http://patchwork.ozlabs.org/api/people/39532/","name":"Alex Bennée","email":"alex.bennee@linaro.org"},"content":"Dave Martin writes:\n\n> It's desirable to be able to reset the vector length to some sane\n> default for new processes, since the new binary and its libraries\n> processes may or may not be SVE-aware.\n>\n> This patch tracks the desired post-exec vector length (if any) in a\n> new thread member sve_vl_onexec, and adds a new thread flag\n> TIF_SVE_VL_INHERIT to control whether to inherit or reset the\n> vector length. Currently these are inactive. Subsequent patches\n> will provide the capability to configure them.\n>\n> Signed-off-by: Dave Martin \n> Cc: Alex Bennée \n\nReviewed-by: Alex Bennée \n\n>\n> ---\n>\n> Changes since v1\n> ----------------\n>\n> Requested by Alex Bennée:\n>\n> * Make sve_vl_onexec an unsigned int: that's the type used virtually\n> everywhere else, and the memory saving is too minor to be interesting.\n> ---\n> arch/arm64/include/asm/processor.h | 1 +\n> arch/arm64/include/asm/thread_info.h | 1 +\n> arch/arm64/kernel/fpsimd.c | 16 ++++++++++++----\n> 3 files changed, 14 insertions(+), 4 deletions(-)\n>\n> diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h\n> index 4831d28..3faceac 100644\n> --- a/arch/arm64/include/asm/processor.h\n> +++ b/arch/arm64/include/asm/processor.h\n> @@ -87,6 +87,7 @@ struct thread_struct {\n> \tstruct fpsimd_state\tfpsimd_state;\n> \tvoid\t\t\t*sve_state;\t/* SVE registers, if any */\n> \tunsigned int\t\tsve_vl;\t\t/* SVE vector length */\n> +\tunsigned int\t\tsve_vl_onexec;\t/* SVE vl after next exec */\n> \tunsigned long\t\tfault_address;\t/* fault info */\n> \tunsigned long\t\tfault_code;\t/* ESR_EL1 value */\n> \tstruct debug_info\tdebug;\t\t/* debugging */\n> diff --git a/arch/arm64/include/asm/thread_info.h b/arch/arm64/include/asm/thread_info.h\n> index f0880fc..d3568ab 100644\n> --- a/arch/arm64/include/asm/thread_info.h\n> +++ b/arch/arm64/include/asm/thread_info.h\n> @@ -92,6 +92,7 @@ void arch_setup_new_exec(void);\n> #define TIF_SINGLESTEP\t\t21\n> #define TIF_32BIT\t\t22\t/* 32bit process */\n> #define TIF_SVE\t\t\t23\t/* Scalable Vector Extension in use */\n> +#define TIF_SVE_VL_INHERIT\t24\t/* Inherit sve_vl_onexec across exec */\n>\n> #define _TIF_SIGPENDING\t\t(1 << TIF_SIGPENDING)\n> #define _TIF_NEED_RESCHED\t(1 << TIF_NEED_RESCHED)\n> diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c\n> index 9b1ebd7..e20b44d 100644\n> --- a/arch/arm64/kernel/fpsimd.c\n> +++ b/arch/arm64/kernel/fpsimd.c\n> @@ -106,6 +106,9 @@\n> */\n> static DEFINE_PER_CPU(struct fpsimd_state *, fpsimd_last_state);\n>\n> +/* Default VL for tasks that don't set it explicitly: */\n> +static int sve_default_vl = SVE_VL_MIN;\n> +\n> static void sve_free(struct task_struct *task)\n> {\n> \tkfree(task->thread.sve_state);\n> @@ -380,15 +383,20 @@ void fpsimd_flush_thread(void)\n> \t\t * If a bug causes this to go wrong, we make some noise and\n> \t\t * try to fudge thread.sve_vl to a safe value here.\n> \t\t */\n> -\t\tvl = current->thread.sve_vl;\n> -\n> -\t\tif (vl == 0)\n> -\t\t\tvl = SVE_VL_MIN;\n> +\t\tvl = current->thread.sve_vl_onexec ?\n> +\t\t\tcurrent->thread.sve_vl_onexec : sve_default_vl;\n>\n> \t\tif (WARN_ON(!sve_vl_valid(vl)))\n> \t\t\tvl = SVE_VL_MIN;\n>\n> \t\tcurrent->thread.sve_vl = vl;\n> +\n> +\t\t/*\n> +\t\t * If the task is not set to inherit, ensure that the vector\n> +\t\t * length will be reset by a subsequent exec:\n> +\t\t */\n> +\t\tif (!test_thread_flag(TIF_SVE_VL_INHERIT))\n> +\t\t\tcurrent->thread.sve_vl_onexec = 0;\n> \t}\n>\n> \tset_thread_flag(TIF_FOREIGN_FPSTATE);\n\n\n--\nAlex Bennée","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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emacs 25.2.50.3","From":"Alex =?utf-8?q?Benn=C3=A9e?= ","To":"Dave Martin ","Subject":"Re: [PATCH v2 12/28] arm64/sve: Support vector length resetting for\n\tnew processes","In-reply-to":"<1504198860-12951-13-git-send-email-Dave.Martin@arm.com>","Date":"Thu, 14 Sep 2017 09:47:05 +0100","Message-ID":"<87k211acqe.fsf@linaro.org>","MIME-Version":"1.0","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170914_014730_101162_C5AE02A6 ","X-CRM114-Status":"GOOD ( 22.00 )","X-Spam-Score":"-2.0 (--)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-2.0 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/,\n\tno\n\ttrust [2a00:1450:400c:c0c:0:0:0:230 listed in] [list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"linux-arch@vger.kernel.org, libc-alpha@sourceware.org,\n\tArd Biesheuvel ,\n\tSzabolcs Nagy ,\n\tCatalin Marinas ,\n\tWill Deacon , \n\tRichard Sandiford ,\n\tkvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org","Content-Type":"text/plain; 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