[{"id":1767948,"web_url":"http://patchwork.ozlabs.org/comment/1767948/","msgid":"<87o9qeac2s.fsf@linaro.org>","list_archive_url":null,"date":"2017-09-13T14:48:59","subject":"Re: [PATCH v2 06/28] arm64/sve: System register and exception\n\tsyndrome definitions","submitter":{"id":39532,"url":"http://patchwork.ozlabs.org/api/people/39532/","name":"Alex Bennée","email":"alex.bennee@linaro.org"},"content":"Dave Martin writes:\n\n> The SVE architecture adds some system registers, ID register fields\n> and a dedicated ESR exception class.\n>\n> This patch adds the appropriate definitions that will be needed by\n> the kernel.\n>\n> Signed-off-by: Dave Martin \n> Cc: Alex Bennée \n\nReviewed-by: Alex Bennée \n\n>\n> ---\n>\n> Changes since v1\n> ----------------\n>\n> Requested by Alex Bennée:\n>\n> * Add comments to clarify CPACR_EL1_ZEN_ELxEN bit meanings.\n> * Add comment clarifying the status of the LEN field expansion bits.\n> ---\n> arch/arm64/include/asm/esr.h | 3 ++-\n> arch/arm64/include/asm/kvm_arm.h | 1 +\n> arch/arm64/include/asm/sysreg.h | 21 +++++++++++++++++++++\n> arch/arm64/kernel/traps.c | 1 +\n> 4 files changed, 25 insertions(+), 1 deletion(-)\n>\n> diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h\n> index 66ed8b6..014d7d8 100644\n> --- a/arch/arm64/include/asm/esr.h\n> +++ b/arch/arm64/include/asm/esr.h\n> @@ -43,7 +43,8 @@\n> #define ESR_ELx_EC_HVC64\t(0x16)\n> #define ESR_ELx_EC_SMC64\t(0x17)\n> #define ESR_ELx_EC_SYS64\t(0x18)\n> -/* Unallocated EC: 0x19 - 0x1E */\n> +#define ESR_ELx_EC_SVE\t\t(0x19)\n> +/* Unallocated EC: 0x1A - 0x1E */\n> #define ESR_ELx_EC_IMP_DEF\t(0x1f)\n> #define ESR_ELx_EC_IABT_LOW\t(0x20)\n> #define ESR_ELx_EC_IABT_CUR\t(0x21)\n> diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h\n> index 61d694c..dbf0537 100644\n> --- a/arch/arm64/include/asm/kvm_arm.h\n> +++ b/arch/arm64/include/asm/kvm_arm.h\n> @@ -185,6 +185,7 @@\n> #define CPTR_EL2_TCPAC\t(1 << 31)\n> #define CPTR_EL2_TTA\t(1 << 20)\n> #define CPTR_EL2_TFP\t(1 << CPTR_EL2_TFP_SHIFT)\n> +#define CPTR_EL2_TZ\t(1 << 8)\n> #define CPTR_EL2_DEFAULT\t0x000033ff\n>\n> /* Hyp Debug Configuration Register bits */\n> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h\n> index 480ecd6..36fe2ae 100644\n> --- a/arch/arm64/include/asm/sysreg.h\n> +++ b/arch/arm64/include/asm/sysreg.h\n> @@ -145,6 +145,7 @@\n>\n> #define SYS_ID_AA64PFR0_EL1\t\tsys_reg(3, 0, 0, 4, 0)\n> #define SYS_ID_AA64PFR1_EL1\t\tsys_reg(3, 0, 0, 4, 1)\n> +#define SYS_ID_AA64ZFR0_EL1\t\tsys_reg(3, 0, 0, 4, 4)\n>\n> #define SYS_ID_AA64DFR0_EL1\t\tsys_reg(3, 0, 0, 5, 0)\n> #define SYS_ID_AA64DFR1_EL1\t\tsys_reg(3, 0, 0, 5, 1)\n> @@ -163,6 +164,8 @@\n> #define SYS_ACTLR_EL1\t\t\tsys_reg(3, 0, 1, 0, 1)\n> #define SYS_CPACR_EL1\t\t\tsys_reg(3, 0, 1, 0, 2)\n>\n> +#define SYS_ZCR_EL1\t\t\tsys_reg(3, 0, 1, 2, 0)\n> +\n> #define SYS_TTBR0_EL1\t\t\tsys_reg(3, 0, 2, 0, 0)\n> #define SYS_TTBR1_EL1\t\t\tsys_reg(3, 0, 2, 0, 1)\n> #define SYS_TCR_EL1\t\t\tsys_reg(3, 0, 2, 0, 2)\n> @@ -253,6 +256,8 @@\n>\n> #define SYS_PMCCFILTR_EL0\t\tsys_reg (3, 3, 14, 15, 7)\n>\n> +#define SYS_ZCR_EL2\t\t\tsys_reg(3, 4, 1, 2, 0)\n> +\n> #define SYS_DACR32_EL2\t\t\tsys_reg(3, 4, 3, 0, 0)\n> #define SYS_IFSR32_EL2\t\t\tsys_reg(3, 4, 5, 0, 1)\n> #define SYS_FPEXC32_EL2\t\t\tsys_reg(3, 4, 5, 3, 0)\n> @@ -335,6 +340,7 @@\n> #define ID_AA64ISAR1_DPB_SHIFT\t\t0\n>\n> /* id_aa64pfr0 */\n> +#define ID_AA64PFR0_SVE_SHIFT\t\t32\n> #define ID_AA64PFR0_GIC_SHIFT\t\t24\n> #define ID_AA64PFR0_ASIMD_SHIFT\t\t20\n> #define ID_AA64PFR0_FP_SHIFT\t\t16\n> @@ -343,6 +349,7 @@\n> #define ID_AA64PFR0_EL1_SHIFT\t\t4\n> #define ID_AA64PFR0_EL0_SHIFT\t\t0\n>\n> +#define ID_AA64PFR0_SVE\t\t\t0x1\n> #define ID_AA64PFR0_FP_NI\t\t0xf\n> #define ID_AA64PFR0_FP_SUPPORTED\t0x0\n> #define ID_AA64PFR0_ASIMD_NI\t\t0xf\n> @@ -444,6 +451,20 @@\n> #endif\n>\n>\n> +/*\n> + * The ZCR_ELx_LEN_* definitions intentionally include bits [8:4] which\n> + * are reserved by the SVE architecture for future expansion of the LEN\n> + * field, with compatible semantics.\n> + */\n> +#define ZCR_ELx_LEN_SHIFT\t0\n> +#define ZCR_ELx_LEN_SIZE\t9\n> +#define ZCR_ELx_LEN_MASK\t0x1ff\n> +\n> +#define CPACR_EL1_ZEN_EL1EN\t(1 << 16) /* enable EL1 access */\n> +#define CPACR_EL1_ZEN_EL0EN\t(1 << 17) /* enable EL0 access, if EL1EN set */\n> +#define CPACR_EL1_ZEN\t\t(CPACR_EL1_ZEN_EL1EN | CPACR_EL1_ZEN_EL0EN)\n> +\n> +\n> /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */\n> #define SYS_MPIDR_SAFE_VAL\t\t(1UL << 31)\n>\n> diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c\n> index 5ea4b85..f202932 100644\n> --- a/arch/arm64/kernel/traps.c\n> +++ b/arch/arm64/kernel/traps.c\n> @@ -603,6 +603,7 @@ static const char *esr_class_str[] = {\n> \t[ESR_ELx_EC_HVC64]\t\t= \"HVC (AArch64)\",\n> \t[ESR_ELx_EC_SMC64]\t\t= \"SMC (AArch64)\",\n> \t[ESR_ELx_EC_SYS64]\t\t= \"MSR/MRS (AArch64)\",\n> +\t[ESR_ELx_EC_SVE]\t\t= \"SVE\",\n> \t[ESR_ELx_EC_IMP_DEF]\t\t= \"EL3 IMP DEF\",\n> \t[ESR_ELx_EC_IABT_LOW]\t\t= \"IABT (lower EL)\",\n> \t[ESR_ELx_EC_IABT_CUR]\t\t= \"IABT (current EL)\",\n\n\n--\nAlex Bennée","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"OSPML5Ss\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"bEuog128\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org 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