[{"id":1767971,"web_url":"http://patchwork.ozlabs.org/comment/1767971/","msgid":"<87mv5ya9qb.fsf@linaro.org>","list_archive_url":null,"date":"2017-09-13T15:39:40","subject":"Re: [PATCH v2 07/28] arm64/sve: Low-level SVE architectural state\n\tmanipulation functions","submitter":{"id":39532,"url":"http://patchwork.ozlabs.org/api/people/39532/","name":"Alex Bennée","email":"alex.bennee@linaro.org"},"content":"Dave Martin writes:\n\n> Manipulating the SVE architectural state, including the vector and\n> predicate registers, first-fault register and the vector length,\n> requires the use of dedicated instructions added by SVE.\n>\n> This patch adds suitable assembly functions for saving and\n> restoring the SVE registers and querying the vector length.\n> Setting of the vector length is done as part of register restore.\n>\n> Since people building kernels may not all get an SVE-enabled\n> toolchain for a while, this patch uses macros that generate\n> explicit opcodes in place of assembler mnemonics.\n>\n> Signed-off-by: Dave Martin \n> Cc: Alex Bennée \n\nIt took me a while to find a way to properly dissemble the resulting\nbinaries, in the end needing to run a native objdump in Stretch. I'd\nhopped my gdb-multiarch was bleeding edge enough but no ;-)\n\nReviewed-by: Alex Bennée \n\n>\n> ---\n>\n> Changes since v1\n> ----------------\n>\n> Requested by Alex Bennée:\n>\n> * Annotate instruction generation macros with the canonical\n> architectural syntax so that people can cross-reference more easily\n> against the architectural documentation.\n> ---\n> arch/arm64/include/asm/fpsimd.h | 5 ++\n> arch/arm64/include/asm/fpsimdmacros.h | 148 ++++++++++++++++++++++++++++++++++\n> arch/arm64/kernel/entry-fpsimd.S | 17 ++++\n> 3 files changed, 170 insertions(+)\n>\n> diff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsimd.h\n> index 410c481..026a7c7 100644\n> --- a/arch/arm64/include/asm/fpsimd.h\n> +++ b/arch/arm64/include/asm/fpsimd.h\n> @@ -67,6 +67,11 @@ extern void fpsimd_update_current_state(struct fpsimd_state *state);\n>\n> extern void fpsimd_flush_task_state(struct task_struct *target);\n>\n> +extern void sve_save_state(void *state, u32 *pfpsr);\n> +extern void sve_load_state(void const *state, u32 const *pfpsr,\n> +\t\t\t unsigned long vq_minus_1);\n> +extern unsigned int sve_get_vl(void);\n> +\n> /* For use by EFI runtime services calls only */\n> extern void __efi_fpsimd_begin(void);\n> extern void __efi_fpsimd_end(void);\n> diff --git a/arch/arm64/include/asm/fpsimdmacros.h b/arch/arm64/include/asm/fpsimdmacros.h\n> index 0f5fdd3..e050d76 100644\n> --- a/arch/arm64/include/asm/fpsimdmacros.h\n> +++ b/arch/arm64/include/asm/fpsimdmacros.h\n> @@ -75,3 +75,151 @@\n> \tldr\tw\\tmpnr, [\\state, #16 * 2 + 4]\n> \tfpsimd_restore_fpcr x\\tmpnr, \\state\n> .endm\n> +\n> +/* Sanity-check macros to help avoid encoding garbage instructions */\n> +\n> +.macro _check_general_reg nr\n> +\t.if (\\nr) < 0 || (\\nr) > 30\n> +\t\t.error \"Bad register number \\nr.\"\n> +\t.endif\n> +.endm\n> +\n> +.macro _sve_check_zreg znr\n> +\t.if (\\znr) < 0 || (\\znr) > 31\n> +\t\t.error \"Bad Scalable Vector Extension vector register number \\znr.\"\n> +\t.endif\n> +.endm\n> +\n> +.macro _sve_check_preg pnr\n> +\t.if (\\pnr) < 0 || (\\pnr) > 15\n> +\t\t.error \"Bad Scalable Vector Extension predicate register number \\pnr.\"\n> +\t.endif\n> +.endm\n> +\n> +.macro _check_num n, min, max\n> +\t.if (\\n) < (\\min) || (\\n) > (\\max)\n> +\t\t.error \"Number \\n out of range [\\min,\\max]\"\n> +\t.endif\n> +.endm\n> +\n> +/* SVE instruction encodings for non-SVE-capable assemblers */\n> +\n> +/* STR (vector): STR Z\\nz, [X\\nxbase, #\\offset, MUL VL] */\n> +.macro _sve_str_v nz, nxbase, offset=0\n> +\t_sve_check_zreg \\nz\n> +\t_check_general_reg \\nxbase\n> +\t_check_num (\\offset), -0x100, 0xff\n> +\t.inst\t0xe5804000\t\t\t\\\n> +\t\t| (\\nz)\t\t\t\t\\\n> +\t\t| ((\\nxbase) << 5)\t\t\\\n> +\t\t| (((\\offset) & 7) << 10)\t\\\n> +\t\t| (((\\offset) & 0x1f8) << 13)\n> +.endm\n> +\n> +/* LDR (vector): LDR Z\\nz, [X\\nxbase, #\\offset, MUL VL] */\n> +.macro _sve_ldr_v nz, nxbase, offset=0\n> +\t_sve_check_zreg \\nz\n> +\t_check_general_reg \\nxbase\n> +\t_check_num (\\offset), -0x100, 0xff\n> +\t.inst\t0x85804000\t\t\t\\\n> +\t\t| (\\nz)\t\t\t\t\\\n> +\t\t| ((\\nxbase) << 5)\t\t\\\n> +\t\t| (((\\offset) & 7) << 10)\t\\\n> +\t\t| (((\\offset) & 0x1f8) << 13)\n> +.endm\n> +\n> +/* STR (predicate): STR P\\np, [X\\nxbase, #\\offset, MUL VL] */\n> +.macro _sve_str_p np, nxbase, offset=0\n> +\t_sve_check_preg \\np\n> +\t_check_general_reg \\nxbase\n> +\t_check_num (\\offset), -0x100, 0xff\n> +\t.inst\t0xe5800000\t\t\t\\\n> +\t\t| (\\np)\t\t\t\t\\\n> +\t\t| ((\\nxbase) << 5)\t\t\\\n> +\t\t| (((\\offset) & 7) << 10)\t\\\n> +\t\t| (((\\offset) & 0x1f8) << 13)\n> +.endm\n> +\n> +/* LDR (predicate): LDR P\\np, [X\\nxbase, #\\offset, MUL VL] */\n> +.macro _sve_ldr_p np, nxbase, offset=0\n> +\t_sve_check_preg \\np\n> +\t_check_general_reg \\nxbase\n> +\t_check_num (\\offset), -0x100, 0xff\n> +\t.inst\t0x85800000\t\t\t\\\n> +\t\t| (\\np)\t\t\t\t\\\n> +\t\t| ((\\nxbase) << 5)\t\t\\\n> +\t\t| (((\\offset) & 7) << 10)\t\\\n> +\t\t| (((\\offset) & 0x1f8) << 13)\n> +.endm\n> +\n> +/* RDVL X\\nx, #\\imm */\n> +.macro _sve_rdvl nx, imm\n> +\t_check_general_reg \\nx\n> +\t_check_num (\\imm), -0x20, 0x1f\n> +\t.inst\t0x04bf5000\t\t\t\\\n> +\t\t| (\\nx)\t\t\t\t\\\n> +\t\t| (((\\imm) & 0x3f) << 5)\n> +.endm\n> +\n> +/* RDFFR (unpredicated): RDFFR P\\np.B */\n> +.macro _sve_rdffr np\n> +\t_sve_check_preg \\np\n> +\t.inst\t0x2519f000\t\t\t\\\n> +\t\t| (\\np)\n> +.endm\n> +\n> +/* WRFFR P\\np.B */\n> +.macro _sve_wrffr np\n> +\t_sve_check_preg \\np\n> +\t.inst\t0x25289000\t\t\t\\\n> +\t\t| ((\\np) << 5)\n> +.endm\n> +\n> +.macro __for from:req, to:req\n> +\t.if (\\from) == (\\to)\n> +\t\t_for__body \\from\n> +\t.else\n> +\t\t__for \\from, (\\from) + ((\\to) - (\\from)) / 2\n> +\t\t__for (\\from) + ((\\to) - (\\from)) / 2 + 1, \\to\n> +\t.endif\n> +.endm\n> +\n> +.macro _for var:req, from:req, to:req, insn:vararg\n> +\t.macro _for__body \\var:req\n> +\t\t\\insn\n> +\t.endm\n> +\n> +\t__for \\from, \\to\n> +\n> +\t.purgem _for__body\n> +.endm\n> +\n> +.macro sve_save nxbase, xpfpsr, nxtmp\n> + _for n, 0, 31,\t_sve_str_v\t\\n, \\nxbase, \\n - 34\n> + _for n, 0, 15,\t_sve_str_p\t\\n, \\nxbase, \\n - 16\n> +\t\t_sve_rdffr\t0\n> +\t\t_sve_str_p\t0, \\nxbase\n> +\t\t_sve_ldr_p\t0, \\nxbase, -16\n> +\n> +\t\tmrs\t\tx\\nxtmp, fpsr\n> +\t\tstr\t\tw\\nxtmp, [\\xpfpsr]\n> +\t\tmrs\t\tx\\nxtmp, fpcr\n> +\t\tstr\t\tw\\nxtmp, [\\xpfpsr, #4]\n> +.endm\n> +\n> +.macro sve_load nxbase, xpfpsr, xvqminus1, nxtmp\n> +\t\tmrs_s\t\tx\\nxtmp, SYS_ZCR_EL1\n> +\t\tbic\t\tx\\nxtmp, x\\nxtmp, ZCR_ELx_LEN_MASK\n> +\t\torr\t\tx\\nxtmp, x\\nxtmp, \\xvqminus1\n> +\t\tmsr_s\t\tSYS_ZCR_EL1, x\\nxtmp\t// self-synchronising\n> +\n> + _for n, 0, 31,\t_sve_ldr_v\t\\n, \\nxbase, \\n - 34\n> +\t\t_sve_ldr_p\t0, \\nxbase\n> +\t\t_sve_wrffr\t0\n> + _for n, 0, 15,\t_sve_ldr_p\t\\n, \\nxbase, \\n - 16\n> +\n> +\t\tldr\t\tw\\nxtmp, [\\xpfpsr]\n> +\t\tmsr\t\tfpsr, x\\nxtmp\n> +\t\tldr\t\tw\\nxtmp, [\\xpfpsr, #4]\n> +\t\tmsr\t\tfpcr, x\\nxtmp\n> +.endm\n> diff --git a/arch/arm64/kernel/entry-fpsimd.S b/arch/arm64/kernel/entry-fpsimd.S\n> index 6a27cd6..73f17bf 100644\n> --- a/arch/arm64/kernel/entry-fpsimd.S\n> +++ b/arch/arm64/kernel/entry-fpsimd.S\n> @@ -41,3 +41,20 @@ ENTRY(fpsimd_load_state)\n> \tfpsimd_restore x0, 8\n> \tret\n> ENDPROC(fpsimd_load_state)\n> +\n> +#ifdef CONFIG_ARM64_SVE\n> +ENTRY(sve_save_state)\n> +\tsve_save 0, x1, 2\n> +\tret\n> +ENDPROC(sve_save_state)\n> +\n> +ENTRY(sve_load_state)\n> +\tsve_load 0, x1, x2, 3\n> +\tret\n> +ENDPROC(sve_load_state)\n> +\n> +ENTRY(sve_get_vl)\n> +\t_sve_rdvl\t0, 1\n> +\tret\n> +ENDPROC(sve_get_vl)\n> +#endif /* CONFIG_ARM64_SVE */\n\n\n--\nAlex Bennée","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list libc-alpha@sourceware.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=sourceware.org\n\t(client-ip=209.132.180.131; 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","Cc":"linux-arm-kernel@lists.infradead.org,\n\tCatalin Marinas ,\n\tWill Deacon ,\n\tArd Biesheuvel ,\n\tSzabolcs Nagy ,\n\tRichard Sandiford ,\n\tkvmarm@lists.cs.columbia.edu, libc-alpha@sourceware.org,\n\tlinux-arch@vger.kernel.org","Subject":"Re: [PATCH v2 07/28] arm64/sve: Low-level SVE architectural state\n\tmanipulation functions","In-reply-to":"<1504198860-12951-8-git-send-email-Dave.Martin@arm.com>","Date":"Wed, 13 Sep 2017 16:39:40 +0100","Message-ID":"<87mv5ya9qb.fsf@linaro.org>","MIME-Version":"1.0","Content-Type":"text/plain; charset=utf-8","Content-Transfer-Encoding":"8bit"}}]