[{"id":1761483,"web_url":"http://patchwork.ozlabs.org/comment/1761483/","msgid":"<3371dbd2-9539-d746-0982-71112d5d98a0@samsung.com>","list_archive_url":null,"date":"2017-09-01T06:28:13","subject":"Re: [PATCH v3 2/2] dt-bindings: drm/bridge: Document Cadence DSI\n\tbridge bindings","submitter":{"id":47122,"url":"http://patchwork.ozlabs.org/api/people/47122/","name":"Andrzej Hajda","email":"a.hajda@samsung.com"},"content":"On 31.08.2017 17:55, Boris Brezillon wrote:\n> Document the bindings used for the Cadence DSI bridge.\n>\n> Signed-off-by: Boris Brezillon \n> ---\n> Changes in v3:\n> - Fix clock names in the example\n> - Document how to represent DSI devices that are controller through\n> an external bus like I2C or SPI\n>\n> Changes in v2:\n> - None\n> ---\n> .../bindings/display/bridge/cdns,dsi.txt | 109 +++++++++++++++++++++\n> 1 file changed, 109 insertions(+)\n> create mode 100644 Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt\n>\n> diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt b/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt\n> new file mode 100644\n> index 000000000000..c70008bd8c0d\n> --- /dev/null\n> +++ b/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt\n> @@ -0,0 +1,109 @@\n> +Cadence DSI bridge\n> +==================\n> +\n> +The Cadence DSI bridge is a DPI to DSI bridge supporting up to 4 DSI lanes.\n> +\n> +Required properties:\n> +- compatible: should be set to \"cdns,dsi-1.3.1\".\n> +- reg: physical base address and length of the controller's registers.\n> +- interrupts: interrupt line connected to the DSI bridge.\n> +- clocks: DSI bridge clocks.\n> +- clock-names: must contain \"pclk\" and \"sysclk\".\n> +- phys: phandle link to the MIPI D-PHY controller.\n> +- phy-names: must contain \"dphy\".\n> +- #address-cells: must be set to 1.\n> +- #size-cells: must be set to 0.\n> +\n> +Required subnodes:\n> +- ports: Ports as described in Documentation/devicetree/bindings/graph.txt.\n> + 2 ports are available:\n> + * port 0: this port is only needed if some of your DSI devices are\n> +\t controlled through an external bus like I2C or SPI. Can have at\n> +\t most 4 endpoints. The endpoint number is directly encoding the\n> +\t DSI virtual channel used by this device.\n> + * port 1: represents the DPI input.\n> + Other ports will be added later to support the new kind of inputs.\n\nI think usual practice is to use lower numbers for input ports, higher\nfor output ports.\nIs there a reason to do it this way?\n\nRegards\nAndrzej\n\n> +\n> +- one subnode per DSI device connected on the DSI bus. Each DSI device should\n> + contain a reg property encoding its virtual channel.\n> +\n> +Example:\n> +\n> +\tdsi0: dsi@fd0c0000 {\n> +\t\tcompatible = \"cdns,dsi-1.3.1\";\n> +\t\treg = <0x0 0xfd0c0000 0x0 0x1000>;\n> +\t\tclocks = <&pclk>, <&sysclk>;\n> +\t\tclock-names = \"pclk\", \"sysclk\";\n> +\t\tinterrupts = <1>;\n> +\t\tphys = <&dphy1>;\n> +\t\tphy-names = \"dphy\";\n> +\t\t#address-cells = <1>;\n> +\t\t#size-cells = <0>;\n> +\n> +\t\tports {\n> +\t\t\t#address-cells = <1>;\n> +\t\t\t#size-cells = <0>;\n> +\n> +\t\t\tport@1 {\n> +\t\t\t\treg = <1>;\n> +\t\t\t\tdsi0_dpi_input: endpoint {\n> +\t\t\t\t\tremote-endpoint = <&xxx_dpi_output>;\n> +\t\t\t\t};\n> +\t\t\t};\n> +\t\t};\n> +\n> +\t\tpanel: dsi-dev@0 {\n> +\t\t\tcompatible = \"\";\n> +\t\t\treg = <0>;\n> +\t\t};\n> +\t};\n> +\n> +or\n> +\n> +\tdsi0: dsi@fd0c0000 {\n> +\t\tcompatible = \"cdns,dsi\";\n> +\t\treg = <0x0 0xfd0c0000 0x0 0x1000>;\n> +\t\tclocks = <&pclk>, <&sysclk>;\n> +\t\tclock-names = \"pclk\", \"sysclk\";\n> +\t\tinterrupts = <1>;\n> +\t\tphys = <&dphy1>;\n> +\t\tphy-names = \"dphy\";\n> +\t\t#address-cells = <1>;\n> +\t\t#size-cells = <0>;\n> +\n> +\t\tports {\n> +\t\t\t#address-cells = <1>;\n> +\t\t\t#size-cells = <0>;\n> +\n> +\t\t\tport@0 {\n> +\t\t\t\treg = <0>;\n> +\t\t\t\t#address-cells = <1>;\n> +\t\t\t\t#size-cells = <0>;\n> +\n> +\t\t\t\tdsi0_output: endpoint@0 {\n> +\t\t\t\t\treg = <0>;\n> +\t\t\t\t\tremote-endpoint = <&dsi_panel_input>;\n> +\t\t\t\t};\n> +\t\t\t};\n> +\n> +\t\t\tport@1 {\n> +\t\t\t\treg = <1>;\n> +\t\t\t\tdsi0_dpi_input: endpoint {\n> +\t\t\t\t\tremote-endpoint = <&xxx_dpi_output>;\n> +\t\t\t\t};\n> +\t\t\t};\n> +\t\t};\n> +\t};\n> +\n> +\ti2c@xxx {\n> +\t\tpanel: panel@59 {\n> +\t\t\tcompatible = \"\";\n> +\t\t\treg = <0x59>;\n> +\n> +\t\t\tport {\n> +\t\t\t\tdsi_panel_input: endpoint {\n> +\t\t\t\t\tremote-endpoint = <&dsi0_output>;\n> +\t\t\t\t};\n> +\t\t\t};\n> +\t\t};\n> +\t};\n\n\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" 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[PATCH v3 2/2] dt-bindings: drm/bridge: Document Cadence DSI\n\tbridge bindings","submitter":{"id":63120,"url":"http://patchwork.ozlabs.org/api/people/63120/","name":"Boris Brezillon","email":"boris.brezillon@free-electrons.com"},"content":"Hi Andrzej,\n\nOn Fri, 01 Sep 2017 08:28:13 +0200\nAndrzej Hajda wrote:\n\n> On 31.08.2017 17:55, Boris Brezillon wrote:\n> > Document the bindings used for the Cadence DSI bridge.\n> >\n> > Signed-off-by: Boris Brezillon \n> > ---\n> > Changes in v3:\n> > - Fix clock names in the example\n> > - Document how to represent DSI devices that are controller through\n> > an external bus like I2C or SPI\n> >\n> > Changes in v2:\n> > - None\n> > ---\n> > .../bindings/display/bridge/cdns,dsi.txt | 109 +++++++++++++++++++++\n> > 1 file changed, 109 insertions(+)\n> > create mode 100644 Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt\n> >\n> > diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt b/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt\n> > new file mode 100644\n> > index 000000000000..c70008bd8c0d\n> > --- /dev/null\n> > +++ b/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt\n> > @@ -0,0 +1,109 @@\n> > +Cadence DSI bridge\n> > +==================\n> > +\n> > +The Cadence DSI bridge is a DPI to DSI bridge supporting up to 4 DSI lanes.\n> > +\n> > +Required properties:\n> > +- compatible: should be set to \"cdns,dsi-1.3.1\".\n> > +- reg: physical base address and length of the controller's registers.\n> > +- interrupts: interrupt line connected to the DSI bridge.\n> > +- clocks: DSI bridge clocks.\n> > +- clock-names: must contain \"pclk\" and \"sysclk\".\n> > +- phys: phandle link to the MIPI D-PHY controller.\n> > +- phy-names: must contain \"dphy\".\n> > +- #address-cells: must be set to 1.\n> > +- #size-cells: must be set to 0.\n> > +\n> > +Required subnodes:\n> > +- ports: Ports as described in Documentation/devicetree/bindings/graph.txt.\n> > + 2 ports are available:\n> > + * port 0: this port is only needed if some of your DSI devices are\n> > +\t controlled through an external bus like I2C or SPI. Can have at\n> > +\t most 4 endpoints. The endpoint number is directly encoding the\n> > +\t DSI virtual channel used by this device.\n> > + * port 1: represents the DPI input.\n> > + Other ports will be added later to support the new kind of inputs. \n> \n> I think usual practice is to use lower numbers for input ports, higher\n> for output ports.\n> Is there a reason to do it this way?\n\nThe main reason I did that is because we only have one output port and\ncan have 1, 2 or 3 input ports: one is the DPI and the 2 others are\ncalled SDI (some kind of serial input). I thought it would be better to\nhave all inputs using contiguous port numbers, and if we put inputs\nfirst that means having a hole between the input and output port (port 0\nwould be the DPI input and port 3 the DSI output).\n\nHonestly, that's just a detail, so if you prefer to have the input\nports start at 0 I'm fine with that.\n\nRegards,\n\nBoris\n\n\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xk9KG5QvYz9s7C\n\tfor ;\n\tFri, 1 Sep 2017 17:06:58 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751310AbdIAHG5 (ORCPT\n\t);\n\tFri, 1 Sep 2017 03:06:57 -0400","from mail.free-electrons.com ([62.4.15.54]:41969 \"EHLO\n\tmail.free-electrons.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751237AbdIAHG4 (ORCPT\n\t); Fri, 1 Sep 2017 03:06:56 -0400","by mail.free-electrons.com (Postfix, from userid 110)\n\tid 79E5E20970; Fri, 1 Sep 2017 09:06:54 +0200 (CEST)","from bbrezillon (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr\n\t[90.63.216.87])\n\tby mail.free-electrons.com (Postfix) with ESMTPSA id F37082096C;\n\tFri, 1 Sep 2017 09:06:53 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tmail.free-electrons.com","X-Spam-Level":"","X-Spam-Status":"No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT\n\tshortcircuit=ham autolearn=disabled version=3.4.0","Date":"Fri, 1 Sep 2017 09:06:54 +0200","From":"Boris Brezillon ","To":"Andrzej Hajda ","Cc":"David Airlie , Daniel Vetter ,\n\tdri-devel@lists.freedesktop.org, Archit Taneja , \n\tMark Rutland ,\n\tdevicetree@vger.kernel.org, Cyprian Wronka ,\n\tThomas Petazzoni ,\n\tPawel Moll ,\n\tIan Campbell ,\n\tSimon Hatliff ,\n\tTomi Valkeinen , Jyri Sarha ,\n\tAlan Douglas , Rob Herring ,\n\tKumar Gala ,\n\tMaxime Ripard ,\n\tRichard Sproul , Neil Webb ","Subject":"Re: [PATCH v3 2/2] dt-bindings: drm/bridge: Document Cadence DSI\n\tbridge bindings","Message-ID":"<20170901090654.343c7853@bbrezillon>","In-Reply-To":"<3371dbd2-9539-d746-0982-71112d5d98a0@samsung.com>","References":"<20170831155519.3704-1-boris.brezillon@free-electrons.com>\n\t\n\t<20170831155519.3704-2-boris.brezillon@free-electrons.com>\n\t<3371dbd2-9539-d746-0982-71112d5d98a0@samsung.com>","X-Mailer":"Claws Mail 3.14.1 (GTK+ 2.24.31; x86_64-pc-linux-gnu)","MIME-Version":"1.0","Content-Type":"text/plain; charset=US-ASCII","Content-Transfer-Encoding":"7bit","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1761499,"web_url":"http://patchwork.ozlabs.org/comment/1761499/","msgid":"<9cc75e8e-a300-1bdf-1aa4-c20b9aa77c42@samsung.com>","list_archive_url":null,"date":"2017-09-01T07:26:11","subject":"Re: [PATCH v3 2/2] dt-bindings: drm/bridge: Document Cadence DSI\n\tbridge bindings","submitter":{"id":47122,"url":"http://patchwork.ozlabs.org/api/people/47122/","name":"Andrzej Hajda","email":"a.hajda@samsung.com"},"content":"On 01.09.2017 09:06, Boris Brezillon wrote:\n> Hi Andrzej,\n>\n> On Fri, 01 Sep 2017 08:28:13 +0200\n> Andrzej Hajda wrote:\n>\n>> On 31.08.2017 17:55, Boris Brezillon wrote:\n>>> Document the bindings used for the Cadence DSI bridge.\n>>>\n>>> Signed-off-by: Boris Brezillon \n>>> ---\n>>> Changes in v3:\n>>> - Fix clock names in the example\n>>> - Document how to represent DSI devices that are controller through\n>>> an external bus like I2C or SPI\n>>>\n>>> Changes in v2:\n>>> - None\n>>> ---\n>>> .../bindings/display/bridge/cdns,dsi.txt | 109 +++++++++++++++++++++\n>>> 1 file changed, 109 insertions(+)\n>>> create mode 100644 Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt\n>>>\n>>> diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt b/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt\n>>> new file mode 100644\n>>> index 000000000000..c70008bd8c0d\n>>> --- /dev/null\n>>> +++ b/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt\n>>> @@ -0,0 +1,109 @@\n>>> +Cadence DSI bridge\n>>> +==================\n>>> +\n>>> +The Cadence DSI bridge is a DPI to DSI bridge supporting up to 4 DSI lanes.\n>>> +\n>>> +Required properties:\n>>> +- compatible: should be set to \"cdns,dsi-1.3.1\".\n>>> +- reg: physical base address and length of the controller's registers.\n>>> +- interrupts: interrupt line connected to the DSI bridge.\n>>> +- clocks: DSI bridge clocks.\n>>> +- clock-names: must contain \"pclk\" and \"sysclk\".\n>>> +- phys: phandle link to the MIPI D-PHY controller.\n>>> +- phy-names: must contain \"dphy\".\n>>> +- #address-cells: must be set to 1.\n>>> +- #size-cells: must be set to 0.\n>>> +\n>>> +Required subnodes:\n>>> +- ports: Ports as described in Documentation/devicetree/bindings/graph.txt.\n>>> + 2 ports are available:\n>>> + * port 0: this port is only needed if some of your DSI devices are\n>>> +\t controlled through an external bus like I2C or SPI. Can have at\n>>> +\t most 4 endpoints. The endpoint number is directly encoding the\n>>> +\t DSI virtual channel used by this device.\n>>> + * port 1: represents the DPI input.\n>>> + Other ports will be added later to support the new kind of inputs. \n>> I think usual practice is to use lower numbers for input ports, higher\n>> for output ports.\n>> Is there a reason to do it this way?\n> The main reason I did that is because we only have one output port and\n> can have 1, 2 or 3 input ports: one is the DPI and the 2 others are\n> called SDI (some kind of serial input). I thought it would be better to\n> have all inputs using contiguous port numbers, and if we put inputs\n> first that means having a hole between the input and output port (port 0\n> would be the DPI input and port 3 the DSI output).\n>\n> Honestly, that's just a detail, so if you prefer to have the input\n> ports start at 0 I'm fine with that.\n\nNo serious preferences, just curiosity. In fact port numbering schema is\nprivate thing of the device node.\n\nRegards\nAndrzej\n\n>\n> Regards,\n>\n> Boris\n>\n>\n>\n>\n>\n\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xk9lc1BRwz9s81\n\tfor ;\n\tFri, 1 Sep 2017 17:26:19 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751354AbdIAH0S (ORCPT\n\t);\n\tFri, 1 Sep 2017 03:26:18 -0400","from mailout2.w1.samsung.com ([210.118.77.12]:53857 \"EHLO\n\tmailout2.w1.samsung.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751345AbdIAH0Q (ORCPT\n\t); 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