[{"id":1761494,"web_url":"http://patchwork.ozlabs.org/comment/1761494/","msgid":"","list_archive_url":null,"date":"2017-09-01T07:12:35","subject":"Re: [Skiboot] [PATCH] opal-prd: Add support for runtime OCC reset\n\tin ZZ","submitter":{"id":1436,"url":"http://patchwork.ozlabs.org/api/people/1436/","name":"Mahesh J Salgaonkar","email":"mahesh@linux.vnet.ibm.com"},"content":"On 08/31/2017 01:56 PM, Shilpasri G Bhat wrote:\n> This patch handles OCC_RESET runtime events in host opal-prd and also\n> provides support for calling 'hostinterface->wakeup()' which is\n> required for doing the reset operation.\n> \n> Signed-off-by: Shilpasri G Bhat \n\nPatch looks good to me.\n\nReviewed-by: Mahesh Salgaonkar \n\nThanks,\n-Mahesh.\n\n> ---\n> - This is based on top of\n> https://urldefense.proofpoint.com/v2/url?u=https-3A__lists.ozlabs.org_pipermail_skiboot_2017-2DAugust_008585.html&d=DwIGaQ&c=jf_iaSHvJObTbx-siA1ZOg&r=Ai3L2JW-0UCviNlQjlx57cFb6BIPotR3Af4uhUMAl18&m=jdbkUAOfWaC23BaUscD1vtdb8M8P3i8ldTb2DFHAsv8&s=J0KYU3rfdqVey-5Gt6HogvWcW2b9MQWtby4yGhOGkAo&e= \n> which handles special wakeup in P9.\n> \n> core/hostservices.c | 28 +++++++++++++++--------\n> external/opal-prd/opal-prd.c | 51 +++++++++++++++++++++++++++++++++++++++++-\n> external/opal-prd/thunk.S | 2 +-\n> hw/occ.c | 53 +++++++++++++++++++++++++++++++++++++++++++-\n> hw/prd.c | 8 +++++++\n> include/opal-api.h | 10 +++++++++\n> include/skiboot.h | 2 ++\n> 7 files changed, 142 insertions(+), 12 deletions(-)\n> \n> diff --git a/core/hostservices.c b/core/hostservices.c\n> index 345c8c0..799b483 100644\n> --- a/core/hostservices.c\n> +++ b/core/hostservices.c\n> @@ -721,17 +721,23 @@ static int hservice_wakeup(uint32_t i_core, uint32_t i_mode)\n> \tstruct cpu_thread *cpu;\n> \tint rc = OPAL_SUCCESS;\n> \n> -\t/*\n> -\t * Mask out the top nibble of i_core since it may contain\n> -\t * 0x4 (which we use for XSCOM targeting)\n> -\t */\n> -\ti_core &= 0x0fffffff;\n> +\tswitch (proc_gen) {\n> +\tcase proc_gen_p8:\n> +\t\ti_core &= SPR_PIR_P8_MASK;\n> +\t\ti_core <<= 3;\n> +\t\tbreak;\n> +\tcase proc_gen_p9:\n> +\t\ti_core &= SPR_PIR_P9_MASK;\n> +\t\ti_core <<= 2;\n> +\t\tbreak;\n> +\tdefault:\n> +\t\treturn OPAL_UNSUPPORTED;\n> +\t}\n> \n> \t/* What do we need to do ? */\n> \tswitch(i_mode) {\n> \tcase 0: /* Assert special wakeup */\n> -\t\t/* XXX Assume P8 */\n> -\t\tcpu = find_cpu_by_pir(i_core << 3);\n> +\t\tcpu = find_cpu_by_pir(i_core);\n> \t\tif (!cpu)\n> \t\t\treturn OPAL_PARAMETER;\n> \t\tprlog(PR_DEBUG, \"HBRT: Special wakeup assert for core 0x%x,\"\n> @@ -742,8 +748,7 @@ static int hservice_wakeup(uint32_t i_core, uint32_t i_mode)\n> \t\t\tcpu->hbrt_spec_wakeup++;\n> \t\treturn rc;\n> \tcase 1: /* Deassert special wakeup */\n> -\t\t/* XXX Assume P8 */\n> -\t\tcpu = find_cpu_by_pir(i_core << 3);\n> +\t\tcpu = find_cpu_by_pir(i_core);\n> \t\tif (!cpu)\n> \t\t\treturn OPAL_PARAMETER;\n> \t\tprlog(PR_DEBUG, \"HBRT: Special wakeup release for core\"\n> @@ -774,6 +779,11 @@ static int hservice_wakeup(uint32_t i_core, uint32_t i_mode)\n> \t}\n> }\n> \n> +int core_special_wakeup(u32 core, u32 mode)\n> +{\n> +\treturn hservice_wakeup(core, mode);\n> +}\n> +\n> static struct host_interfaces hinterface = {\n> \t.interface_version = HOSTBOOT_RUNTIME_INTERFACE_VERSION,\n> \t.puts = hservice_puts,\n> diff --git a/external/opal-prd/opal-prd.c b/external/opal-prd/opal-prd.c\n> index a09a636..614b4b1 100644\n> --- a/external/opal-prd/opal-prd.c\n> +++ b/external/opal-prd/opal-prd.c\n> @@ -506,6 +506,25 @@ int hservice_i2c_write(uint64_t i_master, uint16_t i_devAddr,\n> \t\t\t i_offset, i_length, i_data);\n> }\n> \n> +int hservice_wakeup(u32 core, u32 mode)\n> +{\n> +\tint rc;\n> +\tstruct opal_prd_msg msg;\n> +\n> +\tmsg.hdr.type = OPAL_PRD_MSG_TYPE_CORE_SPECIAL_WAKEUP;\n> +\tmsg.hdr.size = htobe16(sizeof(msg));\n> +\tmsg.spl_wakeup.core = htobe32(core);\n> +\tmsg.spl_wakeup.mode = htobe32(mode);\n> +\n> +\trc = write(ctx->fd, &msg, sizeof(msg));\n> +\tif (rc != sizeof(msg)) {\n> +\t\tpr_log(LOG_ERR, \"FW: failed for core %x : %m\\n\", core);\n> +\t\treturn rc;\n> +\t}\n> +\n> +\treturn 0;\n> +}\n> +\n> static void ipmi_init(struct opal_prd_ctx *ctx)\n> {\n> \tinsert_module(\"ipmi_devintf\");\n> @@ -1353,9 +1372,24 @@ static int pm_complex_reset(uint64_t chip)\n> \treturn rc;\n> }\n> \n> +static bool is_fsp(void)\n> +{\n> +\tchar *path;\n> +\tint rc;\n> +\n> +\trc = asprintf(&path, \"%s/fsps\", devicetree_base);\n> +\tif (rc < 0) {\n> +\t\tpr_log(LOG_ERR, \"PRD: error creating '/fsps' path %m\");\n> +\t\treturn false;\n> +\t}\n> +\n> +\treturn access(path, F_OK) ? false : true;\n> +}\n> +\n> static int handle_msg_occ_reset(struct opal_prd_ctx *ctx,\n> \t\tstruct opal_prd_msg *msg)\n> {\n> +\tstruct opal_prd_msg omsg;\n> \tuint32_t proc;\n> \tint rc;\n> \n> @@ -1365,7 +1399,22 @@ static int handle_msg_occ_reset(struct opal_prd_ctx *ctx,\n> \n> \trc = pm_complex_reset(proc);\n> \n> -\treturn rc;\n> +\tif (!is_fsp())\n> +\t\treturn rc;\n> +\n> +\t/* Send only for zz */\n> +\tomsg.hdr.type = OPAL_PRD_MSG_TYPE_OCC_RESET_STATUS;\n> +\tomsg.hdr.size = htobe16(sizeof(omsg));\n> +\tomsg.occ_reset_status.chip = htobe64(proc);\n> +\tomsg.occ_reset_status.status = htobe64(rc);\n> +\n> +\trc = write(ctx->fd, &omsg, sizeof(omsg));\n> +\tif (rc != sizeof(omsg)) {\n> +\t\tpr_log(LOG_ERR, \"FW: Failed to send OCC_RESET status message: %m\");\n> +\t\treturn rc;\n> +\t}\n> +\n> +\treturn 0;\n> }\n> \n> static int handle_msg_firmware_notify(struct opal_prd_ctx *ctx,\n> diff --git a/external/opal-prd/thunk.S b/external/opal-prd/thunk.S\n> index cca5890..ee3d7c3 100644\n> --- a/external/opal-prd/thunk.S\n> +++ b/external/opal-prd/thunk.S\n> @@ -183,7 +183,7 @@ hinterface:\n> \tDISABLED_THUNK(hservice_lid_load)\n> \tDISABLED_THUNK(hservice_lid_unload)\n> \tCALLBACK_THUNK(hservice_get_reserved_mem)\n> -\tDISABLED_THUNK(hservice_wakeup)\n> +\tCALLBACK_THUNK(hservice_wakeup)\n> \tCALLBACK_THUNK(hservice_nanosleep)\n> \tDISABLED_THUNK(hservice_report_occ_failure)\n> \tCALLBACK_THUNK(hservice_clock_gettime)\n> diff --git a/hw/occ.c b/hw/occ.c\n> index 78c6a6a..a53ac92 100644\n> --- a/hw/occ.c\n> +++ b/hw/occ.c\n> @@ -1837,6 +1837,46 @@ out:\n> \treturn rc;\n> }\n> \n> +u32 last_seq_id;\n> +\n> +int fsp_occ_reset_status(u64 chipid, s64 status)\n> +{\n> +\tstruct fsp_msg *stat;\n> +\tint rc = OPAL_NO_MEM;\n> +\n> +\tif (status == 0) {\n> +\t\tstat = fsp_mkmsg(FSP_CMD_RESET_OCC_STAT, 2, 0, last_seq_id);\n> +\t\tif (!stat)\n> +\t\t\treturn rc;\n> +\n> +\t\trc = fsp_queue_msg(stat, fsp_freemsg);\n> +\t\tif (rc) {\n> +\t\t\tfsp_freemsg(stat);\n> +\t\t\tlog_simple_error(&e_info(OPAL_RC_OCC_RESET),\n> +\t\t\t\t\"OCC: Error %d queueing FSP OCC RESET STATUS message\\n\",\n> +\t\t\t\trc);\n> +\t\t}\n> +\t} else {\n> +\t\tstruct proc_chip *chip = get_chip(chipid);\n> +\n> +\t\tif (!chip)\n> +\t\t\treturn OPAL_PARAMETER;\n> +\n> +\t\tstat = fsp_mkmsg(FSP_CMD_RESET_OCC_STAT, 2,\n> +\t\t\t\t 0xfe00 | (chip->pcid & 0xff), last_seq_id);\n> +\t\tif (!stat)\n> +\t\t\treturn rc;\n> +\t\trc = fsp_queue_msg(stat, fsp_freemsg);\n> +\t\tif (rc) {\n> +\t\t\tfsp_freemsg(stat);\n> +\t\t\tlog_simple_error(&e_info(OPAL_RC_OCC_RESET),\n> +\t\t\t \"OCC: Error %d queueing FSP OCC RESET STATUS message\\n\",\n> +\t\t\t\trc);\n> +\t\t}\n> +\t}\n> +\treturn rc;\n> +}\n> +\n> static void occ_do_reset(u8 scope, u32 dbob_id, u32 seq_id)\n> {\n> \tstruct fsp_msg *rsp, *stat;\n> @@ -1877,7 +1917,18 @@ static void occ_do_reset(u8 scope, u32 dbob_id, u32 seq_id)\n> \t * FSP will request OCC to left in stopped state.\n> \t */\n> \n> -\trc = host_services_occ_stop();\n> +\tswitch (proc_gen) {\n> +\tcase proc_gen_p8:\n> +\t\trc = host_services_occ_stop();\n> +\t\tbreak;\n> +\tcase proc_gen_p9:\n> +\t\tlast_seq_id = seq_id;\n> +\t\tfor_each_chip(chip)\n> +\t\t\tprd_occ_reset(chip->id);\n> +\t\treturn;\n> +\tdefault:\n> +\t\treturn;\n> +\t}\n> \n> \t/* Handle fallback to preload */\n> \tif (rc == -ENOENT && chip->homer_base) {\n> diff --git a/hw/prd.c b/hw/prd.c\n> index d076c19..dcda9c8 100644\n> --- a/hw/prd.c\n> +++ b/hw/prd.c\n> @@ -418,6 +418,14 @@ static int64_t opal_prd_msg(struct opal_prd_msg *msg)\n> \tcase OPAL_PRD_MSG_TYPE_FIRMWARE_REQUEST:\n> \t\trc = prd_msg_handle_firmware_req(msg);\n> \t\tbreak;\n> +\tcase OPAL_PRD_MSG_TYPE_OCC_RESET_STATUS:\n> +\t\trc = fsp_occ_reset_status(msg->occ_reset_status.chip,\n> +\t\t\t\t\t msg->occ_reset_status.status);\n> +\t\tbreak;\n> +\tcase OPAL_PRD_MSG_TYPE_CORE_SPECIAL_WAKEUP:\n> +\t\trc = core_special_wakeup(msg->spl_wakeup.core,\n> +\t\t\t\t\t msg->spl_wakeup.mode);\n> +\t\tbreak;\n> \tdefault:\n> \t\trc = OPAL_UNSUPPORTED;\n> \t}\n> diff --git a/include/opal-api.h b/include/opal-api.h\n> index 0ff0db0..2f303f9 100644\n> --- a/include/opal-api.h\n> +++ b/include/opal-api.h\n> @@ -1052,6 +1052,8 @@ enum opal_prd_msg_type {\n> \tOPAL_PRD_MSG_TYPE_FIRMWARE_RESPONSE, /* HBRT <-- OPAL */\n> \tOPAL_PRD_MSG_TYPE_FIRMWARE_NOTIFY, /* HBRT <-- OPAL */\n> \tOPAL_PRD_MSG_TYPE_SBE_PASSTHROUGH, /* HBRT <-- OPAL */\n> +\tOPAL_PRD_MSG_TYPE_OCC_RESET_STATUS, /* HBRT --> OPAL */\n> +\tOPAL_PRD_MSG_TYPE_CORE_SPECIAL_WAKEUP, /* HBRT --> OPAL */\n> };\n> \n> struct opal_prd_msg_header {\n> @@ -1099,6 +1101,14 @@ struct opal_prd_msg {\n> \t\tstruct {\n> \t\t\t__be64\tchip;\n> \t\t} sbe_passthrough;\n> +\t\tstruct {\n> +\t\t\t__be64 chip;\n> +\t\t\t__be64 status; /* 0 SUCCESS */\n> +\t\t} occ_reset_status;\n> +\t\tstruct {\n> +\t\t\t__be32 core;\n> +\t\t\t__be32 mode;\n> +\t\t} spl_wakeup;\n> \t};\n> };\n> \n> diff --git a/include/skiboot.h b/include/skiboot.h\n> index 4b7d519..5eb9188 100644\n> --- a/include/skiboot.h\n> +++ b/include/skiboot.h\n> @@ -317,4 +317,6 @@ extern int occ_sensor_group_clear(u32 group_hndl, int token);\n> extern void occ_add_sensor_groups(struct dt_node *sg, u32 *phandles,\n> \t\t\t\t int nr_phandles, int chipid);\n> \n> +extern int fsp_occ_reset_status(u64 chipid, s64 status);\n> +extern int core_special_wakeup(u32 core, u32 mode);\n> #endif /* __SKIBOOT_H */\n>","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","skiboot@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","skiboot@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xk9S70JGcz9s7C\n\tfor ;\n\tFri, 1 Sep 2017 17:12:55 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xk9S66FywzDqm8\n\tfor ;\n\tFri, 1 Sep 2017 17:12:54 +1000 (AEST)","from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com\n\t[148.163.158.5])\n\t(using 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Violators will be prosecuted; \n\tFri, 1 Sep 2017 17:12:38 +1000","from d23av01.au.ibm.com (d23av01.au.ibm.com [9.190.234.96])\n\tby d23relay08.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id\n\tv817Ccoe37945478\n\tfor ; Fri, 1 Sep 2017 17:12:38 +1000","from d23av01.au.ibm.com (localhost [127.0.0.1])\n\tby d23av01.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id\n\tv817CcFj012569\n\tfor ; Fri, 1 Sep 2017 17:12:38 +1000","from [9.202.5.157] ([9.202.5.157])\n\tby d23av01.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id\n\tv817CZGK012518; Fri, 1 Sep 2017 17:12:36 +1000"],"To":"Shilpasri G Bhat ,\n\tskiboot@lists.ozlabs.org","References":"<1504168018-30755-1-git-send-email-shilpa.bhat@linux.vnet.ibm.com>","From":"Mahesh Jagannath Salgaonkar ","Date":"Fri, 1 Sep 2017 12:42:35 +0530","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"<1504168018-30755-1-git-send-email-shilpa.bhat@linux.vnet.ibm.com>","Content-Language":"en-MW","X-TM-AS-MML":"disable","x-cbid":"17090107-1617-0000-0000-000001FD4FCF","X-IBM-AV-DETECTION":"SAVI=unused REMOTE=unused XFE=unused","x-cbparentid":"17090107-1618-0000-0000-00004849CFAC","Message-Id":"","X-Proofpoint-Virus-Version":"vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-09-01_02:, , signatures=0","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n\tspamscore=0 suspectscore=0\n\tmalwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam\n\tadjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000\n\tdefinitions=main-1709010106","Subject":"Re: [Skiboot] [PATCH] opal-prd: Add support for runtime OCC reset\n\tin ZZ","X-BeenThere":"skiboot@lists.ozlabs.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"Mailing list for skiboot development ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"ego@linux.vnet.ibm.com","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org","Sender":"\"Skiboot\"\n\t"}},{"id":1762692,"web_url":"http://patchwork.ozlabs.org/comment/1762692/","msgid":"<675c3101-865f-3fa2-6ce8-5d6bd2d4a716@linux.vnet.ibm.com>","list_archive_url":null,"date":"2017-09-04T14:32:13","subject":"Re: [Skiboot] [PATCH] opal-prd: Add support for runtime OCC reset\n\tin ZZ","submitter":{"id":22361,"url":"http://patchwork.ozlabs.org/api/people/22361/","name":"Vasant Hegde","email":"hegdevasant@linux.vnet.ibm.com"},"content":"On 08/31/2017 01:56 PM, Shilpasri G Bhat wrote:\n> This patch handles OCC_RESET runtime events in host opal-prd and also\n> provides support for calling 'hostinterface->wakeup()' which is\n> required for doing the reset operation.\n>\n> Signed-off-by: Shilpasri G Bhat \n> ---\n> - This is based on top of\n> https://lists.ozlabs.org/pipermail/skiboot/2017-August/008585.html\n> which handles special wakeup in P9.\n>\n> core/hostservices.c | 28 +++++++++++++++--------\n> external/opal-prd/opal-prd.c | 51 +++++++++++++++++++++++++++++++++++++++++-\n> external/opal-prd/thunk.S | 2 +-\n> hw/occ.c | 53 +++++++++++++++++++++++++++++++++++++++++++-\n> hw/prd.c | 8 +++++++\n> include/opal-api.h | 10 +++++++++\n> include/skiboot.h | 2 ++\n> 7 files changed, 142 insertions(+), 12 deletions(-)\n>\n\n.../...\n\n> diff --git a/external/opal-prd/thunk.S b/external/opal-prd/thunk.S\n> index cca5890..ee3d7c3 100644\n> --- a/external/opal-prd/thunk.S\n> +++ b/external/opal-prd/thunk.S\n> @@ -183,7 +183,7 @@ hinterface:\n> \tDISABLED_THUNK(hservice_lid_load)\n> \tDISABLED_THUNK(hservice_lid_unload)\n> \tCALLBACK_THUNK(hservice_get_reserved_mem)\n> -\tDISABLED_THUNK(hservice_wakeup)\n> +\tCALLBACK_THUNK(hservice_wakeup)\n\nAnd you should detect service processor type and disable wakeup interface on BMC \nsystem.\n(similar to pnor_read call. See run_prd_daemon()).\n\n> diff --git a/hw/occ.c b/hw/occ.c\n> index 78c6a6a..a53ac92 100644\n> --- a/hw/occ.c\n> +++ b/hw/occ.c\n> @@ -1837,6 +1837,46 @@ out:\n> \treturn rc;\n> }\n>\n> +u32 last_seq_id;\n> +\n> +int fsp_occ_reset_status(u64 chipid, s64 status)\n> +{\n> +\tstruct fsp_msg *stat;\n> +\tint rc = OPAL_NO_MEM;\n> +\n> +\tif (status == 0) {\n\nHow about something like below :\n\tif (status == 0)\n\t\tret = 0;\n\telse\n\t\tret = 0xfe00 | (chip->pcid & 0xff);\n\nAnd then just call fsp_mkmsg. That way you can avoid duplicate code.\n\n-Vasant\n\n> +\t\tstat = fsp_mkmsg(FSP_CMD_RESET_OCC_STAT, 2, 0, last_seq_id);\n> +\t\tif (!stat)\n> +\t\t\treturn rc;\n> +\n> +\t\trc = fsp_queue_msg(stat, fsp_freemsg);\n> +\t\tif (rc) {\n> +\t\t\tfsp_freemsg(stat);\n> +\t\t\tlog_simple_error(&e_info(OPAL_RC_OCC_RESET),\n> +\t\t\t\t\"OCC: Error %d queueing FSP OCC RESET STATUS message\\n\",\n> +\t\t\t\trc);\n> +\t\t}\n> +\t} else {\n> +\t\tstruct proc_chip *chip = get_chip(chipid);\n> +\n> +\t\tif (!chip)\n> +\t\t\treturn OPAL_PARAMETER;\n> +\n> +\t\tstat = fsp_mkmsg(FSP_CMD_RESET_OCC_STAT, 2,\n> +\t\t\t\t 0xfe00 | (chip->pcid & 0xff), last_seq_id);\n> +\t\tif (!stat)\n> +\t\t\treturn rc;\n> +\t\trc = fsp_queue_msg(stat, fsp_freemsg);\n> +\t\tif (rc) {\n> +\t\t\tfsp_freemsg(stat);\n> +\t\t\tlog_simple_error(&e_info(OPAL_RC_OCC_RESET),\n> +\t\t\t \"OCC: Error %d queueing FSP OCC RESET STATUS message\\n\",\n> +\t\t\t\trc);\n> +\t\t}\n> +\t}\n> +\treturn rc;\n> +}","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","skiboot@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","skiboot@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xmC3x0b9yz9t2R\n\tfor ;\n\tTue, 5 Sep 2017 00:32:29 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xmC3w5yCdzDqlM\n\tfor ;\n\tTue, 5 Sep 2017 00:32:28 +1000 (AEST)","from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com\n\t[148.163.156.1])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xmC3s0pvhzDqZx\n\tfor ; Tue, 5 Sep 2017 00:32:24 +1000 (AEST)","from pps.filterd (m0098396.ppops.net [127.0.0.1])\n\tby mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv84EVOIV023274\n\tfor ; Mon, 4 Sep 2017 10:32:22 -0400","from e23smtp05.au.ibm.com (e23smtp05.au.ibm.com [202.81.31.147])\n\tby mx0a-001b2d01.pphosted.com with ESMTP id 2cs7rhkv7x-1\n\t(version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT)\n\tfor ; Mon, 04 Sep 2017 10:32:22 -0400","from localhost\n\tby e23smtp05.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! 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