[{"id":1769524,"web_url":"http://patchwork.ozlabs.org/comment/1769524/","msgid":"<20170916002013.GD21016@localhost.localdomain>","list_archive_url":null,"date":"2017-09-16T00:20:13","subject":"Re: [Qemu-devel] [PATCH v2 7/7] mips: update mips_cpu_list() to use\n\tobject_class_get_list()","submitter":{"id":195,"url":"http://patchwork.ozlabs.org/api/people/195/","name":"Eduardo Habkost","email":"ehabkost@redhat.com"},"content":"On Wed, Aug 30, 2017 at 07:52:25PM -0300, Philippe Mathieu-Daudé wrote:\n> while here, move it from translate_init.c to helper.c\n> \n> Signed-off-by: Philippe Mathieu-Daudé \n> Tested-by: Igor Mammedov \n> Tested-by: James Hogan \n> ---\n> target/mips/helper.c | 46 ++++++++++++++++++++++++++++++++++++++++++++\n> target/mips/translate_init.c | 10 ----------\n> 2 files changed, 46 insertions(+), 10 deletions(-)\n> \n> diff --git a/target/mips/helper.c b/target/mips/helper.c\n> index ea076261af..8d12b0088a 100644\n> --- a/target/mips/helper.c\n> +++ b/target/mips/helper.c\n> @@ -1093,3 +1093,49 @@ void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,\n> \n> cpu_loop_exit_restore(cs, pc);\n> }\n> +\n> +/* Sort alphabetically by type name, except for \"any\". */\n> +static gint mips_cpu_list_compare(gconstpointer a, gconstpointer b)\n> +{\n> + ObjectClass *class_a = (ObjectClass *)a;\n> + ObjectClass *class_b = (ObjectClass *)b;\n> + const char *name_a, *name_b;\n> +\n> + name_a = object_class_get_name(class_a);\n> + name_b = object_class_get_name(class_b);\n> + if (strcmp(name_a, \"any-\" TYPE_MIPS_CPU) == 0) {\n> + return 1;\n> + } else if (strcmp(name_b, \"any-\" TYPE_MIPS_CPU) == 0) {\n> + return -1;\n> + } else {\n> + return strcmp(name_a, name_b);\n> + }\n\nThis works, but I'd prefer to do like x86 and have a\nMIPSCPUClass::ordering field.\n\n(Or, even better: to add a generic CPUClass::ordering field so\nall architectures can use the same method to order the model\nlist)\n\n> +}\n> +\n> +static void mips_cpu_list_entry(gpointer data, gpointer user_data)\n> +{\n> + ObjectClass *oc = data;\n> + CPUListState *s = user_data;\n> + const char *typename;\n> + char *name;\n> +\n> + typename = object_class_get_name(oc);\n> + name = g_strndup(typename, strlen(typename) - strlen(\"-\" TYPE_MIPS_CPU));\n> + (*s->cpu_fprintf)(s->file, \" %s\\n\", name);\n> + g_free(name);\n> +}\n> +\n> +void mips_cpu_list(FILE *f, fprintf_function cpu_fprintf)\n> +{\n> + CPUListState s = {\n> + .file = f,\n> + .cpu_fprintf = cpu_fprintf,\n> + };\n> + GSList *list;\n> +\n> + list = object_class_get_list(TYPE_MIPS_CPU, false);\n> + list = g_slist_sort(list, mips_cpu_list_compare);\n> + (*cpu_fprintf)(f, \"Available CPUs:\\n\");\n> + g_slist_foreach(list, mips_cpu_list_entry, &s);\n> + g_slist_free(list);\n> +}\n\nI think it's about time we implement a generic mechanism to list\nCPU models using the QOM hierarchy, but this is out of the scope\nof this series.\n\n\n> diff --git a/target/mips/translate_init.c b/target/mips/translate_init.c\n> index 8bbded46c4..b75f4c9065 100644\n> --- a/target/mips/translate_init.c\n> +++ b/target/mips/translate_init.c\n> @@ -767,16 +767,6 @@ static const mips_def_t *cpu_mips_find_by_name (const char *name)\n> return NULL;\n> }\n> \n> -void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf)\n> -{\n> - int i;\n> -\n> - for (i = 0; i < ARRAY_SIZE(mips_defs); i++) {\n> - (*cpu_fprintf)(f, \"MIPS '%s'\\n\",\n> - mips_defs[i].name);\n> - }\n> -}\n> -\n> #ifndef CONFIG_USER_ONLY\n> static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def)\n> {\n> -- \n> 2.14.1\n> \n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ext-mx05.extmail.prod.ext.phx2.redhat.com;\n\tdmarc=none (p=none dis=none) header.from=redhat.com","ext-mx05.extmail.prod.ext.phx2.redhat.com;\n\tspf=fail smtp.mailfrom=ehabkost@redhat.com"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xvCbd35DYz9sPm\n\tfor ;\n\tSat, 16 Sep 2017 10:20:45 +1000 (AEST)","from localhost ([::1]:55466 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dt0qh-0005XH-Je\n\tfor incoming@patchwork.ozlabs.org; Fri, 15 Sep 2017 20:20:43 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:39103)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1dt0qL-0005Wt-6O\n\tfor qemu-devel@nongnu.org; Fri, 15 Sep 2017 20:20:22 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1dt0qI-0007hx-0y\n\tfor qemu-devel@nongnu.org; Fri, 15 Sep 2017 20:20:21 -0400","from mx1.redhat.com ([209.132.183.28]:39698)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from ) id 1dt0qH-0007hf-OF\n\tfor qemu-devel@nongnu.org; Fri, 15 Sep 2017 20:20:17 -0400","from smtp.corp.redhat.com\n\t(int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby mx1.redhat.com (Postfix) with ESMTPS id D062A20271;\n\tSat, 16 Sep 2017 00:20:16 +0000 (UTC)","from localhost (ovpn-116-24.gru2.redhat.com [10.97.116.24])\n\tby smtp.corp.redhat.com (Postfix) with ESMTP id 8637917BA0;\n\tSat, 16 Sep 2017 00:20:14 +0000 (UTC)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mx1.redhat.com D062A20271","Date":"Fri, 15 Sep 2017 21:20:13 -0300","From":"Eduardo Habkost ","To":"Philippe =?iso-8859-1?q?Mathieu-Daud=E9?= ","Message-ID":"<20170916002013.GD21016@localhost.localdomain>","References":"<20170830225225.27925-1-f4bug@amsat.org>\n\t<20170830225225.27925-8-f4bug@amsat.org>","MIME-Version":"1.0","Content-Type":"text/plain; charset=iso-8859-1","Content-Disposition":"inline","In-Reply-To":"<20170830225225.27925-8-f4bug@amsat.org>","X-Fnord":"you can see the fnord","User-Agent":"Mutt/1.8.3 (2017-05-23)","X-Scanned-By":"MIMEDefang 2.79 on 10.5.11.12","X-Greylist":"Sender IP whitelisted, not delayed by milter-greylist-4.5.16\n\t(mx1.redhat.com [10.5.110.29]);\n\tSat, 16 Sep 2017 00:20:17 +0000 (UTC)","Content-Transfer-Encoding":"quoted-printable","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]","X-Received-From":"209.132.183.28","Subject":"Re: [Qemu-devel] [PATCH v2 7/7] mips: update mips_cpu_list() to use\n\tobject_class_get_list()","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Thomas Huth , James Hogan ,\n\tqemu-devel@nongnu.org, Yongbok Kim , \n\t=?iso-8859-1?q?Herv=E9?= Poussineau ,\n\tMarcel Apfelbaum ,\n\tIgor Mammedov , Aurelien Jarno\n\t","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1769814,"web_url":"http://patchwork.ozlabs.org/comment/1769814/","msgid":"","list_archive_url":null,"date":"2017-09-17T22:40:56","subject":"Re: [Qemu-devel] [PATCH v2 7/7] mips: update mips_cpu_list() to use\n\tobject_class_get_list()","submitter":{"id":70924,"url":"http://patchwork.ozlabs.org/api/people/70924/","name":"Philippe Mathieu-Daudé","email":"f4bug@amsat.org"},"content":"On 09/15/2017 09:20 PM, Eduardo Habkost wrote:\n> On Wed, Aug 30, 2017 at 07:52:25PM -0300, Philippe Mathieu-Daudé wrote:\n>> while here, move it from translate_init.c to helper.c\n>>\n>> Signed-off-by: Philippe Mathieu-Daudé \n>> Tested-by: Igor Mammedov \n>> Tested-by: James Hogan \n>> ---\n>> target/mips/helper.c | 46 ++++++++++++++++++++++++++++++++++++++++++++\n>> target/mips/translate_init.c | 10 ----------\n>> 2 files changed, 46 insertions(+), 10 deletions(-)\n>>\n>> diff --git a/target/mips/helper.c b/target/mips/helper.c\n>> index ea076261af..8d12b0088a 100644\n>> --- a/target/mips/helper.c\n>> +++ b/target/mips/helper.c\n>> @@ -1093,3 +1093,49 @@ void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,\n>> \n>> cpu_loop_exit_restore(cs, pc);\n>> }\n>> +\n>> +/* Sort alphabetically by type name, except for \"any\". */\n>> +static gint mips_cpu_list_compare(gconstpointer a, gconstpointer b)\n>> +{\n>> + ObjectClass *class_a = (ObjectClass *)a;\n>> + ObjectClass *class_b = (ObjectClass *)b;\n>> + const char *name_a, *name_b;\n>> +\n>> + name_a = object_class_get_name(class_a);\n>> + name_b = object_class_get_name(class_b);\n>> + if (strcmp(name_a, \"any-\" TYPE_MIPS_CPU) == 0) {\n>> + return 1;\n>> + } else if (strcmp(name_b, \"any-\" TYPE_MIPS_CPU) == 0) {\n>> + return -1;\n>> + } else {\n>> + return strcmp(name_a, name_b);\n>> + }\n> \n> This works, but I'd prefer to do like x86 and have a\n> MIPSCPUClass::ordering field.\n> \n> (Or, even better: to add a generic CPUClass::ordering field so\n> all architectures can use the same method to order the model\n> list)\n\nI'll drop this patch, it is not required to QOMify MIPS CPU, and let \nanother series properly refactor CPUClass::ordering.\n\n> \n>> +}\n>> +\n>> +static void mips_cpu_list_entry(gpointer data, gpointer user_data)\n>> +{\n>> + ObjectClass *oc = data;\n>> + CPUListState *s = user_data;\n>> + const char *typename;\n>> + char *name;\n>> +\n>> + typename = object_class_get_name(oc);\n>> + name = g_strndup(typename, strlen(typename) - strlen(\"-\" TYPE_MIPS_CPU));\n>> + (*s->cpu_fprintf)(s->file, \" %s\\n\", name);\n>> + g_free(name);\n>> +}\n>> +\n>> +void mips_cpu_list(FILE *f, fprintf_function cpu_fprintf)\n>> +{\n>> + CPUListState s = {\n>> + .file = f,\n>> + .cpu_fprintf = cpu_fprintf,\n>> + };\n>> + GSList *list;\n>> +\n>> + list = object_class_get_list(TYPE_MIPS_CPU, false);\n>> + list = g_slist_sort(list, mips_cpu_list_compare);\n>> + (*cpu_fprintf)(f, \"Available CPUs:\\n\");\n>> + g_slist_foreach(list, mips_cpu_list_entry, &s);\n>> + g_slist_free(list);\n>> +}\n> \n> I think it's about time we implement a generic mechanism to list\n> CPU models using the QOM hierarchy, but this is out of the scope\n> of this series.\n> \n> \n>> diff --git a/target/mips/translate_init.c b/target/mips/translate_init.c\n>> index 8bbded46c4..b75f4c9065 100644\n>> --- a/target/mips/translate_init.c\n>> +++ b/target/mips/translate_init.c\n>> @@ -767,16 +767,6 @@ static const mips_def_t *cpu_mips_find_by_name (const char *name)\n>> return NULL;\n>> }\n>> \n>> -void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf)\n>> -{\n>> - int i;\n>> -\n>> - for (i = 0; i < ARRAY_SIZE(mips_defs); i++) {\n>> - (*cpu_fprintf)(f, \"MIPS '%s'\\n\",\n>> - mips_defs[i].name);\n>> - }\n>> -}\n>> -\n>> #ifndef CONFIG_USER_ONLY\n>> static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def)\n>> {\n>> -- \n>> 2.14.1\n>>\n>>\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"iTZy3cL5\"; dkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xwPJZ0P5Cz9s76\n\tfor ;\n\tMon, 18 Sep 2017 08:41:49 +1000 (AEST)","from localhost ([::1]:33877 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dtiG3-0002Wd-OJ\n\tfor incoming@patchwork.ozlabs.org; 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\n\tSun, 17 Sep 2017 15:41:05 -0700 (PDT)","To":"Eduardo Habkost ","References":"<20170830225225.27925-1-f4bug@amsat.org>\n\t<20170830225225.27925-8-f4bug@amsat.org>\n\t<20170916002013.GD21016@localhost.localdomain>","From":"=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= ","Message-ID":"","Date":"Sun, 17 Sep 2017 19:40:56 -0300","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<20170916002013.GD21016@localhost.localdomain>","Content-Type":"text/plain; charset=utf-8; format=flowed","Content-Language":"en-US","Content-Transfer-Encoding":"8bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400d:c0d::242","Subject":"Re: [Qemu-devel] [PATCH v2 7/7] mips: update mips_cpu_list() to use\n\tobject_class_get_list()","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Thomas Huth , James Hogan ,\n\tqemu-devel@nongnu.org, Yongbok Kim , \n\t=?utf-8?q?Herv=C3=A9_Poussineau?= ,\n\tMarcel Apfelbaum ,\n\tIgor Mammedov , Aurelien Jarno\n\t","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}}]