[{"id":1761477,"web_url":"http://patchwork.ozlabs.org/comment/1761477/","msgid":"<1504245709.4974.75.camel@kernel.crashing.org>","date":"2017-09-01T06:01:49","subject":"Re: [PATCH v3 6/8] powerpc/xive: introduce H_INT_ESB hcall","submitter":{"id":38,"url":"http://patchwork.ozlabs.org/api/people/38/","name":"Benjamin Herrenschmidt","email":"benh@kernel.crashing.org"},"content":"On Wed, 2017-08-30 at 21:46 +0200, Cédric Le Goater wrote:\n> The H_INT_ESB hcall() is used to issue a load or store to the ESB page\n> instead of using the MMIO pages. This can be used as a workaround on\n> some HW issues. The OS knows that this hcall should be used on an\n> interrupt source when the ESB hcall flag is set to 1 in the hcall\n> H_INT_GET_SOURCE_INFO.\n> \n> To maintain the frontier between the xive frontend and backend, we\n> introduce a new xive operation 'esb_rw' to be used in the routines\n> doing memory accesses on the ESBs.\n> \n> Signed-off-by: Cédric Le Goater \n\nAcked-by: Benjamin Herrenschmidt \n\n---\n> arch/powerpc/include/asm/xive.h | 1 +\n> arch/powerpc/sysdev/xive/common.c | 10 ++++++--\n> arch/powerpc/sysdev/xive/spapr.c | 44 +++++++++++++++++++++++++++++++-\n> arch/powerpc/sysdev/xive/xive-internal.h | 1 +\n> 4 files changed, 53 insertions(+), 3 deletions(-)\n> \n> diff --git a/arch/powerpc/include/asm/xive.h b/arch/powerpc/include/asm/xive.h\n> index 64ec9bbcf03e..371fbebf1ec9 100644\n> --- a/arch/powerpc/include/asm/xive.h\n> +++ b/arch/powerpc/include/asm/xive.h\n> @@ -56,6 +56,7 @@ struct xive_irq_data {\n> #define XIVE_IRQ_FLAG_SHIFT_BUG\t0x04\n> #define XIVE_IRQ_FLAG_MASK_FW\t0x08\n> #define XIVE_IRQ_FLAG_EOI_FW\t0x10\n> +#define XIVE_IRQ_FLAG_H_INT_ESB\t0x20\n> \n> #define XIVE_INVALID_CHIP_ID\t-1\n> \n> diff --git a/arch/powerpc/sysdev/xive/common.c b/arch/powerpc/sysdev/xive/common.c\n> index ac5f18a66742..8fd58773c241 100644\n> --- a/arch/powerpc/sysdev/xive/common.c\n> +++ b/arch/powerpc/sysdev/xive/common.c\n> @@ -198,7 +198,10 @@ static u8 xive_esb_read(struct xive_irq_data *xd, u32 offset)\n> \tif (xd->flags & XIVE_IRQ_FLAG_SHIFT_BUG)\n> \t\toffset |= offset << 4;\n> \n> -\tval = in_be64(xd->eoi_mmio + offset);\n> +\tif ((xd->flags & XIVE_IRQ_FLAG_H_INT_ESB) && xive_ops->esb_rw)\n> +\t\tval = xive_ops->esb_rw(xd->hw_irq, offset, 0, 0);\n> +\telse\n> +\t\tval = in_be64(xd->eoi_mmio + offset);\n> \n> \treturn (u8)val;\n> }\n> @@ -209,7 +212,10 @@ static void xive_esb_write(struct xive_irq_data *xd, u32 offset, u64 data)\n> \tif (xd->flags & XIVE_IRQ_FLAG_SHIFT_BUG)\n> \t\toffset |= offset << 4;\n> \n> -\tout_be64(xd->eoi_mmio + offset, data);\n> +\tif ((xd->flags & XIVE_IRQ_FLAG_H_INT_ESB) && xive_ops->esb_rw)\n> +\t\txive_ops->esb_rw(xd->hw_irq, offset, data, 1);\n> +\telse\n> +\t\tout_be64(xd->eoi_mmio + offset, data);\n> }\n> \n> #ifdef CONFIG_XMON\n> diff --git a/arch/powerpc/sysdev/xive/spapr.c b/arch/powerpc/sysdev/xive/spapr.c\n> index 0fcae7504353..43e9eeb0d39f 100644\n> --- a/arch/powerpc/sysdev/xive/spapr.c\n> +++ b/arch/powerpc/sysdev/xive/spapr.c\n> @@ -224,7 +224,46 @@ static long plpar_int_sync(unsigned long flags, unsigned long lisn)\n> \treturn 0;\n> }\n> \n> -#define XIVE_SRC_H_INT_ESB (1ull << (63 - 60)) /* TODO */\n> +#define XIVE_ESB_FLAG_STORE (1ull << (63 - 63))\n> +\n> +static long plpar_int_esb(unsigned long flags,\n> +\t\t\t unsigned long lisn,\n> +\t\t\t unsigned long offset,\n> +\t\t\t unsigned long in_data,\n> +\t\t\t unsigned long *out_data)\n> +{\n> +\tunsigned long retbuf[PLPAR_HCALL_BUFSIZE];\n> +\tlong rc;\n> +\n> +\tpr_devel(\"H_INT_ESB flags=%lx lisn=%lx offset=%lx in=%lx\\n\",\n> +\t\tflags, lisn, offset, in_data);\n> +\n> +\trc = plpar_hcall(H_INT_ESB, retbuf, flags, lisn, offset, in_data);\n> +\tif (rc) {\n> +\t\tpr_err(\"H_INT_ESB lisn=%ld offset=%ld returned %ld\\n\",\n> +\t\t lisn, offset, rc);\n> +\t\treturn rc;\n> +\t}\n> +\n> +\t*out_data = retbuf[0];\n> +\n> +\treturn 0;\n> +}\n> +\n> +static u64 xive_spapr_esb_rw(u32 lisn, u32 offset, u64 data, bool write)\n> +{\n> +\tunsigned long read_data;\n> +\tlong rc;\n> +\n> +\trc = plpar_int_esb(write ? XIVE_ESB_FLAG_STORE : 0,\n> +\t\t\t lisn, offset, data, &read_data);\n> +\tif (rc)\n> +\t\treturn -1;\n> +\n> +\treturn write ? 0 : read_data;\n> +}\n> +\n> +#define XIVE_SRC_H_INT_ESB (1ull << (63 - 60))\n> #define XIVE_SRC_LSI (1ull << (63 - 61))\n> #define XIVE_SRC_TRIGGER (1ull << (63 - 62))\n> #define XIVE_SRC_STORE_EOI (1ull << (63 - 63))\n> @@ -244,6 +283,8 @@ static int xive_spapr_populate_irq_data(u32 hw_irq, struct xive_irq_data *data)\n> \tif (rc)\n> \t\treturn -EINVAL;\n> \n> +\tif (flags & XIVE_SRC_H_INT_ESB)\n> +\t\tdata->flags |= XIVE_IRQ_FLAG_H_INT_ESB;\n> \tif (flags & XIVE_SRC_STORE_EOI)\n> \t\tdata->flags |= XIVE_IRQ_FLAG_STORE_EOI;\n> \tif (flags & XIVE_SRC_LSI)\n> @@ -487,6 +528,7 @@ static const struct xive_ops xive_spapr_ops = {\n> \t.setup_cpu\t\t= xive_spapr_setup_cpu,\n> \t.teardown_cpu\t\t= xive_spapr_teardown_cpu,\n> \t.sync_source\t\t= xive_spapr_sync_source,\n> +\t.esb_rw\t\t\t= xive_spapr_esb_rw,\n> #ifdef CONFIG_SMP\n> \t.get_ipi\t\t= xive_spapr_get_ipi,\n> \t.put_ipi\t\t= xive_spapr_put_ipi,\n> diff --git a/arch/powerpc/sysdev/xive/xive-internal.h b/arch/powerpc/sysdev/xive/xive-internal.h\n> index dd1e2022cce4..f34abed0c05f 100644\n> --- a/arch/powerpc/sysdev/xive/xive-internal.h\n> +++ b/arch/powerpc/sysdev/xive/xive-internal.h\n> @@ -47,6 +47,7 @@ struct xive_ops {\n> \tvoid\t(*update_pending)(struct xive_cpu *xc);\n> \tvoid\t(*eoi)(u32 hw_irq);\n> \tvoid\t(*sync_source)(u32 hw_irq);\n> +\tu64\t(*esb_rw)(u32 hw_irq, u32 offset, u64 data, bool write);\n> #ifdef CONFIG_SMP\n> \tint\t(*get_ipi)(unsigned int cpu, struct xive_cpu *xc);\n> \tvoid\t(*put_ipi)(unsigned int cpu, struct xive_cpu *xc);","headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xk7w73Sbkz9s8J\n\tfor ;\n\tFri, 1 Sep 2017 16:03:35 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xk7w72cMyzDqlp\n\tfor ;\n\tFri, 1 Sep 2017 16:03:35 +1000 (AEST)","from gate.crashing.org (gate.crashing.org [63.228.1.57])\n\t(using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xk7tm6vGhzDqh5\n\tfor ;\n\tFri, 1 Sep 2017 16:02:24 +1000 (AEST)","from localhost (localhost.localdomain [127.0.0.1])\n\tby gate.crashing.org (8.14.1/8.13.8) with ESMTP id v8161nQA016064;\n\tFri, 1 Sep 2017 01:01:52 -0500"],"Message-ID":"<1504245709.4974.75.camel@kernel.crashing.org>","Subject":"Re: [PATCH v3 6/8] powerpc/xive: introduce H_INT_ESB hcall","From":"Benjamin Herrenschmidt ","To":"=?iso-8859-1?q?C=E9dric?= Le Goater ,\n\tlinuxppc-dev@lists.ozlabs.org","Date":"Fri, 01 Sep 2017 16:01:49 +1000","In-Reply-To":"<20170830194617.26621-7-clg@kaod.org>","References":"<20170830194617.26621-1-clg@kaod.org>\n\t<20170830194617.26621-7-clg@kaod.org>","Content-Type":"text/plain; charset=\"UTF-8\"","X-Mailer":"Evolution 3.24.5 (3.24.5-1.fc26) ","Mime-Version":"1.0","Content-Transfer-Encoding":"8bit","X-BeenThere":"linuxppc-dev@lists.ozlabs.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"Linux on PowerPC Developers Mail List\n\t","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Paul Mackerras ,\n\tDavid Gibson ","Errors-To":"linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org","Sender":"\"Linuxppc-dev\"\n\t"}}]