[{"id":1760683,"web_url":"http://patchwork.ozlabs.org/comment/1760683/","msgid":"","list_archive_url":null,"date":"2017-08-31T06:51:51","subject":"Re: [U-Boot] [PATCH 1/2] PCI: Add driver for a\n\t'pci-host-ecam-generic' host controller","submitter":{"id":64981,"url":"http://patchwork.ozlabs.org/api/people/64981/","name":"Bin Meng","email":"bmeng.cn@gmail.com"},"content":"Hi Tuomas,\n\nOn Wed, Aug 30, 2017 at 4:31 PM, Tuomas Tynkkynen\n wrote:\n> QEMU emulates such a device with '-machine virt,highmem=off' on ARM.\n> The 'highmem=off' part is required for things to work as the PCI code\n> in U-Boot doesn't seem to support 64-bit BARs.\n>\n> This driver is basically a copy-paste of the Xilinx PCIE driver with the\n> Xilinx-specific bits removed and compatible string changed... The\n> generic code should probably be extracted into some sort of library\n> functions instead of duplicating them before committing this driver.\n>\n> Signed-off-by: Tuomas Tynkkynen \n> ---\n> drivers/pci/Kconfig | 8 ++\n> drivers/pci/Makefile | 1 +\n> drivers/pci/pcie_ecam_generic.c | 193 ++++++++++++++++++++++++++++++++++++++++\n> 3 files changed, 202 insertions(+)\n> create mode 100644 drivers/pci/pcie_ecam_generic.c\n>\n> diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig\n> index e2a1c0a409..745161fb9f 100644\n> --- a/drivers/pci/Kconfig\n> +++ b/drivers/pci/Kconfig\n> @@ -33,6 +33,14 @@ config PCI_PNP\n> help\n> Enable PCI memory and I/O space resource allocation and assignment.\n>\n> +config PCIE_ECAM_GENERIC\n> + bool \"Generic PCI-E ECAM support\"\n> + default n\n\nnits: default n is not needed as it is the default value\n\n> + depends on DM_PCI\n> + help\n> + Say Y here if you want to enable support for generic ECAM-based\n> + PCIe controllers, such as the one emulated by QEMU.\n> +\n> config PCIE_DW_MVEBU\n> bool \"Enable Armada-8K PCIe driver (DesignWare core)\"\n> default n\n> diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile\n> index ad44e83996..5eb12efbf5 100644\n> --- a/drivers/pci/Makefile\n> +++ b/drivers/pci/Makefile\n> @@ -17,6 +17,7 @@ obj-$(CONFIG_PCI) += pci.o pci_auto_old.o\n> endif\n> obj-$(CONFIG_PCI) += pci_auto_common.o pci_common.o\n>\n> +obj-$(CONFIG_PCIE_ECAM_GENERIC) += pcie_ecam_generic.o\n> obj-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o\n> obj-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o\n> obj-$(CONFIG_PCI_GT64120) += pci_gt64120.o\n> diff --git a/drivers/pci/pcie_ecam_generic.c b/drivers/pci/pcie_ecam_generic.c\n> new file mode 100644\n> index 0000000000..039e378cb0\n> --- /dev/null\n> +++ b/drivers/pci/pcie_ecam_generic.c\n> @@ -0,0 +1,193 @@\n> +/*\n> + * Generic PCIE host provided by e.g. QEMU\n> + *\n> + * Heavily based on drivers/pci/pcie_xilinx.c\n> + *\n> + * Copyright (C) 2016 Imagination Technologies\n> + *\n> + * SPDX-License-Identifier: GPL-2.0\n> + */\n> +\n> +#include \n> +#include \n> +#include \n> +\n> +#include \n> +\n> +/**\n> + * struct generic_ecam_pcie - generic_ecam PCIe controller state\n> + * @hose: The parent classes PCI controller state\n> + * @cfg_base: The base address of memory mapped configuration space\n> + */\n> +struct generic_ecam_pcie {\n> + struct pci_controller hose;\n\nThis sounds like a non-DM PCI driver stuff. I don't see it is\nreferenced in this driver.\n\n> + void *cfg_base;\n> +};\n> +\n> +/**\n> + * pcie_generic_ecam_config_address() - Calculate the address of a config access\n> + * @pcie: Pointer to the PCI controller state\n> + * @bdf: Identifies the PCIe device to access\n> + * @offset: The offset into the device's configuration space\n> + * @paddress: Pointer to the pointer to write the calculates address to\n> + *\n> + * Calculates the address that should be accessed to perform a PCIe\n> + * configuration space access for a given device identified by the PCIe\n> + * controller device @pcie and the bus, device & function numbers in @bdf. If\n> + * access to the device is not valid then the function will return an error\n> + * code. Otherwise the address to access will be written to the pointer pointed\n> + * to by @paddress.\n> + *\n> + * Return: 0 on success, else -ENODEV\n\nI see this driver always return 0.\n\n> + */\n> +static int pcie_generic_ecam_config_address(struct generic_ecam_pcie *pcie, pci_dev_t bdf,\n> + uint offset, void **paddress)\n> +{\n> + unsigned int bus = PCI_BUS(bdf);\n> + unsigned int dev = PCI_DEV(bdf);\n> + unsigned int func = PCI_FUNC(bdf);\n> + void *addr;\n> +\n> + addr = pcie->cfg_base;\n> + addr += bus << 20;\n> + addr += dev << 15;\n> + addr += func << 12;\n> + addr += offset;\n> + *paddress = addr;\n> +\n> + return 0;\n> +}\n> +\n> +/**\n> + * pcie_generic_ecam_read_config() - Read from configuration space\n> + * @pcie: Pointer to the PCI controller state\n\nThere is no pcie parameter, instead it's bus.\n\n> + * @bdf: Identifies the PCIe device to access\n> + * @offset: The offset into the device's configuration space\n> + * @valuep: A pointer at which to store the read value\n> + * @size: Indicates the size of access to perform\n> + *\n> + * Read a value of size @size from offset @offset within the configuration\n> + * space of the device identified by the bus, device & function numbers in @bdf\n> + * on the PCI bus @bus.\n> + *\n> + * Return: 0 on success, else -ENODEV or -EINVAL\n> + */\n> +static int pcie_generic_ecam_read_config(struct udevice *bus, pci_dev_t bdf,\n> + uint offset, ulong *valuep,\n> + enum pci_size_t size)\n> +{\n> + struct generic_ecam_pcie *pcie = dev_get_priv(bus);\n> + void *address;\n> + int err;\n> +\n> + err = pcie_generic_ecam_config_address(pcie, bdf, offset, &address);\n> + if (err < 0) {\n> + *valuep = pci_get_ff(size);\n> + return 0;\n> + }\n> +\n> + switch (size) {\n> + case PCI_SIZE_8:\n> + *valuep = __raw_readb(address);\n> + return 0;\n> + case PCI_SIZE_16:\n> + *valuep = __raw_readw(address);\n> + return 0;\n> + case PCI_SIZE_32:\n> + *valuep = __raw_readl(address);\n> + return 0;\n> + default:\n> + return -EINVAL;\n> + }\n> +}\n> +\n> +/**\n> + * pcie_generic_ecam_write_config() - Write to configuration space\n> + * @pcie: Pointer to the PCI controller state\n\nThere is no pcie parameter, instead it's bus.\n\n> + * @bdf: Identifies the PCIe device to access\n> + * @offset: The offset into the device's configuration space\n> + * @value: The value to write\n> + * @size: Indicates the size of access to perform\n> + *\n> + * Write the value @value of size @size from offset @offset within the\n> + * configuration space of the device identified by the bus, device & function\n> + * numbers in @bdf on the PCI bus @bus.\n> + *\n> + * Return: 0 on success, else -ENODEV or -EINVAL\n> + */\n> +static int pcie_generic_ecam_write_config(struct udevice *bus, pci_dev_t bdf,\n> + uint offset, ulong value,\n> + enum pci_size_t size)\n> +{\n> + struct generic_ecam_pcie *pcie = dev_get_priv(bus);\n> + void *address;\n> + int err;\n> +\n> + err = pcie_generic_ecam_config_address(pcie, bdf, offset, &address);\n> + if (err < 0)\n> + return 0;\n> +\n> + switch (size) {\n> + case PCI_SIZE_8:\n> + __raw_writeb(value, address);\n> + return 0;\n> + case PCI_SIZE_16:\n> + __raw_writew(value, address);\n> + return 0;\n> + case PCI_SIZE_32:\n> + __raw_writel(value, address);\n> + return 0;\n> + default:\n> + return -EINVAL;\n> + }\n> +}\n> +\n> +/**\n> + * pcie_generic_ecam_ofdata_to_platdata() - Translate from DT to device state\n> + * @dev: A pointer to the device being operated on\n> + *\n> + * Translate relevant data from the device tree pertaining to device @dev into\n> + * state that the driver will later make use of. This state is stored in the\n> + * device's private data structure.\n> + *\n> + * Return: 0 on success, else -EINVAL\n> + */\n> +static int pcie_generic_ecam_ofdata_to_platdata(struct udevice *dev)\n> +{\n> + struct generic_ecam_pcie *pcie = dev_get_priv(dev);\n> + struct fdt_resource reg_res;\n> + DECLARE_GLOBAL_DATA_PTR;\n> + int err;\n> +\n> + err = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev), \"reg\",\n> + 0, ®_res);\n> + if (err < 0) {\n> + error(\"\\\"reg\\\" resource not found\\n\");\n> + return err;\n> + }\n> +\n> + pcie->cfg_base = map_physmem(reg_res.start,\n> + fdt_resource_size(®_res),\n> + MAP_NOCACHE);\n> +\n> + return 0;\n> +}\n> +\n> +static const struct dm_pci_ops pcie_generic_ecam_ops = {\n> + .read_config = pcie_generic_ecam_read_config,\n> + .write_config = pcie_generic_ecam_write_config,\n> +};\n> +\n> +static const struct udevice_id pcie_generic_ecam_ids[] = {\n> + { .compatible = \"pci-host-ecam-generic\" },\n> + { }\n> +};\n> +\n> +U_BOOT_DRIVER(pcie_generic_ecam) = {\n> + .name = \"pcie_generic_ecam\",\n> + .id = UCLASS_PCI,\n> + .of_match = pcie_generic_ecam_ids,\n> + .ops = &pcie_generic_ecam_ops,\n> + .ofdata_to_platdata = pcie_generic_ecam_ofdata_to_platdata,\n> + .priv_auto_alloc_size = sizeof(struct generic_ecam_pcie),\n> +};\n> --\n\nRegards,\nBin","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1761574,"web_url":"http://patchwork.ozlabs.org/comment/1761574/","msgid":"<85ee7750-08f2-4822-0ce4-20469693ada1@gmail.com>","list_archive_url":null,"date":"2017-09-01T09:10:52","subject":"Re: [U-Boot] [PATCH 1/2] PCI: Add driver for a\n\t'pci-host-ecam-generic' host controller","submitter":{"id":72276,"url":"http://patchwork.ozlabs.org/api/people/72276/","name":"Tuomas Tynkkynen","email":"dezgeg@gmail.com"},"content":"Hi,\n\nOn 08/31/2017 09:51 AM, Bin Meng wrote:\n> Hi Tuomas,\n> \n> On Wed, Aug 30, 2017 at 4:31 PM, Tuomas Tynkkynen\n> wrote:\n>> QEMU emulates such a device with '-machine virt,highmem=off' on ARM.\n>> The 'highmem=off' part is required for things to work as the PCI code\n>> in U-Boot doesn't seem to support 64-bit BARs.\n>>\n>> This driver is basically a copy-paste of the Xilinx PCIE driver with the\n>> Xilinx-specific bits removed and compatible string changed... The\n>> generic code should probably be extracted into some sort of library\n>> functions instead of duplicating them before committing this driver.\n>>\n>> Signed-off-by: Tuomas Tynkkynen \n>> ---\n>> drivers/pci/Kconfig | 8 ++\n>> drivers/pci/Makefile | 1 +\n>> drivers/pci/pcie_ecam_generic.c | 193 ++++++++++++++++++++++++++++++++++++++++\n>> 3 files changed, 202 insertions(+)\n>> create mode 100644 drivers/pci/pcie_ecam_generic.c\n>>\n>> diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig\n>> index e2a1c0a409..745161fb9f 100644\n>> --- a/drivers/pci/Kconfig\n>> +++ b/drivers/pci/Kconfig\n>> @@ -33,6 +33,14 @@ config PCI_PNP\n>> help\n>> Enable PCI memory and I/O space resource allocation and assignment.\n>>\n>> +config PCIE_ECAM_GENERIC\n>> + bool \"Generic PCI-E ECAM support\"\n>> + default n\n> \n> nits: default n is not needed as it is the default value\n> \n\nSeems I have copied from PCIE_DW_MVEBU below. Removed.\n\n>> + depends on DM_PCI\n>> + help\n>> + Say Y here if you want to enable support for generic ECAM-based\n>> + PCIe controllers, such as the one emulated by QEMU.\n>> +\n>> config PCIE_DW_MVEBU\n>> bool \"Enable Armada-8K PCIe driver (DesignWare core)\"\n>> default n\n>> diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile\n>> index ad44e83996..5eb12efbf5 100644\n>> --- a/drivers/pci/Makefile\n>> +++ b/drivers/pci/Makefile\n>> @@ -17,6 +17,7 @@ obj-$(CONFIG_PCI) += pci.o pci_auto_old.o\n>> endif\n>> obj-$(CONFIG_PCI) += pci_auto_common.o pci_common.o\n>>\n>> +obj-$(CONFIG_PCIE_ECAM_GENERIC) += pcie_ecam_generic.o\n>> obj-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o\n>> obj-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o\n>> obj-$(CONFIG_PCI_GT64120) += pci_gt64120.o\n>> diff --git a/drivers/pci/pcie_ecam_generic.c b/drivers/pci/pcie_ecam_generic.c\n>> new file mode 100644\n>> index 0000000000..039e378cb0\n>> --- /dev/null\n>> +++ b/drivers/pci/pcie_ecam_generic.c\n>> @@ -0,0 +1,193 @@\n>> +/*\n>> + * Generic PCIE host provided by e.g. QEMU\n>> + *\n>> + * Heavily based on drivers/pci/pcie_xilinx.c\n>> + *\n>> + * Copyright (C) 2016 Imagination Technologies\n>> + *\n>> + * SPDX-License-Identifier: GPL-2.0\n>> + */\n>> +\n>> +#include \n>> +#include \n>> +#include \n>> +\n>> +#include \n>> +\n>> +/**\n>> + * struct generic_ecam_pcie - generic_ecam PCIe controller state\n>> + * @hose: The parent classes PCI controller state\n>> + * @cfg_base: The base address of memory mapped configuration space\n>> + */\n>> +struct generic_ecam_pcie {\n>> + struct pci_controller hose;\n> \n> This sounds like a non-DM PCI driver stuff. I don't see it is\n> referenced in this driver.\n> \n\nIndeed, it appears to be leftover code also in the pcie_xilinx that I\ncopied from. Also a bunch of other drivers that have had a DM conversion\nhave this as leftovers. I will clean them up also.\n\n>> + void *cfg_base;\n>> +};\n>> +\n>> +/**\n>> + * pcie_generic_ecam_config_address() - Calculate the address of a config access\n>> + * @pcie: Pointer to the PCI controller state\n>> + * @bdf: Identifies the PCIe device to access\n>> + * @offset: The offset into the device's configuration space\n>> + * @paddress: Pointer to the pointer to write the calculates address to\n>> + *\n>> + * Calculates the address that should be accessed to perform a PCIe\n>> + * configuration space access for a given device identified by the PCIe\n>> + * controller device @pcie and the bus, device & function numbers in @bdf. If\n>> + * access to the device is not valid then the function will return an error\n>> + * code. Otherwise the address to access will be written to the pointer pointed\n>> + * to by @paddress.\n>> + *\n>> + * Return: 0 on success, else -ENODEV\n> \n> I see this driver always return 0.\n> \n\nWill fix the comment. I kept the same signature for config_address since \nI'm planning to have common parts of .write_config and .read_config \nabstracted (similar to pci_generic_config_{read,write} in Linux) instead \nof copy pasting the same code the 3rd time in U-Boot.\n\n>> + */\n>> +static int pcie_generic_ecam_config_address(struct generic_ecam_pcie *pcie, pci_dev_t bdf,\n>> + uint offset, void **paddress)\n>> +{\n>> + unsigned int bus = PCI_BUS(bdf);\n>> + unsigned int dev = PCI_DEV(bdf);\n>> + unsigned int func = PCI_FUNC(bdf);\n>> + void *addr;\n>> +\n>> + addr = pcie->cfg_base;\n>> + addr += bus << 20;\n>> + addr += dev << 15;\n>> + addr += func << 12;\n>> + addr += offset;\n>> + *paddress = addr;\n>> +\n>> + return 0;\n>> +}\n>> +\n>> +/**\n>> + * pcie_generic_ecam_read_config() - Read from configuration space\n>> + * @pcie: Pointer to the PCI controller state\n> \n> There is no pcie parameter, instead it's bus.\n> \n\nAgain a problem inherited from pcie_xilinx... will fix there as well.\n\n>> + * @bdf: Identifies the PCIe device to access\n>> + * @offset: The offset into the device's configuration space\n>> + * @valuep: A pointer at which to store the read value\n>> + * @size: Indicates the size of access to perform\n>> + *\n>> + * Read a value of size @size from offset @offset within the configuration\n>> + * space of the device identified by the bus, device & function numbers in @bdf\n>> + * on the PCI bus @bus.\n>> + *\n>> + * Return: 0 on success, else -ENODEV or -EINVAL\n>> + */\n>> +static int pcie_generic_ecam_read_config(struct udevice *bus, pci_dev_t bdf,\n>> + uint offset, ulong *valuep,\n>> + enum pci_size_t size)\n>> +{\n>> + struct generic_ecam_pcie *pcie = dev_get_priv(bus);\n>> + void *address;\n>> + int err;\n>> +\n>> + err = pcie_generic_ecam_config_address(pcie, bdf, offset, &address);\n>> + if (err < 0) {\n>> + *valuep = pci_get_ff(size);\n>> + return 0;\n>> + }\n>> +\n>> + switch (size) {\n>> + case PCI_SIZE_8:\n>> + *valuep = __raw_readb(address);\n>> + return 0;\n>> + case PCI_SIZE_16:\n>> + *valuep = __raw_readw(address);\n>> + return 0;\n>> + case PCI_SIZE_32:\n>> + *valuep = __raw_readl(address);\n>> + return 0;\n>> + default:\n>> + return -EINVAL;\n>> + }\n>> +}\n>> +\n>> +/**\n>> + * pcie_generic_ecam_write_config() - Write to configuration space\n>> + * @pcie: Pointer to the PCI controller state\n> \n> There is no pcie parameter, instead it's bus.\n> \n\nDitto.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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