[{"id":1760663,"web_url":"http://patchwork.ozlabs.org/comment/1760663/","msgid":"<30241474-5f96-2d94-b1a9-4f163c8a4914@ti.com>","list_archive_url":null,"date":"2017-08-31T05:54:25","subject":"Re: [PATCH 12/17] ARM: dts: Add missing aess node and binding for\n\tomap4","submitter":{"id":9142,"url":"http://patchwork.ozlabs.org/api/people/9142/","name":"Peter Ujfalusi","email":"peter.ujfalusi@ti.com"},"content":"\n\n\nTexas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki\n\nOn 2017-08-30 18:19, Tony Lindgren wrote:\n> On omap4 we're missing the aess node with it's related \"ti,hwmods\"\n> property that the SoC interconnect code needs.\n> \n> Note that this will only show up as a bug with \"doesn't have\n> mpu register target base\" boot errors when the legacy platform\n> data is removed.\n> \n> Cc: Liam Girdwood \n> Cc: Mark Brown \n> Cc: Mark Rutland \n> Cc: Peter Ujfalusi \n> Cc: Rob Herring \n> Signed-off-by: Tony Lindgren \n> ---\n> .../devicetree/bindings/sound/ti-aess.txt | 33 ++++++++++++++++++++++\n> arch/arm/boot/dts/omap4.dtsi | 8 ++++++\n> 2 files changed, 41 insertions(+)\n> create mode 100644 Documentation/devicetree/bindings/sound/ti-aess.txt\n> \n> diff --git a/Documentation/devicetree/bindings/sound/ti-aess.txt b/Documentation/devicetree/bindings/sound/ti-aess.txt\n> new file mode 100644\n> --- /dev/null\n> +++ b/Documentation/devicetree/bindings/sound/ti-aess.txt\n> @@ -0,0 +1,33 @@\n> +Texas Instruments Audio Engine Subsystem (AESS) binding\n> +\n> +AESS performs real-time signal processing on TI SoCs.\n> +\n> +\n> +Required properties:\n> +\n> +compatible: Shall be one of the following:\n> +\t \"ti,omap4-aess\"\n> +\n> +reg: Shall contain the device instance IO range\n> +\n> +interrupts: Shall contain the device instance interrupt\n> +\n> +\n> +Optional properties:\n> +\n> +reg-names: Shall contain the IO range names if multiple IO\n> +\t ranges are used by the SoC\n> +\n> +ti,hwmods: Shall contain the TI interconnect module name if needed\n> +\t by the SoC\n> +\n> +\n> +Example:\n> +\n> +\taess: aess@401f1000 {\n> +\t\tcompatible = \"ti,omap4-aess\";\n> +\t\treg = <0x401f1000 0x400>, /* MPU private access */\n> +\t\t <0x490f1000 0x400>; /* L3 Interconnect */\n> +\t\treg-names = \"mpu\", \"dma\";\n> +\t\tti,hwmods = \"aess\";\n> +\t};\n> diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi\n> --- a/arch/arm/boot/dts/omap4.dtsi\n> +++ b/arch/arm/boot/dts/omap4.dtsi\n> @@ -793,6 +793,14 @@\n> \t\t\tti,hwmods = \"slimbus1\";\n> \t\t};\n> \n> +\t\taess: aess@401f1000 {\n> +\t\t\tcompatible = \"ti,omap4-aess\";\n> +\t\t\treg = <0x401f1000 0x400>, /* MPU private access */\n> +\t\t\t <0x490f1000 0x400>; /* L3 Interconnect */\n> +\t\t\treg-names = \"mpu\", \"dma\";\n> +\t\t\tti,hwmods = \"aess\";\n\nstatus = \"disabled\"\n\n> +\t\t};\n\nSimilar comment applies to AESS as to the McASP. We don't have driver\nfor it and we most likely not going to have.\nBut the binding is not correct in any case. The latest official Android\nkernel is 3.4(ish) to support AESS/ABE. I have rewritten the whole thing\nas an effort to upstream it and maintained the code up to 3.15. There\nthe DT node looks like this:\n\naess: aess@0x401f1000 {\n\tcompatible = \"ti,omap4-aess\";\n\treg = <0x401f1000 0x3ff>, /* MPU private access */\n\t\t<0x40180000 0xffff>, /* DMEM - MPU */\n\t\t<0x401a0000 0x1fff>, /* CMEM - MPU */\n\t\t<0x401c0000 0x5fff>, /* SMEM - MPU */\n\t\t<0x401e0000 0x1fff>, /* PMEM - MPU */\n\t\t<0x490f1000 0x3ff>, /* L3 Interconnect */\n\t\t<0x49080000 0xffff>, /* DMEM - MPU */\n\t\t<0x490a0000 0x1fff>, /* CMEM - MPU */\n\t\t<0x490ce000 0x5fff>, /* SMEM - MPU */\n\t\t<0x490e0000 0x1fff>; /* PMEM - MPU */\n\treg-names = \"mpu\", \"dmem\", \"cmem\", \"smem\", \"pmem\",\n\t\t\t\"dma\",\"dmem_dma\", \"cmem_dma\", \"smem_dma\",\n\t\t\t\"pmem_dma\";\n\tinterrupts = <0 99 0x4>;\n\tti,hwmods = \"aess\";\n\tdmas = <&sdma 101>,\n\t\t<&sdma 102>,\n\t\t<&sdma 103>,\n\t\t<&sdma 104>,\n\t\t<&sdma 105>,\n\t\t<&sdma 106>,\n\t\t<&sdma 107>,\n\t\t<&sdma 108>;\n\tdma-names = \"fifo0\", \"fifo1\", \"fifo2\", \"fifo3\", \"fifo4\",\n\t\t\t\"fifo5\", \"fifo6\", \"fifo7\";\n};\n\nThis is more closer to what we might need to describe AESS, but it might\nbe not correct if I ever have the time to forward port and convert it to\ncurrent upstream framework (DPCM, graph, whatever)\n\n> +\n> \t\tmcbsp4: mcbsp@48096000 {\n> \t\t\tcompatible = \"ti,omap4-mcbsp\";\n> \t\t\treg = <0x48096000 0xff>; /* L4 Interconnect */\n> \n\n- Péter\n\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=ti.com header.i=@ti.com header.b=\"F/CN9vRx\"; \n\tdkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xjWlq6h9dz9sMN\n\tfor ;\n\tThu, 31 Aug 2017 15:54:15 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1750892AbdHaFyO (ORCPT\n\t);\n\tThu, 31 Aug 2017 01:54:14 -0400","from lelnx193.ext.ti.com ([198.47.27.77]:29613 \"EHLO\n\tlelnx193.ext.ti.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1750864AbdHaFyN (ORCPT\n\t); Thu, 31 Aug 2017 01:54:13 -0400","from dflxv15.itg.ti.com ([128.247.5.124])\n\tby lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v7V5s3xb006434; \n\tThu, 31 Aug 2017 00:54:03 -0500","from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30])\n\tby dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7V5s3qS030699;\n\tThu, 31 Aug 2017 00:54:03 -0500","from DFLE109.ent.ti.com (10.64.6.30) by DFLE109.ent.ti.com\n\t(10.64.6.30) with Microsoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34;\n\tThu, 31 Aug 2017 00:54:03 -0500","from dflp32.itg.ti.com (10.64.6.15) by DFLE109.ent.ti.com\n\t(10.64.6.30) with Microsoft SMTP Server (version=TLS1_0,\n\tcipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend\n\tTransport; Thu, 31 Aug 2017 00:54:03 -0500","from [192.168.2.6] (ileax41-snat.itg.ti.com [10.172.224.153])\n\tby dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7V5s14D025531;\n\tThu, 31 Aug 2017 00:54:01 -0500"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com;\n\ts=ti-com-17Q1; t=1504158844;\n\tbh=3UXJeeoVTO8MF9F9NYJX+6BBoNKTvV7je7/OqAsnRNg=;\n\th=Subject:To:References:CC:From:Date:In-Reply-To;\n\tb=F/CN9vRxNkc5GUFZSaX/hqfrbHLhL9PbRFW4trWkhZcbfA7SHyIfBoGrzx1MiYkfe\n\tsa5pAjE0bpLe8c1WW3LU3EHwAx1B3vypD2//Ql6N48jwKkhXLGlQ0ymhlhpjVTxol7\n\tqofB1gcAsiD/ne9h6E3c4mOAjzFkSQlRkXx+5dsc=","Subject":"Re: [PATCH 12/17] ARM: dts: Add missing aess node and binding for\n\tomap4","To":"Tony Lindgren , ","References":"<20170830151953.30856-1-tony@atomide.com>\n\t<20170830151953.30856-13-tony@atomide.com>","CC":"=?utf-8?q?Beno=C3=AEt_Cousson?= ,\n\t, Liam Girdwood , \n\tMark Brown , Mark Rutland , \n\tRob Herring ","From":"Peter Ujfalusi ","Message-ID":"<30241474-5f96-2d94-b1a9-4f163c8a4914@ti.com>","Date":"Thu, 31 Aug 2017 08:54:25 +0300","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101\n\tThunderbird/45.8.0","MIME-Version":"1.0","In-Reply-To":"<20170830151953.30856-13-tony@atomide.com>","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"quoted-printable","X-EXCLAIMER-MD-CONFIG":"e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1761078,"web_url":"http://patchwork.ozlabs.org/comment/1761078/","msgid":"<20170831145112.GL6008@atomide.com>","list_archive_url":null,"date":"2017-08-31T14:51:12","subject":"Re: [PATCH 12/17] ARM: dts: Add missing aess node and binding for\n\tomap4","submitter":{"id":365,"url":"http://patchwork.ozlabs.org/api/people/365/","name":"Tony Lindgren","email":"tony@atomide.com"},"content":"* Peter Ujfalusi [170830 22:54]:\n> On 2017-08-30 18:19, Tony Lindgren wrote:\n> > +\t\taess: aess@401f1000 {\n> > +\t\t\tcompatible = \"ti,omap4-aess\";\n> > +\t\t\treg = <0x401f1000 0x400>, /* MPU private access */\n> > +\t\t\t <0x490f1000 0x400>; /* L3 Interconnect */\n> > +\t\t\treg-names = \"mpu\", \"dma\";\n> > +\t\t\tti,hwmods = \"aess\";\n> \n> status = \"disabled\"\n\nThat could be done for it's children if needed like I replied in\nthe McASP patch as this is for the interconnect target module.\nAnd this will need to just use the \"ti,sysc-type2\" compatible.\n\n> Similar comment applies to AESS as to the McASP. We don't have driver\n> for it and we most likely not going to have.\n\nOK\n\n> But the binding is not correct in any case. The latest official Android\n> kernel is 3.4(ish) to support AESS/ABE. I have rewritten the whole thing\n> as an effort to upstream it and maintained the code up to 3.15. There\n> the DT node looks like this:\n> \n> aess: aess@0x401f1000 {\n> \tcompatible = \"ti,omap4-aess\";\n> \treg = <0x401f1000 0x3ff>, /* MPU private access */\n> \t\t<0x40180000 0xffff>, /* DMEM - MPU */\n> \t\t<0x401a0000 0x1fff>, /* CMEM - MPU */\n> \t\t<0x401c0000 0x5fff>, /* SMEM - MPU */\n> \t\t<0x401e0000 0x1fff>, /* PMEM - MPU */\n> \t\t<0x490f1000 0x3ff>, /* L3 Interconnect */\n> \t\t<0x49080000 0xffff>, /* DMEM - MPU */\n> \t\t<0x490a0000 0x1fff>, /* CMEM - MPU */\n> \t\t<0x490ce000 0x5fff>, /* SMEM - MPU */\n> \t\t<0x490e0000 0x1fff>; /* PMEM - MPU */\n> \treg-names = \"mpu\", \"dmem\", \"cmem\", \"smem\", \"pmem\",\n> \t\t\t\"dma\",\"dmem_dma\", \"cmem_dma\", \"smem_dma\",\n> \t\t\t\"pmem_dma\";\n> \tinterrupts = <0 99 0x4>;\n> \tti,hwmods = \"aess\";\n> \tdmas = <&sdma 101>,\n> \t\t<&sdma 102>,\n> \t\t<&sdma 103>,\n> \t\t<&sdma 104>,\n> \t\t<&sdma 105>,\n> \t\t<&sdma 106>,\n> \t\t<&sdma 107>,\n> \t\t<&sdma 108>;\n> \tdma-names = \"fifo0\", \"fifo1\", \"fifo2\", \"fifo3\", \"fifo4\",\n> \t\t\t\"fifo5\", \"fifo6\", \"fifo7\";\n> };\n> \n> This is more closer to what we might need to describe AESS, but it might\n> be not correct if I ever have the time to forward port and convert it to\n> current upstream framework (DPCM, graph, whatever)\n\nYeah OK thanks. If there ever is a driver for it, those can then\nbe added as child nodes of the \"ti,sysc-type2\" interconnect target\nnode.\n\nRegards,\n\nTony\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xjlgV06pwz9s7c\n\tfor ;\n\tFri, 1 Sep 2017 00:51:18 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751589AbdHaOvQ (ORCPT\n\t);\n\tThu, 31 Aug 2017 10:51:16 -0400","from muru.com ([72.249.23.125]:39042 \"EHLO muru.com\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1751478AbdHaOvP (ORCPT );\n\tThu, 31 Aug 2017 10:51:15 -0400","from atomide.com (localhost [127.0.0.1])\n\tby muru.com (Postfix) with ESMTPS id 58F6781E6;\n\tThu, 31 Aug 2017 14:51:38 +0000 (UTC)"],"Date":"Thu, 31 Aug 2017 07:51:12 -0700","From":"Tony Lindgren ","To":"Peter Ujfalusi ","Cc":"linux-omap@vger.kernel.org, =?utf-8?q?Beno=C3=AEt?=\n\tCousson , devicetree@vger.kernel.org,\n\tLiam Girdwood , Mark Brown ,\n\tMark Rutland , Rob Herring ","Subject":"Re: [PATCH 12/17] ARM: dts: Add missing aess node and binding for\n\tomap4","Message-ID":"<20170831145112.GL6008@atomide.com>","References":"<20170830151953.30856-1-tony@atomide.com>\n\t<20170830151953.30856-13-tony@atomide.com>\n\t<30241474-5f96-2d94-b1a9-4f163c8a4914@ti.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<30241474-5f96-2d94-b1a9-4f163c8a4914@ti.com>","User-Agent":"Mutt/1.8.3 (2017-05-23)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}}]