[{"id":1760220,"web_url":"http://patchwork.ozlabs.org/comment/1760220/","msgid":"<20170830084012.19d91759@w520.home>","list_archive_url":null,"date":"2017-08-30T14:40:12","subject":"Re: [PATCH v3 3/3] PCI: Avoid slot reset for Cavium cn8xxx root\n\tports","submitter":{"id":4123,"url":"http://patchwork.ozlabs.org/api/people/4123/","name":"Alex Williamson","email":"alex.williamson@redhat.com"},"content":"On Wed, 30 Aug 2017 16:24:54 +0200\nJan Glauber wrote:\n\n> Root ports of cn8xxx do not function after a slot reset when used with\n> some e1000e and LSI HBA devices. Add a quirk to prevent slot reset on\n> these root ports.\n> \n> Signed-off-by: Jan Glauber \n> ---\n> drivers/pci/quirks.c | 16 ++++++++++++++++\n> 1 file changed, 16 insertions(+)\n> \n> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c\n> index 85191b8..6679971 100644\n> --- a/drivers/pci/quirks.c\n> +++ b/drivers/pci/quirks.c\n> @@ -845,6 +845,22 @@ static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev)\n> DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link);\n> #endif\n> \n> +/*\n> + * Root port on some Cavium CN8xxx chips do not successfully complete\n> + * a bus reset when used with certain types of child devices. Config\n> + * space access to the child may quit responding. Flag all devices under\n> + * the secondary bus as non-resettable.\n> + */\n> +static void quirk_CN8xxx_secondary_bus(struct pci_dev *dev)\n> +{\n> +\tstruct pci_dev *pdev;\n> +\n> +\tdev_warn(&dev->dev, \"Cavium CN8xxx quirk detected; reset for devices on secondary bus disabled\\n\");\n> +\tlist_for_each_entry(pdev, &dev->subordinate->devices, bus_list)\n> +\t\tpdev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;\n> +}\n> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_CN8xxx_secondary_bus);\n> +\n> /*\n> * Some settings of MMRBC can lead to data corruption so block changes.\n> * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide\n\n\nThis doesn't seem reliable, doesn't the user just need to remove and\nreprobe the slot and the device would re-appear without this flag set?\nThanks,\n\nAlex","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=)","ext-mx07.extmail.prod.ext.phx2.redhat.com;\n\tdmarc=none (p=none dis=none) header.from=redhat.com","ext-mx07.extmail.prod.ext.phx2.redhat.com;\n\tspf=fail smtp.mailfrom=alex.williamson@redhat.com"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xj7TF5KJGz9s8P\n\tfor ;\n\tThu, 31 Aug 2017 00:40:17 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751581AbdH3OkQ (ORCPT );\n\tWed, 30 Aug 2017 10:40:16 -0400","from mx1.redhat.com ([209.132.183.28]:50844 \"EHLO mx1.redhat.com\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1751357AbdH3OkO (ORCPT );\n\tWed, 30 Aug 2017 10:40:14 -0400","from smtp.corp.redhat.com\n\t(int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby mx1.redhat.com (Postfix) with ESMTPS id 2FBBEC047B81;\n\tWed, 30 Aug 2017 14:40:14 +0000 (UTC)","from w520.home (ovpn-116-27.phx2.redhat.com [10.3.116.27])\n\tby smtp.corp.redhat.com (Postfix) with ESMTP id 2ABF887F86;\n\tWed, 30 Aug 2017 14:40:13 +0000 (UTC)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mx1.redhat.com 2FBBEC047B81","Date":"Wed, 30 Aug 2017 08:40:12 -0600","From":"Alex Williamson ","To":"Jan Glauber ","Cc":"Bjorn Helgaas , linux-pci@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org, david.daney@cavium.com,\n\tJon Masters , Robert Richter ,\n\tlinux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org","Subject":"Re: [PATCH v3 3/3] PCI: Avoid slot reset for Cavium cn8xxx root\n\tports","Message-ID":"<20170830084012.19d91759@w520.home>","In-Reply-To":"<20170830142454.10971-4-jglauber@cavium.com>","References":"<20170830142454.10971-1-jglauber@cavium.com>\n\t<20170830142454.10971-4-jglauber@cavium.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=US-ASCII","Content-Transfer-Encoding":"7bit","X-Scanned-By":"MIMEDefang 2.79 on 10.5.11.15","X-Greylist":"Sender IP whitelisted, not delayed by milter-greylist-4.5.16\n\t(mx1.redhat.com [10.5.110.31]);\n\tWed, 30 Aug 2017 14:40:14 +0000 (UTC)","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"}},{"id":1760789,"web_url":"http://patchwork.ozlabs.org/comment/1760789/","msgid":"<20170831094052.GA15906@hc>","list_archive_url":null,"date":"2017-08-31T09:40:52","subject":"Re: [PATCH v3 3/3] PCI: Avoid slot reset for Cavium cn8xxx root\n\tports","submitter":{"id":68474,"url":"http://patchwork.ozlabs.org/api/people/68474/","name":"Jan Glauber","email":"jan.glauber@caviumnetworks.com"},"content":"On Wed, Aug 30, 2017 at 08:40:12AM -0600, Alex Williamson wrote:\n> On Wed, 30 Aug 2017 16:24:54 +0200\n> Jan Glauber wrote:\n> \n> > Root ports of cn8xxx do not function after a slot reset when used with\n> > some e1000e and LSI HBA devices. Add a quirk to prevent slot reset on\n> > these root ports.\n> > \n> > Signed-off-by: Jan Glauber \n> > ---\n> > drivers/pci/quirks.c | 16 ++++++++++++++++\n> > 1 file changed, 16 insertions(+)\n> > \n> > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c\n> > index 85191b8..6679971 100644\n> > --- a/drivers/pci/quirks.c\n> > +++ b/drivers/pci/quirks.c\n> > @@ -845,6 +845,22 @@ static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev)\n> > DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link);\n> > #endif\n> > \n> > +/*\n> > + * Root port on some Cavium CN8xxx chips do not successfully complete\n> > + * a bus reset when used with certain types of child devices. Config\n> > + * space access to the child may quit responding. Flag all devices under\n> > + * the secondary bus as non-resettable.\n> > + */\n> > +static void quirk_CN8xxx_secondary_bus(struct pci_dev *dev)\n> > +{\n> > +\tstruct pci_dev *pdev;\n> > +\n> > +\tdev_warn(&dev->dev, \"Cavium CN8xxx quirk detected; reset for devices on secondary bus disabled\\n\");\n> > +\tlist_for_each_entry(pdev, &dev->subordinate->devices, bus_list)\n> > +\t\tpdev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;\n> > +}\n> > +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_CN8xxx_secondary_bus);\n> > +\n> > /*\n> > * Some settings of MMRBC can lead to data corruption so block changes.\n> > * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide\n> \n> \n> This doesn't seem reliable, doesn't the user just need to remove and\n> reprobe the slot and the device would re-appear without this flag set?\n\nNo, I tried before to disable the slot with \"echo 0 > /sys/bus/pci/slots/3/power\"\nbut that does not work as it is not supported.\n\nI'm not familiar with the quirk types, would another one be better\nsuited here (even if we don't have the problem you descibed)?\n\nthanks,\nJan\n\n\n> Thanks,\n> \n> Alex","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; 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a=rsa-sha256; c=relaxed/relaxed;\n\td=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version;\n\tbh=/xLOUm7Uv0cEDa8eu5VPeQBeNowHvlfY0RGHJjGCAK0=;\n\tb=WNJPhcedaqkB+KHMLjs7oJMGU1mTU77CHXiZPaD4Fe/NbNPq5VF96KdBF6FJpezQmuO/oGlxveuDygex1KjqnnTf7mQTHKraJvkPR24B89HRCnuDDQr/K0tiUAXgBceivwrWnj6bBswW/bTnSVJa6fLTUL8hec13A9Lp4CsdM1M=","Date":"Thu, 31 Aug 2017 11:40:52 +0200","From":"Jan Glauber ","To":"Alex Williamson ","Cc":"Bjorn Helgaas , linux-pci@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org, david.daney@cavium.com,\n\tJon Masters , Robert Richter ,\n\tlinux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org","Subject":"Re: [PATCH v3 3/3] PCI: Avoid slot reset for Cavium cn8xxx root\n\tports","Message-ID":"<20170831094052.GA15906@hc>","References":"<20170830142454.10971-1-jglauber@cavium.com>\n\t<20170830142454.10971-4-jglauber@cavium.com>\n\t<20170830084012.19d91759@w520.home>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170830084012.19d91759@w520.home>","User-Agent":"Mutt/1.5.21 (2010-09-15)","X-Originating-IP":"[88.67.130.225]","X-ClientProxiedBy":"DB6PR1001CA0003.EURPRD10.PROD.OUTLOOK.COM (10.171.79.13)\n\tTo BN3PR07MB2578.namprd07.prod.outlook.com (10.167.5.6)","X-MS-PublicTrafficType":"Email","X-MS-Office365-Filtering-Correlation-Id":"1f932ce7-bb23-44b0-da6f-08d4f054658f","X-Microsoft-Antispam":"UriScan:; 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SFP:1101; SCL:1; SRVR:BN3PR07MB2578; H:hc; FPR:;\n\tSPF:None; PTR:InfoNoRecords; A:1; MX:1; LANG:en; ","Received-SPF":"None (protection.outlook.com: cavium.com does not designate\n\tpermitted sender hosts)","SpamDiagnosticOutput":"1:99","SpamDiagnosticMetadata":"NSPM","X-OriginatorOrg":"caviumnetworks.com","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"31 Aug 2017 09:41:02.1052\n\t(UTC)","X-MS-Exchange-CrossTenant-FromEntityHeader":"Hosted","X-MS-Exchange-CrossTenant-Id":"711e4ccf-2e9b-4bcf-a551-4094005b6194","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"BN3PR07MB2578","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"}},{"id":1761141,"web_url":"http://patchwork.ozlabs.org/comment/1761141/","msgid":"<20170831100130.5c8a922e@w520.home>","list_archive_url":null,"date":"2017-08-31T16:01:30","subject":"Re: [PATCH v3 3/3] PCI: Avoid slot reset for Cavium cn8xxx root\n\tports","submitter":{"id":4123,"url":"http://patchwork.ozlabs.org/api/people/4123/","name":"Alex Williamson","email":"alex.williamson@redhat.com"},"content":"On Thu, 31 Aug 2017 11:40:52 +0200\nJan Glauber wrote:\n\n> On Wed, Aug 30, 2017 at 08:40:12AM -0600, Alex Williamson wrote:\n> > On Wed, 30 Aug 2017 16:24:54 +0200\n> > Jan Glauber wrote:\n> > \n> > > Root ports of cn8xxx do not function after a slot reset when used with\n> > > some e1000e and LSI HBA devices. Add a quirk to prevent slot reset on\n> > > these root ports.\n> > > \n> > > Signed-off-by: Jan Glauber \n> > > ---\n> > > drivers/pci/quirks.c | 16 ++++++++++++++++\n> > > 1 file changed, 16 insertions(+)\n> > > \n> > > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c\n> > > index 85191b8..6679971 100644\n> > > --- a/drivers/pci/quirks.c\n> > > +++ b/drivers/pci/quirks.c\n> > > @@ -845,6 +845,22 @@ static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev)\n> > > DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link);\n> > > #endif\n> > > \n> > > +/*\n> > > + * Root port on some Cavium CN8xxx chips do not successfully complete\n> > > + * a bus reset when used with certain types of child devices. Config\n> > > + * space access to the child may quit responding. Flag all devices under\n> > > + * the secondary bus as non-resettable.\n> > > + */\n> > > +static void quirk_CN8xxx_secondary_bus(struct pci_dev *dev)\n> > > +{\n> > > +\tstruct pci_dev *pdev;\n> > > +\n> > > +\tdev_warn(&dev->dev, \"Cavium CN8xxx quirk detected; reset for devices on secondary bus disabled\\n\");\n> > > +\tlist_for_each_entry(pdev, &dev->subordinate->devices, bus_list)\n> > > +\t\tpdev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;\n> > > +}\n> > > +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_CN8xxx_secondary_bus);\n> > > +\n> > > /*\n> > > * Some settings of MMRBC can lead to data corruption so block changes.\n> > > * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide \n> > \n> > \n> > This doesn't seem reliable, doesn't the user just need to remove and\n> > reprobe the slot and the device would re-appear without this flag set? \n> \n> No, I tried before to disable the slot with \"echo 0 > /sys/bus/pci/slots/3/power\"\n> but that does not work as it is not supported.\n> \n> I'm not familiar with the quirk types, would another one be better\n> suited here (even if we don't have the problem you descibed)?\n\nThe scenario I'm mentioning is to \"echo 1 > /sys/bus/pci/devices//remove\", then \"echo >\n/sys/bus/pci/rescan\". This would break the ordering implicit in using\na fixup defined for the root port. It seems like it'd make a lot more\nsense to add a test on the parent bridge more similar to how the bus\nreset works. It's not the subordinate devices imposing the\nno-bus-reset flag, it's the bridge device and the objects and code\nshould support and reflect that. Thanks,\n\nAlex","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=)","ext-mx10.extmail.prod.ext.phx2.redhat.com;\n\tdmarc=none (p=none dis=none) header.from=redhat.com","ext-mx10.extmail.prod.ext.phx2.redhat.com;\n\tspf=fail smtp.mailfrom=alex.williamson@redhat.com"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xjnDZ3dHTz9sMN\n\tfor ;\n\tFri, 1 Sep 2017 02:01:34 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751662AbdHaQBc (ORCPT );\n\tThu, 31 Aug 2017 12:01:32 -0400","from mx1.redhat.com ([209.132.183.28]:48094 \"EHLO mx1.redhat.com\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1751583AbdHaQBb (ORCPT );\n\tThu, 31 Aug 2017 12:01:31 -0400","from smtp.corp.redhat.com\n\t(int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby mx1.redhat.com (Postfix) with ESMTPS id 87C3961490;\n\tThu, 31 Aug 2017 16:01:31 +0000 (UTC)","from w520.home (ovpn-116-27.phx2.redhat.com [10.3.116.27])\n\tby smtp.corp.redhat.com (Postfix) with ESMTP id 9B54C9353C;\n\tThu, 31 Aug 2017 16:01:30 +0000 (UTC)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mx1.redhat.com 87C3961490","Date":"Thu, 31 Aug 2017 10:01:30 -0600","From":"Alex Williamson ","To":"Jan Glauber ","Cc":"Bjorn Helgaas , linux-pci@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org, david.daney@cavium.com,\n\tJon Masters , Robert Richter ,\n\tlinux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org","Subject":"Re: [PATCH v3 3/3] PCI: Avoid slot reset for Cavium cn8xxx root\n\tports","Message-ID":"<20170831100130.5c8a922e@w520.home>","In-Reply-To":"<20170831094052.GA15906@hc>","References":"<20170830142454.10971-1-jglauber@cavium.com>\n\t<20170830142454.10971-4-jglauber@cavium.com>\n\t<20170830084012.19d91759@w520.home> <20170831094052.GA15906@hc>","MIME-Version":"1.0","Content-Type":"text/plain; charset=US-ASCII","Content-Transfer-Encoding":"7bit","X-Scanned-By":"MIMEDefang 2.79 on 10.5.11.15","X-Greylist":"Sender IP whitelisted, not delayed by milter-greylist-4.5.16\n\t(mx1.redhat.com [10.5.110.39]);\n\tThu, 31 Aug 2017 16:01:31 +0000 (UTC)","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"}},{"id":1764558,"web_url":"http://patchwork.ozlabs.org/comment/1764558/","msgid":"<20170907074011.GA13490@hc>","list_archive_url":null,"date":"2017-09-07T07:40:11","subject":"Re: [PATCH v3 3/3] PCI: Avoid slot reset for Cavium cn8xxx root\n\tports","submitter":{"id":68474,"url":"http://patchwork.ozlabs.org/api/people/68474/","name":"Jan Glauber","email":"jan.glauber@caviumnetworks.com"},"content":"On Thu, Aug 31, 2017 at 10:01:30AM -0600, Alex Williamson wrote:\n> On Thu, 31 Aug 2017 11:40:52 +0200\n> Jan Glauber wrote:\n> \n> > On Wed, Aug 30, 2017 at 08:40:12AM -0600, Alex Williamson wrote:\n> > > On Wed, 30 Aug 2017 16:24:54 +0200\n> > > Jan Glauber wrote:\n> > > \n> > > > Root ports of cn8xxx do not function after a slot reset when used with\n> > > > some e1000e and LSI HBA devices. Add a quirk to prevent slot reset on\n> > > > these root ports.\n> > > > \n> > > > Signed-off-by: Jan Glauber \n> > > > ---\n> > > > drivers/pci/quirks.c | 16 ++++++++++++++++\n> > > > 1 file changed, 16 insertions(+)\n> > > > \n> > > > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c\n> > > > index 85191b8..6679971 100644\n> > > > --- a/drivers/pci/quirks.c\n> > > > +++ b/drivers/pci/quirks.c\n> > > > @@ -845,6 +845,22 @@ static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev)\n> > > > DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link);\n> > > > #endif\n> > > > \n> > > > +/*\n> > > > + * Root port on some Cavium CN8xxx chips do not successfully complete\n> > > > + * a bus reset when used with certain types of child devices. Config\n> > > > + * space access to the child may quit responding. Flag all devices under\n> > > > + * the secondary bus as non-resettable.\n> > > > + */\n> > > > +static void quirk_CN8xxx_secondary_bus(struct pci_dev *dev)\n> > > > +{\n> > > > +\tstruct pci_dev *pdev;\n> > > > +\n> > > > +\tdev_warn(&dev->dev, \"Cavium CN8xxx quirk detected; reset for devices on secondary bus disabled\\n\");\n> > > > +\tlist_for_each_entry(pdev, &dev->subordinate->devices, bus_list)\n> > > > +\t\tpdev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;\n> > > > +}\n> > > > +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_CN8xxx_secondary_bus);\n> > > > +\n> > > > /*\n> > > > * Some settings of MMRBC can lead to data corruption so block changes.\n> > > > * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide \n> > > \n> > > \n> > > This doesn't seem reliable, doesn't the user just need to remove and\n> > > reprobe the slot and the device would re-appear without this flag set? \n> > \n> > No, I tried before to disable the slot with \"echo 0 > /sys/bus/pci/slots/3/power\"\n> > but that does not work as it is not supported.\n> > \n> > I'm not familiar with the quirk types, would another one be better\n> > suited here (even if we don't have the problem you descibed)?\n> \n> The scenario I'm mentioning is to \"echo 1 > /sys/bus/pci/devices/ device under the slot>/remove\", then \"echo >\n> /sys/bus/pci/rescan\". This would break the ordering implicit in using\n> a fixup defined for the root port. It seems like it'd make a lot more\n> sense to add a test on the parent bridge more similar to how the bus\n> reset works. It's not the subordinate devices imposing the\n> no-bus-reset flag, it's the bridge device and the objects and code\n> should support and reflect that. Thanks,\n\nDoing \"echo > /sys/bus/pci/rescan\" after the\nremove did not work for me, but maybe the format of the device address\nneeds to be different. Anyway, the sequence\n echo 1 > /sys/bus/pci/devices//remove\n echo 1 > /sys/bus/pci/rescan\nstill triggers the panic as you mentioned above.\n\nI agree that the subordinate devices are not causing the issue, still\nI need to make pci_slot_resetable() return false in our case.\n\nSo what if we add an additional check like:\n\ndiff --git a/drivers/pci/pci.c b/drivers/pci/pci.c\nindex fdf65a6..389db4b 100644\n--- a/drivers/pci/pci.c\n+++ b/drivers/pci/pci.c\n@@ -4389,6 +4389,9 @@ static bool pci_slot_resetable(struct pci_slot *slot)\n {\n struct pci_dev *dev;\n \n+ if (slot->bus->self & PCI_DEV_FLAGS_NO_BUS_RESET)\n+ return false;\n+\n list_for_each_entry(dev, &slot->bus->devices, bus_list) {\n if (!dev->slot || dev->slot != slot)\n continue;\n\n--Jan","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; 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a=rsa-sha256; c=relaxed/relaxed;\n\td=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version;\n\tbh=3yrnQxM5sccC1LmFSYongBTfLtOZPpa4aDxN2GwMQpA=;\n\tb=KIgwzsSnmFrFC+ZyRpQsTxQAl4qfPwo180dTTTv9SyTu1mDqRhwg1LDGIynTuvABKKsvROzEyuBwCIbaJIqucYwWKvffH5hHsiRQ3NN4ihc7nsF+7BgNn8MfuOrp2gNPDzHl2a+T4kjTjBSHbJz3JPOCiechw1cBqkiuLYigRFQ=","Date":"Thu, 7 Sep 2017 09:40:11 +0200","From":"Jan Glauber ","To":"Alex Williamson ","Cc":"Bjorn Helgaas , linux-pci@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org, david.daney@cavium.com,\n\tJon Masters , Robert Richter ,\n\tlinux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org","Subject":"Re: [PATCH v3 3/3] PCI: Avoid slot reset for Cavium cn8xxx root\n\tports","Message-ID":"<20170907074011.GA13490@hc>","References":"<20170830142454.10971-1-jglauber@cavium.com>\n\t<20170830142454.10971-4-jglauber@cavium.com>\n\t<20170830084012.19d91759@w520.home> <20170831094052.GA15906@hc>\n\t<20170831100130.5c8a922e@w520.home>","MIME-Version":"1.0","Content-Type":"text/plain; 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SFP:1101; SCL:1; SRVR:BN3PR07MB2577; H:hc; FPR:;\n\tSPF:None; PTR:InfoNoRecords; MX:1; A:1; LANG:en; ","Received-SPF":"None (protection.outlook.com: cavium.com does not designate\n\tpermitted sender hosts)","SpamDiagnosticOutput":"1:99","SpamDiagnosticMetadata":"NSPM","X-OriginatorOrg":"caviumnetworks.com","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"07 Sep 2017 07:40:21.4612\n\t(UTC)","X-MS-Exchange-CrossTenant-FromEntityHeader":"Hosted","X-MS-Exchange-CrossTenant-Id":"711e4ccf-2e9b-4bcf-a551-4094005b6194","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"BN3PR07MB2577","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"}},{"id":1764561,"web_url":"http://patchwork.ozlabs.org/comment/1764561/","msgid":"<20170907074904.GB13490@hc>","list_archive_url":null,"date":"2017-09-07T07:49:04","subject":"Re: [PATCH v3 3/3] PCI: Avoid slot reset for Cavium cn8xxx root\n\tports","submitter":{"id":68474,"url":"http://patchwork.ozlabs.org/api/people/68474/","name":"Jan Glauber","email":"jan.glauber@caviumnetworks.com"},"content":"On Thu, Sep 07, 2017 at 09:40:11AM +0200, Jan Glauber wrote:\n> So what if we add an additional check like:\n> \n> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c\n> index fdf65a6..389db4b 100644\n> --- a/drivers/pci/pci.c\n> +++ b/drivers/pci/pci.c\n> @@ -4389,6 +4389,9 @@ static bool pci_slot_resetable(struct pci_slot *slot)\n> {\n> struct pci_dev *dev;\n> \n> + if (slot->bus->self & PCI_DEV_FLAGS_NO_BUS_RESET)\n> + return false;\n> +\n> list_for_each_entry(dev, &slot->bus->devices, bus_list) {\n> if (!dev->slot || dev->slot != slot)\n> continue;\n\nObviously I meant:\nif (slot->bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)\n\n--Jan","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; 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a=rsa-sha256; c=relaxed/relaxed;\n\td=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version;\n\tbh=aQRaFwI1AFTTsNksqDvBKw8GmFBjc2G3Xu9QvN73nj4=;\n\tb=j0dZVV+5CxffXdD4pz9yraLZ4f+rc9vzxgKlL6s/e77Wpg1BWkAbQwK8TwY43p9Mg3RrIyuZ5i0FMUC2iLemg1C1GVAf0dw7PjCupwL397TO46s/TZD7OT5siDMRDz9op432FrG/f6g6Avyl1+5BuEkKGM7txTAwUmWchP5E9eY=","Date":"Thu, 7 Sep 2017 09:49:04 +0200","From":"Jan Glauber ","To":"Alex Williamson ","Cc":"Bjorn Helgaas , linux-pci@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org, david.daney@cavium.com,\n\tJon Masters , Robert Richter ,\n\tlinux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org","Subject":"Re: [PATCH v3 3/3] PCI: Avoid slot reset for Cavium cn8xxx root\n\tports","Message-ID":"<20170907074904.GB13490@hc>","References":"<20170830142454.10971-1-jglauber@cavium.com>\n\t<20170830142454.10971-4-jglauber@cavium.com>\n\t<20170830084012.19d91759@w520.home> <20170831094052.GA15906@hc>\n\t<20170831100130.5c8a922e@w520.home> <20170907074011.GA13490@hc>","MIME-Version":"1.0","Content-Type":"text/plain; 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SFP:1101; SCL:1; SRVR:CY1PR07MB2585; H:hc; FPR:;\n\tSPF:None; PTR:InfoNoRecords; MX:1; A:1; LANG:en; ","Received-SPF":"None (protection.outlook.com: cavium.com does not designate\n\tpermitted sender hosts)","SpamDiagnosticOutput":"1:99","SpamDiagnosticMetadata":"NSPM","X-OriginatorOrg":"caviumnetworks.com","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"07 Sep 2017 07:49:16.5534\n\t(UTC)","X-MS-Exchange-CrossTenant-FromEntityHeader":"Hosted","X-MS-Exchange-CrossTenant-Id":"711e4ccf-2e9b-4bcf-a551-4094005b6194","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"CY1PR07MB2585","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"}},{"id":1764836,"web_url":"http://patchwork.ozlabs.org/comment/1764836/","msgid":"<20170907105237.3f025280@w520.home>","list_archive_url":null,"date":"2017-09-07T16:52:37","subject":"Re: [PATCH v3 3/3] PCI: Avoid slot reset for Cavium cn8xxx root\n\tports","submitter":{"id":4123,"url":"http://patchwork.ozlabs.org/api/people/4123/","name":"Alex Williamson","email":"alex.williamson@redhat.com"},"content":"On Thu, 7 Sep 2017 09:49:04 +0200\nJan Glauber wrote:\n\n> On Thu, Sep 07, 2017 at 09:40:11AM +0200, Jan Glauber wrote:\n> > So what if we add an additional check like:\n> > \n> > diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c\n> > index fdf65a6..389db4b 100644\n> > --- a/drivers/pci/pci.c\n> > +++ b/drivers/pci/pci.c\n> > @@ -4389,6 +4389,9 @@ static bool pci_slot_resetable(struct pci_slot *slot)\n> > {\n> > struct pci_dev *dev;\n> > \n> > + if (slot->bus->self & PCI_DEV_FLAGS_NO_BUS_RESET)\n> > + return false;\n> > +\n> > list_for_each_entry(dev, &slot->bus->devices, bus_list) {\n> > if (!dev->slot || dev->slot != slot)\n> > continue; \n> \n> Obviously I meant:\n> if (slot->bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)\n\nMuch better, perhaps even incorporate the bus->self check for good\nmeasure... is it possible to have a slot on a root bus? Taking\ndifferent approaches for bus vs slot reset should have been a giant red\nflag that something is wrong. Thanks,\n\nAlex","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=)","ext-mx05.extmail.prod.ext.phx2.redhat.com;\n\tdmarc=none (p=none dis=none) header.from=redhat.com","ext-mx05.extmail.prod.ext.phx2.redhat.com;\n\tspf=fail smtp.mailfrom=alex.williamson@redhat.com"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xp62c672Bz9s8J\n\tfor ;\n\tFri, 8 Sep 2017 02:52:56 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1754882AbdIGQwy (ORCPT );\n\tThu, 7 Sep 2017 12:52:54 -0400","from mx1.redhat.com ([209.132.183.28]:35910 \"EHLO mx1.redhat.com\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1754850AbdIGQwy (ORCPT );\n\tThu, 7 Sep 2017 12:52:54 -0400","from smtp.corp.redhat.com\n\t(int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby mx1.redhat.com (Postfix) with ESMTPS id D3DDD128E;\n\tThu, 7 Sep 2017 16:52:53 +0000 (UTC)","from w520.home (ovpn-116-27.phx2.redhat.com [10.3.116.27])\n\tby smtp.corp.redhat.com (Postfix) with ESMTP id AB0406F988;\n\tThu, 7 Sep 2017 16:52:37 +0000 (UTC)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mx1.redhat.com D3DDD128E","Date":"Thu, 7 Sep 2017 10:52:37 -0600","From":"Alex Williamson ","To":"Jan Glauber ","Cc":"Bjorn Helgaas , linux-pci@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org, david.daney@cavium.com,\n\tJon Masters , Robert Richter ,\n\tlinux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org","Subject":"Re: [PATCH v3 3/3] PCI: Avoid slot reset for Cavium cn8xxx root\n\tports","Message-ID":"<20170907105237.3f025280@w520.home>","In-Reply-To":"<20170907074904.GB13490@hc>","References":"<20170830142454.10971-1-jglauber@cavium.com>\n\t<20170830142454.10971-4-jglauber@cavium.com>\n\t<20170830084012.19d91759@w520.home> <20170831094052.GA15906@hc>\n\t<20170831100130.5c8a922e@w520.home> <20170907074011.GA13490@hc>\n\t<20170907074904.GB13490@hc>","MIME-Version":"1.0","Content-Type":"text/plain; charset=US-ASCII","Content-Transfer-Encoding":"7bit","X-Scanned-By":"MIMEDefang 2.79 on 10.5.11.13","X-Greylist":"Sender IP whitelisted, not delayed by milter-greylist-4.5.16\n\t(mx1.redhat.com [10.5.110.29]);\n\tThu, 07 Sep 2017 16:52:54 +0000 (UTC)","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"}}]