[{"id":1759921,"web_url":"http://patchwork.ozlabs.org/comment/1759921/","msgid":"<1504076904.4670.20.camel@neuling.org>","date":"2017-08-30T07:08:24","subject":"Re: [PATCH RFC] Interface to set SPRN_TIDR","submitter":{"id":109,"url":"http://patchwork.ozlabs.org/api/people/109/","name":"Michael Neuling","email":"mikey@neuling.org"},"content":"Suka,\n\nPlease CC Christophe who as an alternative way of doing this. We ned to get\nagreement across all users of TIDR/AS_notify...\n\nHis patch is here:\n https://lists.ozlabs.org/pipermail/linuxppc-dev/2017-August/161582.html\n\nMikey\n\nOn Tue, 2017-08-29 at 19:38 -0700, Sukadev Bhattiprolu wrote:\n> We need the SPRN_TIDR to be set for use with fast thread-wakeup\n> (core-to-core wakeup) in VAS. Each user thread that has a receive\n> window setup and expects to be notified when a sender issues a paste\n> needs to have a unique SPRN_TIDR value.\n> \n> The SPRN_TIDR value only needs to unique within the process but for\n> now we use a globally unique thread id as described below.\n> \n> Signed-off-by: Sukadev Bhattiprolu \n> ---\n> Changelog[v2]\n> \t- Michael Ellerman: Use an interface to assign TIDR so it is\n> \t  assigned to only threads that need it; move assignment to\n> \t  restore_sprs(). Drop lint from rebase;\n> \n> \n>  arch/powerpc/include/asm/processor.h |  4 ++\n>  arch/powerpc/include/asm/switch_to.h |  3 ++\n>  arch/powerpc/kernel/process.c        | 97\n> ++++++++++++++++++++++++++++++++++++\n>  3 files changed, 104 insertions(+)\n> \n> diff --git a/arch/powerpc/include/asm/processor.h\n> b/arch/powerpc/include/asm/processor.h\n> index fab7ff8..bf6ba63 100644\n> --- a/arch/powerpc/include/asm/processor.h\n> +++ b/arch/powerpc/include/asm/processor.h\n> @@ -232,6 +232,10 @@ struct debug_reg {\n>  struct thread_struct {\n>  \tunsigned long\tksp;\t\t/* Kernel stack pointer */\n> \n> +#ifdef CONFIG_PPC_VAS\n> +\tunsigned long\ttidr;\n> +#endif\n> +\n>  #ifdef CONFIG_PPC64\n>  \tunsigned long\tksp_vsid;\n>  #endif\n> diff --git a/arch/powerpc/include/asm/switch_to.h\n> b/arch/powerpc/include/asm/switch_to.h\n> index 17c8380..4962455 100644\n> --- a/arch/powerpc/include/asm/switch_to.h\n> +++ b/arch/powerpc/include/asm/switch_to.h\n> @@ -91,4 +91,7 @@ static inline void clear_task_ebb(struct task_struct *t)\n>  #endif\n>  }\n> \n> +extern void set_thread_tidr(struct task_struct *t);\n> +extern void clear_thread_tidr(struct task_struct *t);\n> +\n>  #endif /* _ASM_POWERPC_SWITCH_TO_H */\n> diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c\n> index 1f0fd36..13abb22 100644\n> --- a/arch/powerpc/kernel/process.c\n> +++ b/arch/powerpc/kernel/process.c\n> @@ -1132,6 +1132,10 @@ static inline void restore_sprs(struct thread_struct\n> *old_thread,\n>  \t\t\tmtspr(SPRN_TAR, new_thread->tar);\n>  \t}\n>  #endif\n> +#ifdef CONFIG_PPC_VAS\n> +\tif (old_thread->tidr != new_thread->tidr)\n> +\t\tmtspr(SPRN_TIDR, new_thread->tidr);\n> +#endif\n>  }\n> \n>  #ifdef CONFIG_PPC_BOOK3S_64\n> @@ -1446,9 +1450,97 @@ void flush_thread(void)\n>  #endif /* CONFIG_HAVE_HW_BREAKPOINT */\n>  }\n> \n> +#ifdef CONFIG_PPC_VAS\n> +static DEFINE_SPINLOCK(vas_thread_id_lock);\n> +static DEFINE_IDA(vas_thread_ida);\n> +\n> +/*\n> + * We need to assign an unique thread id to each thread in a process. This\n> + * thread id is intended to be used with the Fast Thread-wakeup (aka Core-\n> + * to-core wakeup) mechanism being implemented on top of Virtual Accelerator\n> + * Switchboard (VAS).\n> + *\n> + * To get a unique thread-id per process we could simply use task_pid_nr()\n> + * but the problem is that task_pid_nr() is not yet available for the thread\n> + * when copy_thread() is called. Fixing that would require changing more\n> + * intrusive arch-neutral code in code path in copy_process()?.\n> + *\n> + * Further, to assign unique thread ids within each process, we need an\n> + * atomic field (or an IDR) in task_struct, which again intrudes into the\n> + * arch-neutral code.\n> + *\n> + * So try to assign globally unique thraed ids for now.\n> + *\n> + * NOTE: TIDR 0 indicates that the thread does not need a TIDR value.\n> + * \t For now, only threads that expect to be notified by the VAS\n> + * \t hardware need a TIDR value and we assign values > 0 for those.\n> + */\n> +#define MAX_THREAD_CONTEXT\t((1 << 15) - 2)\n> +static int assign_thread_tidr(void)\n> +{\n> +\tint index;\n> +\tint err;\n> +\n> +again:\n> +\tif (!ida_pre_get(&vas_thread_ida, GFP_KERNEL))\n> +\t\treturn -ENOMEM;\n> +\n> +\tspin_lock(&vas_thread_id_lock);\n> +\terr = ida_get_new_above(&vas_thread_ida, 1, &index);\n> +\tspin_unlock(&vas_thread_id_lock);\n> +\n> +\tif (err == -EAGAIN)\n> +\t\tgoto again;\n> +\telse if (err)\n> +\t\treturn err;\n> +\n> +\tif (index > MAX_THREAD_CONTEXT) {\n> +\t\tspin_lock(&vas_thread_id_lock);\n> +\t\tida_remove(&vas_thread_ida, index);\n> +\t\tspin_unlock(&vas_thread_id_lock);\n> +\t\treturn -ENOMEM;\n> +\t}\n> +\n> +\treturn index;\n> +}\n> +\n> +static void free_thread_tidr(int id)\n> +{\n> +\tspin_lock(&vas_thread_id_lock);\n> +\tida_remove(&vas_thread_ida, id);\n> +\tspin_unlock(&vas_thread_id_lock);\n> +}\n> +\n> +void clear_thread_tidr(struct task_struct *t)\n> +{\n> +\tif (t->thread.tidr) {\n> +\t\tfree_thread_tidr(t->thread.tidr);\n> +\t\tt->thread.tidr = 0;\n> +\t\tmtspr(SPRN_TIDR, 0);\n> +\t}\n> +}\n> +\n> +/*\n> + * Assign an unique thread id for this thread and set it in the\n> + * thread structure. For now, we need this interface only for\n> + * the current task.\n> + */\n> +void set_thread_tidr(struct task_struct *t)\n> +{\n> +\tWARN_ON(t != current);\n> +\tt->thread.tidr = assign_thread_tidr();\n> +\tmtspr(SPRN_TIDR, t->thread.tidr);\n> +}\n> +\n> +#endif /* CONFIG_PPC_VAS */\n> +\n> +\n>  void\n>  release_thread(struct task_struct *t)\n>  {\n> +#ifdef CONFIG_PPC_VAS\n> +\tclear_thread_tidr(t);\n> +#endif\n>  }\n> \n>  /*\n> @@ -1474,6 +1566,8 @@ int arch_dup_task_struct(struct task_struct *dst, struct\n> task_struct *src)\n> \n>  \tclear_task_ebb(dst);\n> \n> +\tdst->thread.tidr = 0;\n> +\n>  \treturn 0;\n>  }\n> \n> @@ -1584,6 +1678,9 @@ int copy_thread(unsigned long clone_flags, unsigned long\n> usp,\n>  #endif\n> \n>  \tsetup_ksp_vsid(p, sp);\n> +#ifdef CONFIG_PPC_VAS\n> +\tp->thread.tidr = 0;\n> +#endif\n> \n>  #ifdef CONFIG_PPC64 \n>  \tif (cpu_has_feature(CPU_FTR_DSCR)) {","headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xhxT95s0Vz9sN5\n\tfor ;\n\tWed, 30 Aug 2017 17:09:33 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xhxT92fkDzDqXh\n\tfor ;\n\tWed, 30 Aug 2017 17:09:33 +1000 (AEST)","from ozlabs.org (ozlabs.org [IPv6:2401:3900:2:1::2])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xhxRr416WzDqH0\n\tfor ;\n\tWed, 30 Aug 2017 17:08:24 +1000 (AEST)","from localhost.localdomain (localhost [127.0.0.1])\n\tby ozlabs.org (Postfix) with ESMTP id 3xhxRr2kJFz9sN5;\n\tWed, 30 Aug 2017 17:08:24 +1000 (AEST)","by localhost.localdomain (Postfix, from userid 1000)\n\tid 5291BEEDE21; Wed, 30 Aug 2017 17:08:24 +1000 (AEST)"],"Message-ID":"<1504076904.4670.20.camel@neuling.org>","Subject":"Re: [PATCH RFC] Interface to set SPRN_TIDR","From":"Michael Neuling ","To":"Sukadev Bhattiprolu , Michael Ellerman\n\t, Benjamin Herrenschmidt , \n\tnpiggin@gmail.com","Date":"Wed, 30 Aug 2017 17:08:24 +1000","In-Reply-To":"<20170830023856.GC26152@us.ibm.com>","References":"<20170830023856.GC26152@us.ibm.com>","Content-Type":"text/plain; charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable","X-Mailer":"Evolution 3.22.6-1ubuntu1 ","Mime-Version":"1.0","X-BeenThere":"linuxppc-dev@lists.ozlabs.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"Linux on PowerPC Developers Mail List\n\t","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"linuxppc-dev@lists.ozlabs.org,\n\tChristophe Lombard ","Errors-To":"linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org","Sender":"\"Linuxppc-dev\"\n\t"}},{"id":1760574,"web_url":"http://patchwork.ozlabs.org/comment/1760574/","msgid":"<20170830233208.GC20351@us.ibm.com>","date":"2017-08-30T23:32:08","subject":"Re: [PATCH RFC] Interface to set SPRN_TIDR","submitter":{"id":984,"url":"http://patchwork.ozlabs.org/api/people/984/","name":"Sukadev Bhattiprolu","email":"sukadev@linux.vnet.ibm.com"},"content":"Michael Neuling [mikey@neuling.org] wrote:\n> Suka,\n> \n> Please CC Christophe who as an alternative way of doing this. We ned to get\n> agreement across all users of TIDR/AS_notify...\n\nMikey,\n\nThanks. There is overlap between the two patches. I will send a patch on\ntop of Christophe's for the interfaces to assign/clear the TIDR value and\nclear the thread->tidr during arch_dup_task_struct(). I will also drop the\nCONFIG_VAS check since its not only for VAS.\n\nChristophe, can you let me know of any other comments on this patch?\n\nSuka\n> \n> His patch is here:\n> https://lists.ozlabs.org/pipermail/linuxppc-dev/2017-August/161582.html\n> \n> Mikey\n> \n> On Tue, 2017-08-29 at 19:38 -0700, Sukadev Bhattiprolu wrote:\n> > We need the SPRN_TIDR to be set for use with fast thread-wakeup\n> > (core-to-core wakeup) in VAS. Each user thread that has a receive\n> > window setup and expects to be notified when a sender issues a paste\n> > needs to have a unique SPRN_TIDR value.\n> > \n> > The SPRN_TIDR value only needs to unique within the process but for\n> > now we use a globally unique thread id as described below.\n> > \n> > Signed-off-by: Sukadev Bhattiprolu \n> > ---\n> > Changelog[v2]\n> > \t- Michael Ellerman: Use an interface to assign TIDR so it is\n> > \t  assigned to only threads that need it; move assignment to\n> > \t  restore_sprs(). Drop lint from rebase;\n> > \n> > \n> >  arch/powerpc/include/asm/processor.h |  4 ++\n> >  arch/powerpc/include/asm/switch_to.h |  3 ++\n> >  arch/powerpc/kernel/process.c        | 97\n> > ++++++++++++++++++++++++++++++++++++\n> >  3 files changed, 104 insertions(+)\n> > \n> > diff --git a/arch/powerpc/include/asm/processor.h\n> > b/arch/powerpc/include/asm/processor.h\n> > index fab7ff8..bf6ba63 100644\n> > --- a/arch/powerpc/include/asm/processor.h\n> > +++ b/arch/powerpc/include/asm/processor.h\n> > @@ -232,6 +232,10 @@ struct debug_reg {\n> >  struct thread_struct {\n> >  \tunsigned long\tksp;\t\t/* Kernel stack pointer */\n> > \n> > +#ifdef CONFIG_PPC_VAS\n> > +\tunsigned long\ttidr;\n> > +#endif\n> > +\n> >  #ifdef CONFIG_PPC64\n> >  \tunsigned long\tksp_vsid;\n> >  #endif\n> > diff --git a/arch/powerpc/include/asm/switch_to.h\n> > b/arch/powerpc/include/asm/switch_to.h\n> > index 17c8380..4962455 100644\n> > --- a/arch/powerpc/include/asm/switch_to.h\n> > +++ b/arch/powerpc/include/asm/switch_to.h\n> > @@ -91,4 +91,7 @@ static inline void clear_task_ebb(struct task_struct *t)\n> >  #endif\n> >  }\n> > \n> > +extern void set_thread_tidr(struct task_struct *t);\n> > +extern void clear_thread_tidr(struct task_struct *t);\n> > +\n> >  #endif /* _ASM_POWERPC_SWITCH_TO_H */\n> > diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c\n> > index 1f0fd36..13abb22 100644\n> > --- a/arch/powerpc/kernel/process.c\n> > +++ b/arch/powerpc/kernel/process.c\n> > @@ -1132,6 +1132,10 @@ static inline void restore_sprs(struct thread_struct\n> > *old_thread,\n> >  \t\t\tmtspr(SPRN_TAR, new_thread->tar);\n> >  \t}\n> >  #endif\n> > +#ifdef CONFIG_PPC_VAS\n> > +\tif (old_thread->tidr != new_thread->tidr)\n> > +\t\tmtspr(SPRN_TIDR, new_thread->tidr);\n> > +#endif\n> >  }\n> > \n> >  #ifdef CONFIG_PPC_BOOK3S_64\n> > @@ -1446,9 +1450,97 @@ void flush_thread(void)\n> >  #endif /* CONFIG_HAVE_HW_BREAKPOINT */\n> >  }\n> > \n> > +#ifdef CONFIG_PPC_VAS\n> > +static DEFINE_SPINLOCK(vas_thread_id_lock);\n> > +static DEFINE_IDA(vas_thread_ida);\n> > +\n> > +/*\n> > + * We need to assign an unique thread id to each thread in a process. This\n> > + * thread id is intended to be used with the Fast Thread-wakeup (aka Core-\n> > + * to-core wakeup) mechanism being implemented on top of Virtual Accelerator\n> > + * Switchboard (VAS).\n> > + *\n> > + * To get a unique thread-id per process we could simply use task_pid_nr()\n> > + * but the problem is that task_pid_nr() is not yet available for the thread\n> > + * when copy_thread() is called. Fixing that would require changing more\n> > + * intrusive arch-neutral code in code path in copy_process()?.\n> > + *\n> > + * Further, to assign unique thread ids within each process, we need an\n> > + * atomic field (or an IDR) in task_struct, which again intrudes into the\n> > + * arch-neutral code.\n> > + *\n> > + * So try to assign globally unique thraed ids for now.\n> > + *\n> > + * NOTE: TIDR 0 indicates that the thread does not need a TIDR value.\n> > + * \t For now, only threads that expect to be notified by the VAS\n> > + * \t hardware need a TIDR value and we assign values > 0 for those.\n> > + */\n> > +#define MAX_THREAD_CONTEXT\t((1 << 15) - 2)\n> > +static int assign_thread_tidr(void)\n> > +{\n> > +\tint index;\n> > +\tint err;\n> > +\n> > +again:\n> > +\tif (!ida_pre_get(&vas_thread_ida, GFP_KERNEL))\n> > +\t\treturn -ENOMEM;\n> > +\n> > +\tspin_lock(&vas_thread_id_lock);\n> > +\terr = ida_get_new_above(&vas_thread_ida, 1, &index);\n> > +\tspin_unlock(&vas_thread_id_lock);\n> > +\n> > +\tif (err == -EAGAIN)\n> > +\t\tgoto again;\n> > +\telse if (err)\n> > +\t\treturn err;\n> > +\n> > +\tif (index > MAX_THREAD_CONTEXT) {\n> > +\t\tspin_lock(&vas_thread_id_lock);\n> > +\t\tida_remove(&vas_thread_ida, index);\n> > +\t\tspin_unlock(&vas_thread_id_lock);\n> > +\t\treturn -ENOMEM;\n> > +\t}\n> > +\n> > +\treturn index;\n> > +}\n> > +\n> > +static void free_thread_tidr(int id)\n> > +{\n> > +\tspin_lock(&vas_thread_id_lock);\n> > +\tida_remove(&vas_thread_ida, id);\n> > +\tspin_unlock(&vas_thread_id_lock);\n> > +}\n> > +\n> > +void clear_thread_tidr(struct task_struct *t)\n> > +{\n> > +\tif (t->thread.tidr) {\n> > +\t\tfree_thread_tidr(t->thread.tidr);\n> > +\t\tt->thread.tidr = 0;\n> > +\t\tmtspr(SPRN_TIDR, 0);\n> > +\t}\n> > +}\n> > +\n> > +/*\n> > + * Assign an unique thread id for this thread and set it in the\n> > + * thread structure. For now, we need this interface only for\n> > + * the current task.\n> > + */\n> > +void set_thread_tidr(struct task_struct *t)\n> > +{\n> > +\tWARN_ON(t != current);\n> > +\tt->thread.tidr = assign_thread_tidr();\n> > +\tmtspr(SPRN_TIDR, t->thread.tidr);\n> > +}\n> > +\n> > +#endif /* CONFIG_PPC_VAS */\n> > +\n> > +\n> >  void\n> >  release_thread(struct task_struct *t)\n> >  {\n> > +#ifdef CONFIG_PPC_VAS\n> > +\tclear_thread_tidr(t);\n> > +#endif\n> >  }\n> > \n> >  /*\n> > @@ -1474,6 +1566,8 @@ int arch_dup_task_struct(struct task_struct *dst, struct\n> > task_struct *src)\n> > \n> >  \tclear_task_ebb(dst);\n> > \n> > +\tdst->thread.tidr = 0;\n> > +\n> >  \treturn 0;\n> >  }\n> > \n> > @@ -1584,6 +1678,9 @@ int copy_thread(unsigned long clone_flags, unsigned long\n> > usp,\n> >  #endif\n> > \n> >  \tsetup_ksp_vsid(p, sp);\n> > +#ifdef CONFIG_PPC_VAS\n> > +\tp->thread.tidr = 0;\n> > +#endif\n> > \n> >  #ifdef CONFIG_PPC64 \n> >  \tif (cpu_has_feature(CPU_FTR_DSCR)) {","headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xjMJF2VBVz9s7f\n\tfor ;\n\tThu, 31 Aug 2017 09:33:17 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xjMJF1XVrzDqgp\n\tfor ;\n\tThu, 31 Aug 2017 09:33:17 +1000 (AEST)","from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com\n\t[148.163.158.5])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xjMH53yglzDqF4\n\tfor ;\n\tThu, 31 Aug 2017 09:32:17 +1000 (AEST)","from pps.filterd (m0098419.ppops.net [127.0.0.1])\n\tby mx0b-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv7UNSg0m014698\n\tfor ; Wed, 30 Aug 2017 19:32:14 -0400","from e37.co.us.ibm.com (e37.co.us.ibm.com [32.97.110.158])\n\tby mx0b-001b2d01.pphosted.com with ESMTP id 2cp0gjw1fm-1\n\t(version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT)\n\tfor ; Wed, 30 Aug 2017 19:32:14 -0400","from localhost\n\tby e37.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! 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Violators will be prosecuted; \n\tWed, 30 Aug 2017 17:32:10 -0600","from b03ledav001.gho.boulder.ibm.com\n\t(b03ledav001.gho.boulder.ibm.com [9.17.130.232])\n\tby b03cxnp08028.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with\n\tESMTP id v7UNWAp732571574; Wed, 30 Aug 2017 16:32:10 -0700","from b03ledav001.gho.boulder.ibm.com (unknown [127.0.0.1])\n\tby IMSVA (Postfix) with ESMTP id 2699F6E038;\n\tWed, 30 Aug 2017 17:32:10 -0600 (MDT)","from suka-w540.localdomain (unknown [9.70.94.25])\n\tby b03ledav001.gho.boulder.ibm.com (Postfix) with ESMTP id D75136E03F;\n\tWed, 30 Aug 2017 17:32:09 -0600 (MDT)","by suka-w540.localdomain (Postfix, from userid 1000)\n\tid 6F8ED228F9A; Wed, 30 Aug 2017 16:32:08 -0700 (PDT)"],"Date":"Wed, 30 Aug 2017 16:32:08 -0700","From":"Sukadev Bhattiprolu ","To":"Michael Neuling ","Subject":"Re: [PATCH RFC] Interface to set SPRN_TIDR","References":"<20170830023856.GC26152@us.ibm.com>\n\t<1504076904.4670.20.camel@neuling.org>","MIME-Version":"1.0","Content-Type":"text/plain; charset=iso-8859-1","Content-Disposition":"inline","Content-Transfer-Encoding":"quoted-printable","In-Reply-To":"<1504076904.4670.20.camel@neuling.org>","X-Operating-System":"Linux 2.0.32 on an i486","User-Agent":"Mutt/1.7.1 (2016-10-04)","X-TM-AS-GCONF":"00","x-cbid":"17083023-0024-0000-0000-0000171FB56F","X-IBM-SpamModules-Scores":"","X-IBM-SpamModules-Versions":"BY=3.00007638; HX=3.00000241; KW=3.00000007;\n\tPH=3.00000004; SC=3.00000226; SDB=6.00909940; UDB=6.00456416;\n\tIPR=6.00690224; \n\tBA=6.00005562; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009;\n\tZB=6.00000000; \n\tZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00016934;\n\tXFM=3.00000015; UTC=2017-08-30 23:32:12","X-IBM-AV-DETECTION":"SAVI=unused REMOTE=unused XFE=unused","x-cbparentid":"17083023-0025-0000-0000-00004C861E1E","Message-Id":"<20170830233208.GC20351@us.ibm.com>","X-Proofpoint-Virus-Version":"vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-08-30_09:, , signatures=0","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n\tspamscore=0 suspectscore=1\n\tmalwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam\n\tadjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000\n\tdefinitions=main-1708300358","X-BeenThere":"linuxppc-dev@lists.ozlabs.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"Linux on PowerPC Developers Mail List\n\t","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"linuxppc-dev@lists.ozlabs.org,\n\tChristophe Lombard , npiggin@gmail.com","Errors-To":"linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org","Sender":"\"Linuxppc-dev\"\n\t"}},{"id":1761100,"web_url":"http://patchwork.ozlabs.org/comment/1761100/","msgid":"<9cfefb69-3a3f-a4df-2ba1-cbcf13e1fadc@linux.vnet.ibm.com>","date":"2017-08-31T15:14:51","subject":"Re: [PATCH RFC] Interface to set SPRN_TIDR","submitter":{"id":41411,"url":"http://patchwork.ozlabs.org/api/people/41411/","name":"Philippe Bergheaud","email":"felix@linux.vnet.ibm.com"},"content":"On 31/08/2017 01:32, Sukadev Bhattiprolu wrote:\n> Michael Neuling [mikey@neuling.org] wrote:\n>> Suka,\n>>\n>> Please CC Christophe who as an alternative way of doing this. We ned to get\n>> agreement across all users of TIDR/AS_notify...\n> Mikey,\n>\n> Thanks. There is overlap between the two patches. I will send a patch on\n> top of Christophe's for the interfaces to assign/clear the TIDR value and\n> clear the thread->tidr during arch_dup_task_struct(). I will also drop the\n> CONFIG_VAS check since its not only for VAS.\n>\n> Christophe, can you let me know of any other comments on this patch?\n>\n> Suka\nSuka,\n\nI am seconding Christophe on this matter. I think that your patch now \nfulfills the CAPI use case requirements, with one exception: CAPI does \nnot restrict assigning a thread id to the current task. Please find a \nfew minor questions below.\n\nPhilippe\n\n>> His patch is here:\n>> https://urldefense.proofpoint.com/v2/url?u=https-3A__lists.ozlabs.org_pipermail_linuxppc-2Ddev_2017-2DAugust_161582.html&d=DwIFAw&c=jf_iaSHvJObTbx-siA1ZOg&r=KC0fX9VGJYXlSiH9qN2ZONDbh8vUCZFX8GUhF3rHAvg&m=XQenBfWewOBjWopgf1Fh2UAVGnlzq766MNuzx7jYfuA&s=07WOVTh9f_4IBZfCJes4lvc7LWenBlqVfAXIXxL2QH4&e=\n>>\n>> Mikey\n>>\n>> On Tue, 2017-08-29 at 19:38 -0700, Sukadev Bhattiprolu wrote:\n>>> We need the SPRN_TIDR to be set for use with fast thread-wakeup\n>>> (core-to-core wakeup) in VAS. Each user thread that has a receive\n>>> window setup and expects to be notified when a sender issues a paste\n>>> needs to have a unique SPRN_TIDR value.\n>>>\n>>> The SPRN_TIDR value only needs to unique within the process but for\n>>> now we use a globally unique thread id as described below.\n>>>\n>>> Signed-off-by: Sukadev Bhattiprolu \n>>> ---\n>>> Changelog[v2]\n>>> \t- Michael Ellerman: Use an interface to assign TIDR so it is\n>>> \t assigned to only threads that need it; move assignment to\n>>> \t restore_sprs(). Drop lint from rebase;\n>>>\n>>>\n>>> arch/powerpc/include/asm/processor.h | 4 ++\n>>> arch/powerpc/include/asm/switch_to.h | 3 ++\n>>> arch/powerpc/kernel/process.c | 97\n>>> ++++++++++++++++++++++++++++++++++++\n>>> 3 files changed, 104 insertions(+)\n>>>\n>>> diff --git a/arch/powerpc/include/asm/processor.h\n>>> b/arch/powerpc/include/asm/processor.h\n>>> index fab7ff8..bf6ba63 100644\n>>> --- a/arch/powerpc/include/asm/processor.h\n>>> +++ b/arch/powerpc/include/asm/processor.h\n>>> @@ -232,6 +232,10 @@ struct debug_reg {\n>>> struct thread_struct {\n>>> \tunsigned long\tksp;\t\t/* Kernel stack pointer */\n>>>\n>>> +#ifdef CONFIG_PPC_VAS\n>>> +\tunsigned long\ttidr;\n>>> +#endif\n>>> +\n>>> #ifdef CONFIG_PPC64\n>>> \tunsigned long\tksp_vsid;\n>>> #endif\n>>> diff --git a/arch/powerpc/include/asm/switch_to.h\n>>> b/arch/powerpc/include/asm/switch_to.h\n>>> index 17c8380..4962455 100644\n>>> --- a/arch/powerpc/include/asm/switch_to.h\n>>> +++ b/arch/powerpc/include/asm/switch_to.h\n>>> @@ -91,4 +91,7 @@ static inline void clear_task_ebb(struct task_struct *t)\n>>> #endif\n>>> }\n>>>\n>>> +extern void set_thread_tidr(struct task_struct *t);\n>>> +extern void clear_thread_tidr(struct task_struct *t);\n>>> +\n>>> #endif /* _ASM_POWERPC_SWITCH_TO_H */\n>>> diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c\n>>> index 1f0fd36..13abb22 100644\n>>> --- a/arch/powerpc/kernel/process.c\n>>> +++ b/arch/powerpc/kernel/process.c\n>>> @@ -1132,6 +1132,10 @@ static inline void restore_sprs(struct thread_struct\n>>> *old_thread,\n>>> \t\t\tmtspr(SPRN_TAR, new_thread->tar);\n>>> \t}\n>>> #endif\n>>> +#ifdef CONFIG_PPC_VAS\n>>> +\tif (old_thread->tidr != new_thread->tidr)\n>>> +\t\tmtspr(SPRN_TIDR, new_thread->tidr);\n>>> +#endif\n>>> }\n>>>\n>>> #ifdef CONFIG_PPC_BOOK3S_64\n>>> @@ -1446,9 +1450,97 @@ void flush_thread(void)\n>>> #endif /* CONFIG_HAVE_HW_BREAKPOINT */\n>>> }\n>>>\n>>> +#ifdef CONFIG_PPC_VAS\n>>> +static DEFINE_SPINLOCK(vas_thread_id_lock);\n>>> +static DEFINE_IDA(vas_thread_ida);\n>>> +\n>>> +/*\n>>> + * We need to assign an unique thread id to each thread in a process. This\n>>> + * thread id is intended to be used with the Fast Thread-wakeup (aka Core-\n>>> + * to-core wakeup) mechanism being implemented on top of Virtual Accelerator\n>>> + * Switchboard (VAS).\n>>> + *\n>>> + * To get a unique thread-id per process we could simply use task_pid_nr()\n>>> + * but the problem is that task_pid_nr() is not yet available for the thread\n>>> + * when copy_thread() is called. Fixing that would require changing more\n>>> + * intrusive arch-neutral code in code path in copy_process()?.\n>>> + *\n>>> + * Further, to assign unique thread ids within each process, we need an\n>>> + * atomic field (or an IDR) in task_struct, which again intrudes into the\n>>> + * arch-neutral code.\n>>> + *\n>>> + * So try to assign globally unique thraed ids for now.\n>>> + *\n>>> + * NOTE: TIDR 0 indicates that the thread does not need a TIDR value.\n>>> + * \t For now, only threads that expect to be notified by the VAS\n>>> + * \t hardware need a TIDR value and we assign values > 0 for those.\n>>> + */\n>>> +#define MAX_THREAD_CONTEXT\t((1 << 15) - 2)\nWhy are you excluding ((1 << 15) - 1)?\n>>> +static int assign_thread_tidr(void)\n>>> +{\n>>> +\tint index;\n>>> +\tint err;\n>>> +\n>>> +again:\n>>> +\tif (!ida_pre_get(&vas_thread_ida, GFP_KERNEL))\n>>> +\t\treturn -ENOMEM;\n>>> +\n>>> +\tspin_lock(&vas_thread_id_lock);\n>>> +\terr = ida_get_new_above(&vas_thread_ida, 1, &index);\nWhy are you excluding 1?\n>>> +\tspin_unlock(&vas_thread_id_lock);\n>>> +\n>>> +\tif (err == -EAGAIN)\n>>> +\t\tgoto again;\n>>> +\telse if (err)\n>>> +\t\treturn err;\n>>> +\n>>> +\tif (index > MAX_THREAD_CONTEXT) {\n>>> +\t\tspin_lock(&vas_thread_id_lock);\n>>> +\t\tida_remove(&vas_thread_ida, index);\n>>> +\t\tspin_unlock(&vas_thread_id_lock);\n>>> +\t\treturn -ENOMEM;\n>>> +\t}\n>>> +\n>>> +\treturn index;\n>>> +}\n>>> +\n>>> +static void free_thread_tidr(int id)\n>>> +{\n>>> +\tspin_lock(&vas_thread_id_lock);\n>>> +\tida_remove(&vas_thread_ida, id);\n>>> +\tspin_unlock(&vas_thread_id_lock);\n>>> +}\n>>> +\n>>> +void clear_thread_tidr(struct task_struct *t)\n>>> +{\n>>> +\tif (t->thread.tidr) {\n>>> +\t\tfree_thread_tidr(t->thread.tidr);\n>>> +\t\tt->thread.tidr = 0;\n>>> +\t\tmtspr(SPRN_TIDR, 0);\n>>> +\t}\n>>> +}\n>>> +\n>>> +/*\n>>> + * Assign an unique thread id for this thread and set it in the\n>>> + * thread structure. For now, we need this interface only for\n>>> + * the current task.\n>>> + */\n>>> +void set_thread_tidr(struct task_struct *t)\n>>> +{\n>>> +\tWARN_ON(t != current);\nCAPI does not have this restriction. It should be possible to assign a \nthread id to an arbitrary task.\n>>> +\tt->thread.tidr = assign_thread_tidr();\n>>> +\tmtspr(SPRN_TIDR, t->thread.tidr);\n>>> +}\n>>> +\n>>> +#endif /* CONFIG_PPC_VAS */\n>>> +\n>>> +\n>>> void\n>>> release_thread(struct task_struct *t)\n>>> {\n>>> +#ifdef CONFIG_PPC_VAS\n>>> +\tclear_thread_tidr(t);\n>>> +#endif\n>>> }\n>>>\n>>> /*\n>>> @@ -1474,6 +1566,8 @@ int arch_dup_task_struct(struct task_struct *dst, struct\n>>> task_struct *src)\n>>>\n>>> \tclear_task_ebb(dst);\n>>>\n>>> +\tdst->thread.tidr = 0;\n>>> +\n>>> \treturn 0;\n>>> }\n>>>\n>>> @@ -1584,6 +1678,9 @@ int copy_thread(unsigned long clone_flags, unsigned long\n>>> usp,\n>>> #endif\n>>>\n>>> \tsetup_ksp_vsid(p, sp);\n>>> +#ifdef CONFIG_PPC_VAS\n>>> +\tp->thread.tidr = 0;\n>>> +#endif\n>>>\n>>> #ifdef CONFIG_PPC64\n>>> \tif (cpu_has_feature(CPU_FTR_DSCR)) {","headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xjmDW59ZFz9s7c\n\tfor ;\n\tFri, 1 Sep 2017 01:16:27 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xjmDW49bwzDqTy\n\tfor ;\n\tFri, 1 Sep 2017 01:16:27 +1000 (AEST)","from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com\n\t[148.163.156.1])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xjmBv0ZyHzDqGZ\n\tfor ;\n\tFri, 1 Sep 2017 01:15:02 +1000 (AEST)","from pps.filterd (m0098404.ppops.net [127.0.0.1])\n\tby mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv7VFDO4V035774\n\tfor ; Thu, 31 Aug 2017 11:15:00 -0400","from e06smtp14.uk.ibm.com (e06smtp14.uk.ibm.com [195.75.94.110])\n\tby mx0a-001b2d01.pphosted.com with ESMTP id 2cpkvgugtn-1\n\t(version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT)\n\tfor ; Thu, 31 Aug 2017 11:14:57 -0400","from localhost\n\tby e06smtp14.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! Violators will be prosecuted\n\tfor from ; \n\tThu, 31 Aug 2017 16:14:54 +0100","from b06cxnps4076.portsmouth.uk.ibm.com (9.149.109.198)\n\tby e06smtp14.uk.ibm.com (192.168.101.144) with IBM ESMTP SMTP\n\tGateway: Authorized Use Only! Violators will be prosecuted; \n\tThu, 31 Aug 2017 16:14:53 +0100","from d06av24.portsmouth.uk.ibm.com (mk.ibm.com [9.149.105.60])\n\tby b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with\n\tESMTP id v7VFEqIP15138882; Thu, 31 Aug 2017 15:14:52 GMT","from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1])\n\tby IMSVA (Postfix) with ESMTP id 8BC1C42041;\n\tThu, 31 Aug 2017 16:11:29 +0100 (BST)","from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1])\n\tby IMSVA (Postfix) with ESMTP id 4A4BC4203F;\n\tThu, 31 Aug 2017 16:11:29 +0100 (BST)","from [9.101.4.37] (unknown [9.101.4.37])\n\tby d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTPS;\n\tThu, 31 Aug 2017 16:11:29 +0100 (BST)"],"Subject":"Re: [PATCH RFC] Interface to set SPRN_TIDR","To":"Sukadev Bhattiprolu ,\n\tMichael Neuling ","References":"<20170830023856.GC26152@us.ibm.com>\n\t<1504076904.4670.20.camel@neuling.org>\n\t<20170830233208.GC20351@us.ibm.com>","From":"felix ","Date":"Thu, 31 Aug 2017 17:14:51 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101\n\tThunderbird/45.2.0","MIME-Version":"1.0","In-Reply-To":"<20170830233208.GC20351@us.ibm.com>","Content-Type":"text/plain; charset=windows-1252; format=flowed","Content-Transfer-Encoding":"7bit","X-TM-AS-GCONF":"00","x-cbid":"17083115-0016-0000-0000-000004E7C4C3","X-IBM-AV-DETECTION":"SAVI=unused REMOTE=unused XFE=unused","x-cbparentid":"17083115-0017-0000-0000-000028214487","Message-Id":"<9cfefb69-3a3f-a4df-2ba1-cbcf13e1fadc@linux.vnet.ibm.com>","X-Proofpoint-Virus-Version":"vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-08-31_05:, , signatures=0","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n\tspamscore=0 suspectscore=1\n\tmalwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam\n\tadjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000\n\tdefinitions=main-1708310226","X-BeenThere":"linuxppc-dev@lists.ozlabs.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"Linux on PowerPC Developers Mail List\n\t","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"linuxppc-dev@lists.ozlabs.org,\n\tChristophe Lombard , npiggin@gmail.com","Errors-To":"linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org","Sender":"\"Linuxppc-dev\"\n\t"}},{"id":1761238,"web_url":"http://patchwork.ozlabs.org/comment/1761238/","msgid":"<20170831180618.GA31814@us.ibm.com>","date":"2017-08-31T18:06:18","subject":"Re: [PATCH RFC] Interface to set SPRN_TIDR","submitter":{"id":984,"url":"http://patchwork.ozlabs.org/api/people/984/","name":"Sukadev Bhattiprolu","email":"sukadev@linux.vnet.ibm.com"},"content":"felix [felix@linux.vnet.ibm.com] wrote:\n> On 31/08/2017 01:32, Sukadev Bhattiprolu wrote:\n> > Michael Neuling [mikey@neuling.org] wrote:\n> > > Suka,\n> > > \n> > > Please CC Christophe who as an alternative way of doing this. We ned to get\n> > > agreement across all users of TIDR/AS_notify...\n> > Mikey,\n> > \n> > Thanks. There is overlap between the two patches. I will send a patch on\n> > top of Christophe's for the interfaces to assign/clear the TIDR value and\n> > clear the thread->tidr during arch_dup_task_struct(). I will also drop the\n> > CONFIG_VAS check since its not only for VAS.\n> > \n> > Christophe, can you let me know of any other comments on this patch?\n> > \n> > Suka\n> Suka,\n> \n> I am seconding Christophe on this matter. I think that your patch now\n> fulfills the CAPI use case requirements, with one exception: CAPI does not\n> restrict assigning a thread id to the current task. Please find a few minor\n> questions below.\n> \n> Philippe\n> \n> > > His patch is here:\n> > > https://urldefense.proofpoint.com/v2/url?u=https-3A__lists.ozlabs.org_pipermail_linuxppc-2Ddev_2017-2DAugust_161582.html&d=DwIFAw&c=jf_iaSHvJObTbx-siA1ZOg&r=KC0fX9VGJYXlSiH9qN2ZONDbh8vUCZFX8GUhF3rHAvg&m=XQenBfWewOBjWopgf1Fh2UAVGnlzq766MNuzx7jYfuA&s=07WOVTh9f_4IBZfCJes4lvc7LWenBlqVfAXIXxL2QH4&e=\n> > > \n> > > Mikey\n> > > \n> > > On Tue, 2017-08-29 at 19:38 -0700, Sukadev Bhattiprolu wrote:\n> > > > We need the SPRN_TIDR to be set for use with fast thread-wakeup\n> > > > (core-to-core wakeup) in VAS. Each user thread that has a receive\n> > > > window setup and expects to be notified when a sender issues a paste\n> > > > needs to have a unique SPRN_TIDR value.\n> > > > \n> > > > The SPRN_TIDR value only needs to unique within the process but for\n> > > > now we use a globally unique thread id as described below.\n> > > > \n> > > > Signed-off-by: Sukadev Bhattiprolu \n> > > > ---\n> > > > Changelog[v2]\n> > > > \t- Michael Ellerman: Use an interface to assign TIDR so it is\n> > > > \t assigned to only threads that need it; move assignment to\n> > > > \t restore_sprs(). Drop lint from rebase;\n> > > > \n> > > > \n> > > > arch/powerpc/include/asm/processor.h | 4 ++\n> > > > arch/powerpc/include/asm/switch_to.h | 3 ++\n> > > > arch/powerpc/kernel/process.c | 97\n> > > > ++++++++++++++++++++++++++++++++++++\n> > > > 3 files changed, 104 insertions(+)\n> > > > \n> > > > diff --git a/arch/powerpc/include/asm/processor.h\n> > > > b/arch/powerpc/include/asm/processor.h\n> > > > index fab7ff8..bf6ba63 100644\n> > > > --- a/arch/powerpc/include/asm/processor.h\n> > > > +++ b/arch/powerpc/include/asm/processor.h\n> > > > @@ -232,6 +232,10 @@ struct debug_reg {\n> > > > struct thread_struct {\n> > > > \tunsigned long\tksp;\t\t/* Kernel stack pointer */\n> > > > \n> > > > +#ifdef CONFIG_PPC_VAS\n> > > > +\tunsigned long\ttidr;\n> > > > +#endif\n> > > > +\n> > > > #ifdef CONFIG_PPC64\n> > > > \tunsigned long\tksp_vsid;\n> > > > #endif\n> > > > diff --git a/arch/powerpc/include/asm/switch_to.h\n> > > > b/arch/powerpc/include/asm/switch_to.h\n> > > > index 17c8380..4962455 100644\n> > > > --- a/arch/powerpc/include/asm/switch_to.h\n> > > > +++ b/arch/powerpc/include/asm/switch_to.h\n> > > > @@ -91,4 +91,7 @@ static inline void clear_task_ebb(struct task_struct *t)\n> > > > #endif\n> > > > }\n> > > > \n> > > > +extern void set_thread_tidr(struct task_struct *t);\n> > > > +extern void clear_thread_tidr(struct task_struct *t);\n> > > > +\n> > > > #endif /* _ASM_POWERPC_SWITCH_TO_H */\n> > > > diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c\n> > > > index 1f0fd36..13abb22 100644\n> > > > --- a/arch/powerpc/kernel/process.c\n> > > > +++ b/arch/powerpc/kernel/process.c\n> > > > @@ -1132,6 +1132,10 @@ static inline void restore_sprs(struct thread_struct\n> > > > *old_thread,\n> > > > \t\t\tmtspr(SPRN_TAR, new_thread->tar);\n> > > > \t}\n> > > > #endif\n> > > > +#ifdef CONFIG_PPC_VAS\n> > > > +\tif (old_thread->tidr != new_thread->tidr)\n> > > > +\t\tmtspr(SPRN_TIDR, new_thread->tidr);\n> > > > +#endif\n> > > > }\n> > > > \n> > > > #ifdef CONFIG_PPC_BOOK3S_64\n> > > > @@ -1446,9 +1450,97 @@ void flush_thread(void)\n> > > > #endif /* CONFIG_HAVE_HW_BREAKPOINT */\n> > > > }\n> > > > \n> > > > +#ifdef CONFIG_PPC_VAS\n> > > > +static DEFINE_SPINLOCK(vas_thread_id_lock);\n> > > > +static DEFINE_IDA(vas_thread_ida);\n> > > > +\n> > > > +/*\n> > > > + * We need to assign an unique thread id to each thread in a process. This\n> > > > + * thread id is intended to be used with the Fast Thread-wakeup (aka Core-\n> > > > + * to-core wakeup) mechanism being implemented on top of Virtual Accelerator\n> > > > + * Switchboard (VAS).\n> > > > + *\n> > > > + * To get a unique thread-id per process we could simply use task_pid_nr()\n> > > > + * but the problem is that task_pid_nr() is not yet available for the thread\n> > > > + * when copy_thread() is called. Fixing that would require changing more\n> > > > + * intrusive arch-neutral code in code path in copy_process()?.\n> > > > + *\n> > > > + * Further, to assign unique thread ids within each process, we need an\n> > > > + * atomic field (or an IDR) in task_struct, which again intrudes into the\n> > > > + * arch-neutral code.\n> > > > + *\n> > > > + * So try to assign globally unique thraed ids for now.\n> > > > + *\n> > > > + * NOTE: TIDR 0 indicates that the thread does not need a TIDR value.\n> > > > + * \t For now, only threads that expect to be notified by the VAS\n> > > > + * \t hardware need a TIDR value and we assign values > 0 for those.\n> > > > + */\n> > > > +#define MAX_THREAD_CONTEXT\t((1 << 15) - 2)\n> Why are you excluding ((1 << 15) - 1)?\n\nYou are right. I don't need to exclude that. Also, TIDR is a 16-bit (0:15 in\nVAS's Local Notify TID) value right? So, will change to\n\n\t#define MAX_THREAD_CONTEXT\t((1 << 16) - 1)\n\n> > > > +static int assign_thread_tidr(void)\n> > > > +{\n> > > > +\tint index;\n> > > > +\tint err;\n> > > > +\n> > > > +again:\n> > > > +\tif (!ida_pre_get(&vas_thread_ida, GFP_KERNEL))\n> > > > +\t\treturn -ENOMEM;\n> > > > +\n> > > > +\tspin_lock(&vas_thread_id_lock);\n> > > > +\terr = ida_get_new_above(&vas_thread_ida, 1, &index);\n> Why are you excluding 1?\n\nI think the \"_above\" in the name is misleading. The function header for\nida_get_new_above() says \"above or equal\" so 1 is not excluded?\n\n> > > > +\tspin_unlock(&vas_thread_id_lock);\n> > > > +\n> > > > +\tif (err == -EAGAIN)\n> > > > +\t\tgoto again;\n> > > > +\telse if (err)\n> > > > +\t\treturn err;\n> > > > +\n> > > > +\tif (index > MAX_THREAD_CONTEXT) {\n> > > > +\t\tspin_lock(&vas_thread_id_lock);\n> > > > +\t\tida_remove(&vas_thread_ida, index);\n> > > > +\t\tspin_unlock(&vas_thread_id_lock);\n> > > > +\t\treturn -ENOMEM;\n> > > > +\t}\n> > > > +\n> > > > +\treturn index;\n> > > > +}\n> > > > +\n> > > > +static void free_thread_tidr(int id)\n> > > > +{\n> > > > +\tspin_lock(&vas_thread_id_lock);\n> > > > +\tida_remove(&vas_thread_ida, id);\n> > > > +\tspin_unlock(&vas_thread_id_lock);\n> > > > +}\n> > > > +\n> > > > +void clear_thread_tidr(struct task_struct *t)\n> > > > +{\n> > > > +\tif (t->thread.tidr) {\n> > > > +\t\tfree_thread_tidr(t->thread.tidr);\n> > > > +\t\tt->thread.tidr = 0;\n> > > > +\t\tmtspr(SPRN_TIDR, 0);\n> > > > +\t}\n> > > > +}\n> > > > +\n> > > > +/*\n> > > > + * Assign an unique thread id for this thread and set it in the\n> > > > + * thread structure. For now, we need this interface only for\n> > > > + * the current task.\n> > > > + */\n> > > > +void set_thread_tidr(struct task_struct *t)\n> > > > +{\n> > > > +\tWARN_ON(t != current);\n> CAPI does not have this restriction. It should be possible to assign a\n> thread id to an arbitrary task.\n\nI see. We (or caller) just have to figure out the locking for the task.\n\n> > > > +\tt->thread.tidr = assign_thread_tidr();\n> > > > +\tmtspr(SPRN_TIDR, t->thread.tidr);\n> > > > +}\n> > > > +","headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xjr2T1Wz7z9s7c\n\tfor ;\n\tFri, 1 Sep 2017 04:08:01 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xjr2S6DlPzDqV5\n\tfor ;\n\tFri, 1 Sep 2017 04:08:00 +1000 (AEST)","from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com\n\t[148.163.158.5])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xjr0g03tnzDqGZ\n\tfor ;\n\tFri, 1 Sep 2017 04:06:26 +1000 (AEST)","from pps.filterd (m0098414.ppops.net [127.0.0.1])\n\tby mx0b-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv7VI441K015996\n\tfor ; Thu, 31 Aug 2017 14:06:23 -0400","from e35.co.us.ibm.com (e35.co.us.ibm.com [32.97.110.153])\n\tby mx0b-001b2d01.pphosted.com with ESMTP id 2cpjw8yc8a-1\n\t(version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT)\n\tfor ; Thu, 31 Aug 2017 14:06:23 -0400","from localhost\n\tby e35.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! 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We ned to get\n>>>> agreement across all users of TIDR/AS_notify...\n>>> Mikey,\n>>>\n>>> Thanks. There is overlap between the two patches. I will send a patch on\n>>> top of Christophe's for the interfaces to assign/clear the TIDR value and\n>>> clear the thread->tidr during arch_dup_task_struct(). I will also drop the\n>>> CONFIG_VAS check since its not only for VAS.\n>>>\n>>> Christophe, can you let me know of any other comments on this patch?\n>>>\n>>> Suka\n>> Suka,\n>>\n>> I am seconding Christophe on this matter. I think that your patch now\n>> fulfills the CAPI use case requirements, with one exception: CAPI does not\n>> restrict assigning a thread id to the current task. Please find a few minor\n>> questions below.\n>>\n>> Philippe\n>>\n>>>> His patch is here:\n>>>> https://urldefense.proofpoint.com/v2/url?u=https-3A__lists.ozlabs.org_pipermail_linuxppc-2Ddev_2017-2DAugust_161582.html&d=DwIFAw&c=jf_iaSHvJObTbx-siA1ZOg&r=KC0fX9VGJYXlSiH9qN2ZONDbh8vUCZFX8GUhF3rHAvg&m=XQenBfWewOBjWopgf1Fh2UAVGnlzq766MNuzx7jYfuA&s=07WOVTh9f_4IBZfCJes4lvc7LWenBlqVfAXIXxL2QH4&e=\n>>>>\n>>>> Mikey\n>>>>\n>>>> On Tue, 2017-08-29 at 19:38 -0700, Sukadev Bhattiprolu wrote:\n>>>>> We need the SPRN_TIDR to be set for use with fast thread-wakeup\n>>>>> (core-to-core wakeup) in VAS. Each user thread that has a receive\n>>>>> window setup and expects to be notified when a sender issues a paste\n>>>>> needs to have a unique SPRN_TIDR value.\n>>>>>\n>>>>> The SPRN_TIDR value only needs to unique within the process but for\n>>>>> now we use a globally unique thread id as described below.\n>>>>>\n>>>>> Signed-off-by: Sukadev Bhattiprolu \n>>>>> ---\n>>>>> Changelog[v2]\n>>>>> \t- Michael Ellerman: Use an interface to assign TIDR so it is\n>>>>> \t assigned to only threads that need it; move assignment to\n>>>>> \t restore_sprs(). Drop lint from rebase;\n>>>>>\n>>>>>\n>>>>> arch/powerpc/include/asm/processor.h | 4 ++\n>>>>> arch/powerpc/include/asm/switch_to.h | 3 ++\n>>>>> arch/powerpc/kernel/process.c | 97\n>>>>> ++++++++++++++++++++++++++++++++++++\n>>>>> 3 files changed, 104 insertions(+)\n>>>>>\n>>>>> diff --git a/arch/powerpc/include/asm/processor.h\n>>>>> b/arch/powerpc/include/asm/processor.h\n>>>>> index fab7ff8..bf6ba63 100644\n>>>>> --- a/arch/powerpc/include/asm/processor.h\n>>>>> +++ b/arch/powerpc/include/asm/processor.h\n>>>>> @@ -232,6 +232,10 @@ struct debug_reg {\n>>>>> struct thread_struct {\n>>>>> \tunsigned long\tksp;\t\t/* Kernel stack pointer */\n>>>>>\n>>>>> +#ifdef CONFIG_PPC_VAS\n>>>>> +\tunsigned long\ttidr;\n>>>>> +#endif\n>>>>> +\n>>>>> #ifdef CONFIG_PPC64\n>>>>> \tunsigned long\tksp_vsid;\n>>>>> #endif\n>>>>> diff --git a/arch/powerpc/include/asm/switch_to.h\n>>>>> b/arch/powerpc/include/asm/switch_to.h\n>>>>> index 17c8380..4962455 100644\n>>>>> --- a/arch/powerpc/include/asm/switch_to.h\n>>>>> +++ b/arch/powerpc/include/asm/switch_to.h\n>>>>> @@ -91,4 +91,7 @@ static inline void clear_task_ebb(struct task_struct *t)\n>>>>> #endif\n>>>>> }\n>>>>>\n>>>>> +extern void set_thread_tidr(struct task_struct *t);\n>>>>> +extern void clear_thread_tidr(struct task_struct *t);\n>>>>> +\n>>>>> #endif /* _ASM_POWERPC_SWITCH_TO_H */\n>>>>> diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c\n>>>>> index 1f0fd36..13abb22 100644\n>>>>> --- a/arch/powerpc/kernel/process.c\n>>>>> +++ b/arch/powerpc/kernel/process.c\n>>>>> @@ -1132,6 +1132,10 @@ static inline void restore_sprs(struct thread_struct\n>>>>> *old_thread,\n>>>>> \t\t\tmtspr(SPRN_TAR, new_thread->tar);\n>>>>> \t}\n>>>>> #endif\n>>>>> +#ifdef CONFIG_PPC_VAS\n>>>>> +\tif (old_thread->tidr != new_thread->tidr)\n>>>>> +\t\tmtspr(SPRN_TIDR, new_thread->tidr);\n>>>>> +#endif\n>>>>> }\n>>>>>\n>>>>> #ifdef CONFIG_PPC_BOOK3S_64\n>>>>> @@ -1446,9 +1450,97 @@ void flush_thread(void)\n>>>>> #endif /* CONFIG_HAVE_HW_BREAKPOINT */\n>>>>> }\n>>>>>\n>>>>> +#ifdef CONFIG_PPC_VAS\n>>>>> +static DEFINE_SPINLOCK(vas_thread_id_lock);\n>>>>> +static DEFINE_IDA(vas_thread_ida);\n>>>>> +\n>>>>> +/*\n>>>>> + * We need to assign an unique thread id to each thread in a process. This\n>>>>> + * thread id is intended to be used with the Fast Thread-wakeup (aka Core-\n>>>>> + * to-core wakeup) mechanism being implemented on top of Virtual Accelerator\n>>>>> + * Switchboard (VAS).\n>>>>> + *\n>>>>> + * To get a unique thread-id per process we could simply use task_pid_nr()\n>>>>> + * but the problem is that task_pid_nr() is not yet available for the thread\n>>>>> + * when copy_thread() is called. Fixing that would require changing more\n>>>>> + * intrusive arch-neutral code in code path in copy_process()?.\n>>>>> + *\n>>>>> + * Further, to assign unique thread ids within each process, we need an\n>>>>> + * atomic field (or an IDR) in task_struct, which again intrudes into the\n>>>>> + * arch-neutral code.\n>>>>> + *\n>>>>> + * So try to assign globally unique thraed ids for now.\n>>>>> + *\n>>>>> + * NOTE: TIDR 0 indicates that the thread does not need a TIDR value.\n>>>>> + * \t For now, only threads that expect to be notified by the VAS\n>>>>> + * \t hardware need a TIDR value and we assign values > 0 for those.\n>>>>> + */\n>>>>> +#define MAX_THREAD_CONTEXT\t((1 << 15) - 2)\n>> Why are you excluding ((1 << 15) - 1)?\n> You are right. I don't need to exclude that. Also, TIDR is a 16-bit (0:15 in\n> VAS's Local Notify TID) value right? So, will change to\n>\n> \t#define MAX_THREAD_CONTEXT\t((1 << 16) - 1)\nYes.\n>\n>>>>> +static int assign_thread_tidr(void)\n>>>>> +{\n>>>>> +\tint index;\n>>>>> +\tint err;\n>>>>> +\n>>>>> +again:\n>>>>> +\tif (!ida_pre_get(&vas_thread_ida, GFP_KERNEL))\n>>>>> +\t\treturn -ENOMEM;\n>>>>> +\n>>>>> +\tspin_lock(&vas_thread_id_lock);\n>>>>> +\terr = ida_get_new_above(&vas_thread_ida, 1, &index);\n>> Why are you excluding 1?\n> I think the \"_above\" in the name is misleading. The function header for\n> ida_get_new_above() says \"above or equal\" so 1 is not excluded?\nUnderstood.\n>\n>>>>> +\tspin_unlock(&vas_thread_id_lock);\n>>>>> +\n>>>>> +\tif (err == -EAGAIN)\n>>>>> +\t\tgoto again;\n>>>>> +\telse if (err)\n>>>>> +\t\treturn err;\n>>>>> +\n>>>>> +\tif (index > MAX_THREAD_CONTEXT) {\n>>>>> +\t\tspin_lock(&vas_thread_id_lock);\n>>>>> +\t\tida_remove(&vas_thread_ida, index);\n>>>>> +\t\tspin_unlock(&vas_thread_id_lock);\n>>>>> +\t\treturn -ENOMEM;\n>>>>> +\t}\n>>>>> +\n>>>>> +\treturn index;\n>>>>> +}\n>>>>> +\n>>>>> +static void free_thread_tidr(int id)\n>>>>> +{\n>>>>> +\tspin_lock(&vas_thread_id_lock);\n>>>>> +\tida_remove(&vas_thread_ida, id);\n>>>>> +\tspin_unlock(&vas_thread_id_lock);\n>>>>> +}\n>>>>> +\n>>>>> +void clear_thread_tidr(struct task_struct *t)\n>>>>> +{\n>>>>> +\tif (t->thread.tidr) {\n>>>>> +\t\tfree_thread_tidr(t->thread.tidr);\n>>>>> +\t\tt->thread.tidr = 0;\n>>>>> +\t\tmtspr(SPRN_TIDR, 0);\n>>>>> +\t}\n>>>>> +}\n>>>>> +\n>>>>> +/*\n>>>>> + * Assign an unique thread id for this thread and set it in the\n>>>>> + * thread structure. For now, we need this interface only for\n>>>>> + * the current task.\n>>>>> + */\n>>>>> +void set_thread_tidr(struct task_struct *t)\n>>>>> +{\n>>>>> +\tWARN_ON(t != current);\n>> CAPI does not have this restriction. It should be possible to assign a\n>> thread id to an arbitrary task.\n> I see. We (or caller) just have to figure out the locking for the task.\nThe extension to any thread can be implemented in a separate patch. \n'current' will do for now.\n>\n>>>>> +\tt->thread.tidr = assign_thread_tidr();\n>>>>> +\tmtspr(SPRN_TIDR, t->thread.tidr);\n>>>>> +}\n>>>>> +","headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xkDH142Bkz9s72\n\tfor ;\n\tFri, 1 Sep 2017 19:20:13 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xkDH12Y9NzDqn6\n\tfor ;\n\tFri, 1 Sep 2017 19:20:13 +1000 (AEST)","from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com\n\t[148.163.158.5])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xkDF41Y6VzDqjy\n\tfor ;\n\tFri, 1 Sep 2017 19:18:31 +1000 (AEST)","from pps.filterd (m0098414.ppops.net [127.0.0.1])\n\tby mx0b-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv819EHjS042326\n\tfor ; Fri, 1 Sep 2017 05:18:28 -0400","from e06smtp14.uk.ibm.com (e06smtp14.uk.ibm.com [195.75.94.110])\n\tby mx0b-001b2d01.pphosted.com with ESMTP id 2cq1jsku2g-1\n\t(version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT)\n\tfor ; Fri, 01 Sep 2017 05:18:28 -0400","from localhost\n\tby e06smtp14.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! 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Violators will be prosecuted; \n\tFri, 1 Sep 2017 10:18:24 +0100","from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com\n\t[9.149.105.232])\n\tby b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with\n\tESMTP id v819IOXC8978434; Fri, 1 Sep 2017 09:18:24 GMT","from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1])\n\tby IMSVA (Postfix) with ESMTP id 98CC952049;\n\tFri, 1 Sep 2017 09:13:48 +0100 (BST)","from [9.101.4.37] (unknown [9.101.4.37])\n\tby d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id 618105203F; \n\tFri, 1 Sep 2017 09:13:48 +0100 (BST)"],"Subject":"Re: [PATCH RFC] Interface to set SPRN_TIDR","To":"Sukadev Bhattiprolu ","References":"<20170830023856.GC26152@us.ibm.com>\n\t<1504076904.4670.20.camel@neuling.org>\n\t<20170830233208.GC20351@us.ibm.com>\n\t<9cfefb69-3a3f-a4df-2ba1-cbcf13e1fadc@linux.vnet.ibm.com>\n\t<20170831180618.GA31814@us.ibm.com>","From":"Philippe Bergheaud ","Date":"Fri, 1 Sep 2017 11:18:23 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101\n\tThunderbird/45.2.0","MIME-Version":"1.0","In-Reply-To":"<20170831180618.GA31814@us.ibm.com>","Content-Type":"text/plain; charset=windows-1252; format=flowed","Content-Transfer-Encoding":"7bit","X-TM-AS-GCONF":"00","x-cbid":"17090109-0016-0000-0000-000004E7F6DB","X-IBM-AV-DETECTION":"SAVI=unused REMOTE=unused XFE=unused","x-cbparentid":"17090109-0017-0000-0000-0000282179DC","Message-Id":"","X-Proofpoint-Virus-Version":"vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-09-01_02:, , signatures=0","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n\tspamscore=0 suspectscore=1\n\tmalwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam\n\tadjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000\n\tdefinitions=main-1709010136","X-BeenThere":"linuxppc-dev@lists.ozlabs.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"Linux on PowerPC Developers Mail List\n\t","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Michael Neuling , linuxppc-dev@lists.ozlabs.org,\n\tChristophe Lombard , npiggin@gmail.com","Errors-To":"linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org","Sender":"\"Linuxppc-dev\"\n\t"}}]