[{"id":1759848,"web_url":"http://patchwork.ozlabs.org/comment/1759848/","msgid":"<93538cee-a05c-44cc-cd69-3e3c8a0d168e@amsat.org>","list_archive_url":null,"date":"2017-08-30T03:54:06","subject":"Re: [Qemu-devel] [PATCH v2 7/9] AHCI: Rework IRQ constants","submitter":{"id":70924,"url":"http://patchwork.ozlabs.org/api/people/70924/","name":"Philippe Mathieu-Daudé","email":"f4bug@amsat.org"},"content":"On 08/29/2017 05:49 PM, John Snow wrote:\n> Create a new enum so that we can name the IRQ bits, which will make debugging\n> them a little nicer if we can print them out. Not handled in this patch, but\n> this will make it possible to get a nice debug printf detailing exactly which\n> status bits are set, as it can be multiple at any given time.\n> \n> As a consequence of this patch, it is no longer possible to set multiple IRQ\n> codes at once, but nothing was utilizing this ability anyway.\n> \n> Signed-off-by: John Snow \n> ---\n> hw/ide/ahci.c | 49 ++++++++++++++++++++++++++++++++++++++-----------\n> hw/ide/ahci_internal.h | 44 +++++++++++++++++++++++++++++++++++---------\n> hw/ide/trace-events | 2 +-\n> 3 files changed, 74 insertions(+), 21 deletions(-)\n> \n> diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c\n> index c60a000..a0a4dd6 100644\n> --- a/hw/ide/ahci.c\n> +++ b/hw/ide/ahci.c\n> @@ -56,6 +56,27 @@ static bool ahci_map_fis_address(AHCIDevice *ad);\n> static void ahci_unmap_clb_address(AHCIDevice *ad);\n> static void ahci_unmap_fis_address(AHCIDevice *ad);\n> \n> +static const char *AHCIPortIRQ_lookup[AHCI_PORT_IRQ__END] = {\n> + [AHCI_PORT_IRQ_BIT_DHRS] = \"DHRS\",\n> + [AHCI_PORT_IRQ_BIT_PSS] = \"PSS\",\n> + [AHCI_PORT_IRQ_BIT_DSS] = \"DSS\",\n> + [AHCI_PORT_IRQ_BIT_SDBS] = \"SDBS\",\n> + [AHCI_PORT_IRQ_BIT_UFS] = \"UFS\",\n> + [AHCI_PORT_IRQ_BIT_DPS] = \"DPS\",\n> + [AHCI_PORT_IRQ_BIT_PCS] = \"PCS\",\n> + [AHCI_PORT_IRQ_BIT_DMPS] = \"DMPS\",\n> + [8 ... 21] = \"RESERVED\",\n> + [AHCI_PORT_IRQ_BIT_PRCS] = \"PRCS\",\n> + [AHCI_PORT_IRQ_BIT_IPMS] = \"IPMS\",\n> + [AHCI_PORT_IRQ_BIT_OFS] = \"OFS\",\n> + [25] = \"RESERVED\",\n> + [AHCI_PORT_IRQ_BIT_INFS] = \"INFS\",\n> + [AHCI_PORT_IRQ_BIT_IFS] = \"IFS\",\n> + [AHCI_PORT_IRQ_BIT_HBDS] = \"HBDS\",\n> + [AHCI_PORT_IRQ_BIT_HBFS] = \"HBFS\",\n> + [AHCI_PORT_IRQ_BIT_TFES] = \"TFES\",\n> + [AHCI_PORT_IRQ_BIT_CPDS] = \"CPDS\"\n> +};\n> \n> static uint32_t ahci_port_read(AHCIState *s, int port, int offset)\n> {\n> @@ -170,12 +191,18 @@ static void ahci_check_irq(AHCIState *s)\n> }\n> \n> static void ahci_trigger_irq(AHCIState *s, AHCIDevice *d,\n> - int irq_type)\n> + enum AHCIPortIRQ irqbit)\n> {\n> - DPRINTF(d->port_no, \"trigger irq %#x -> %x\\n\",\n> - irq_type, d->port_regs.irq_mask & irq_type);\n> + g_assert(irqbit >= 0 && irqbit < 32);\n\nI still think this assert is superfluous, anyway (and having hard time \nreading C99 statement before declarations - I need to grow):\n\nReviewed-by: Philippe Mathieu-Daudé \n\n> + uint32_t irq = 1U << irqbit;\n> + uint32_t irqstat = d->port_regs.irq_stat | irq;\n> \n> - d->port_regs.irq_stat |= irq_type;\n> + trace_ahci_trigger_irq(s, d->port_no,\n> + AHCIPortIRQ_lookup[irqbit], irq,\n> + d->port_regs.irq_stat, irqstat,\n> + irqstat & d->port_regs.irq_mask);\n> +\n> + d->port_regs.irq_stat = irqstat;\n> ahci_check_irq(s);\n> }\n> \n> @@ -718,7 +745,7 @@ static void ahci_write_fis_sdb(AHCIState *s, NCQTransferState *ncq_tfs)\n> \n> /* Trigger IRQ if interrupt bit is set (which currently, it always is) */\n> if (sdb_fis->flags & 0x40) {\n> - ahci_trigger_irq(s, ad, PORT_IRQ_SDB_FIS);\n> + ahci_trigger_irq(s, ad, AHCI_PORT_IRQ_BIT_SDBS);\n> }\n> }\n> \n> @@ -761,10 +788,10 @@ static void ahci_write_fis_pio(AHCIDevice *ad, uint16_t len)\n> ad->port.ifs[0].status;\n> \n> if (pio_fis[2] & ERR_STAT) {\n> - ahci_trigger_irq(ad->hba, ad, PORT_IRQ_TF_ERR);\n> + ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_TFES);\n> }\n> \n> - ahci_trigger_irq(ad->hba, ad, PORT_IRQ_PIOS_FIS);\n> + ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_PSS);\n> }\n> \n> static bool ahci_write_fis_d2h(AHCIDevice *ad)\n> @@ -804,10 +831,10 @@ static bool ahci_write_fis_d2h(AHCIDevice *ad)\n> ad->port.ifs[0].status;\n> \n> if (d2h_fis[2] & ERR_STAT) {\n> - ahci_trigger_irq(ad->hba, ad, PORT_IRQ_TF_ERR);\n> + ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_TFES);\n> }\n> \n> - ahci_trigger_irq(ad->hba, ad, PORT_IRQ_D2H_REG_FIS);\n> + ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_DHRS);\n> return true;\n> }\n> \n> @@ -1082,7 +1109,7 @@ static void process_ncq_command(AHCIState *s, int port, uint8_t *cmd_fis,\n> \"is smaller than the requested size (0x%zx)\",\n> ncq_tfs->sglist.size, size);\n> ncq_err(ncq_tfs);\n> - ahci_trigger_irq(ad->hba, ad, PORT_IRQ_OVERFLOW);\n> + ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_OFS);\n> return;\n> } else if (ncq_tfs->sglist.size != size) {\n> trace_process_ncq_command_large(s, port, tag,\n> @@ -1225,7 +1252,7 @@ static int handle_cmd(AHCIState *s, int port, uint8_t slot)\n> trace_handle_cmd_badfis(s, port);\n> return -1;\n> } else if (cmd_len != 0x80) {\n> - ahci_trigger_irq(s, &s->dev[port], PORT_IRQ_HBUS_ERR);\n> + ahci_trigger_irq(s, &s->dev[port], AHCI_PORT_IRQ_BIT_HBFS);\n> trace_handle_cmd_badmap(s, port, cmd_len);\n> goto out;\n> }\n> diff --git a/hw/ide/ahci_internal.h b/hw/ide/ahci_internal.h\n> index 1e21169..7e67add 100644\n> --- a/hw/ide/ahci_internal.h\n> +++ b/hw/ide/ahci_internal.h\n> @@ -91,6 +91,31 @@\n> #define PORT_CMD_ISSUE 0x38 /* command issue */\n> #define PORT_RESERVED 0x3c /* reserved */\n> \n> +/* Port interrupt bit descriptors */\n> +enum AHCIPortIRQ {\n> + AHCI_PORT_IRQ_BIT_DHRS = 0,\n> + AHCI_PORT_IRQ_BIT_PSS = 1,\n> + AHCI_PORT_IRQ_BIT_DSS = 2,\n> + AHCI_PORT_IRQ_BIT_SDBS = 3,\n> + AHCI_PORT_IRQ_BIT_UFS = 4,\n> + AHCI_PORT_IRQ_BIT_DPS = 5,\n> + AHCI_PORT_IRQ_BIT_PCS = 6,\n> + AHCI_PORT_IRQ_BIT_DMPS = 7,\n> + /* RESERVED */\n> + AHCI_PORT_IRQ_BIT_PRCS = 22,\n> + AHCI_PORT_IRQ_BIT_IPMS = 23,\n> + AHCI_PORT_IRQ_BIT_OFS = 24,\n> + /* RESERVED */\n> + AHCI_PORT_IRQ_BIT_INFS = 26,\n> + AHCI_PORT_IRQ_BIT_IFS = 27,\n> + AHCI_PORT_IRQ_BIT_HBDS = 28,\n> + AHCI_PORT_IRQ_BIT_HBFS = 29,\n> + AHCI_PORT_IRQ_BIT_TFES = 30,\n> + AHCI_PORT_IRQ_BIT_CPDS = 31,\n> + AHCI_PORT_IRQ__END = 32\n> +};\n> +\n> +\n> /* PORT_IRQ_{STAT,MASK} bits */\n> #define PORT_IRQ_COLD_PRES (1U << 31) /* cold presence detect */\n> #define PORT_IRQ_TF_ERR (1 << 30) /* task file error */\n> @@ -98,18 +123,19 @@\n> #define PORT_IRQ_HBUS_DATA_ERR (1 << 28) /* host bus data error */\n> #define PORT_IRQ_IF_ERR (1 << 27) /* interface fatal error */\n> #define PORT_IRQ_IF_NONFATAL (1 << 26) /* interface non-fatal error */\n> + /* reserved */\n> #define PORT_IRQ_OVERFLOW (1 << 24) /* xfer exhausted available S/G */\n> #define PORT_IRQ_BAD_PMP (1 << 23) /* incorrect port multiplier */\n> -\n> #define PORT_IRQ_PHYRDY (1 << 22) /* PhyRdy changed */\n> -#define PORT_IRQ_DEV_ILCK (1 << 7) /* device interlock */\n> -#define PORT_IRQ_CONNECT (1 << 6) /* port connect change status */\n> -#define PORT_IRQ_SG_DONE (1 << 5) /* descriptor processed */\n> -#define PORT_IRQ_UNK_FIS (1 << 4) /* unknown FIS rx'd */\n> -#define PORT_IRQ_SDB_FIS (1 << 3) /* Set Device Bits FIS rx'd */\n> -#define PORT_IRQ_DMAS_FIS (1 << 2) /* DMA Setup FIS rx'd */\n> -#define PORT_IRQ_PIOS_FIS (1 << 1) /* PIO Setup FIS rx'd */\n> -#define PORT_IRQ_D2H_REG_FIS (1 << 0) /* D2H Register FIS rx'd */\n> + /* reserved */\n> +#define PORT_IRQ_DEV_ILCK (1 << 7) /* device interlock */\n> +#define PORT_IRQ_CONNECT (1 << 6) /* port connect change status */\n> +#define PORT_IRQ_SG_DONE (1 << 5) /* descriptor processed */\n> +#define PORT_IRQ_UNK_FIS (1 << 4) /* unknown FIS rx'd */\n> +#define PORT_IRQ_SDB_FIS (1 << 3) /* Set Device Bits FIS rx'd */\n> +#define PORT_IRQ_DMAS_FIS (1 << 2) /* DMA Setup FIS rx'd */\n> +#define PORT_IRQ_PIOS_FIS (1 << 1) /* PIO Setup FIS rx'd */\n> +#define PORT_IRQ_D2H_REG_FIS (1 << 0) /* D2H Register FIS rx'd */\n> \n> #define PORT_IRQ_FREEZE (PORT_IRQ_HBUS_ERR | PORT_IRQ_IF_ERR | \\\n> PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY | \\\n> diff --git a/hw/ide/trace-events b/hw/ide/trace-events\n> index 0b61c5d..e15fd77 100644\n> --- a/hw/ide/trace-events\n> +++ b/hw/ide/trace-events\n> @@ -62,7 +62,7 @@ ahci_port_read(void *s, int port, int offset, uint32_t ret) \"ahci(%p)[%d]: port\n> ahci_irq_raise(void *s) \"ahci(%p): raise irq\"\n> ahci_irq_lower(void *s) \"ahci(%p): lower irq\"\n> ahci_check_irq(void *s, uint32_t old, uint32_t new) \"ahci(%p): check irq 0x%08x --> 0x%08x\"\n> -\n> +ahci_trigger_irq(void *s, int port, const char *name, uint32_t val, uint32_t old, uint32_t new, uint32_t effective) \"ahci(%p)[%d]: trigger irq +%s (0x%08x); irqstat: 0x%08x --> 0x%08x; effective: 0x%08x\"\n> ahci_port_write(void *s, int port, int offset, uint32_t val) \"ahci(%p)[%d]: port write @ 0x%x: 0x%08x\"\n> ahci_mem_read_32(void *s, uint64_t addr, uint32_t val) \"ahci(%p): mem read @ 0x%\"PRIx64\": 0x%08x\"\n> ahci_mem_read(void *s, unsigned size, uint64_t addr, uint64_t val) \"ahci(%p): read%u @ 0x%\"PRIx64\": 0x%016\"PRIx64\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com 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qemu-block@nongnu.org","References":"<20170829204934.9039-1-jsnow@redhat.com>\n\t<20170829204934.9039-8-jsnow@redhat.com>","From":"=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= ","Message-ID":"<93538cee-a05c-44cc-cd69-3e3c8a0d168e@amsat.org>","Date":"Wed, 30 Aug 2017 00:54:06 -0300","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<20170829204934.9039-8-jsnow@redhat.com>","Content-Type":"text/plain; charset=utf-8; format=flowed","Content-Language":"en-US","Content-Transfer-Encoding":"8bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400d:c09::22e","Subject":"Re: [Qemu-devel] [PATCH v2 7/9] AHCI: Rework IRQ constants","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"qemu-devel@nongnu.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1760573,"web_url":"http://patchwork.ozlabs.org/comment/1760573/","msgid":"<6a5e72c1-526d-0601-6590-08213b2362a6@redhat.com>","list_archive_url":null,"date":"2017-08-30T23:28:02","subject":"Re: [Qemu-devel] [PATCH v2 7/9] AHCI: Rework IRQ constants","submitter":{"id":64343,"url":"http://patchwork.ozlabs.org/api/people/64343/","name":"John Snow","email":"jsnow@redhat.com"},"content":"On 08/29/2017 11:54 PM, Philippe Mathieu-Daudé wrote:\n> On 08/29/2017 05:49 PM, John Snow wrote:\n>> Create a new enum so that we can name the IRQ bits, which will make\n>> debugging\n>> them a little nicer if we can print them out. Not handled in this\n>> patch, but\n>> this will make it possible to get a nice debug printf detailing\n>> exactly which\n>> status bits are set, as it can be multiple at any given time.\n>>\n>> As a consequence of this patch, it is no longer possible to set\n>> multiple IRQ\n>> codes at once, but nothing was utilizing this ability anyway.\n>>\n>> Signed-off-by: John Snow \n>> ---\n>> hw/ide/ahci.c | 49\n>> ++++++++++++++++++++++++++++++++++++++-----------\n>> hw/ide/ahci_internal.h | 44\n>> +++++++++++++++++++++++++++++++++++---------\n>> hw/ide/trace-events | 2 +-\n>> 3 files changed, 74 insertions(+), 21 deletions(-)\n>>\n>> diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c\n>> index c60a000..a0a4dd6 100644\n>> --- a/hw/ide/ahci.c\n>> +++ b/hw/ide/ahci.c\n>> @@ -56,6 +56,27 @@ static bool ahci_map_fis_address(AHCIDevice *ad);\n>> static void ahci_unmap_clb_address(AHCIDevice *ad);\n>> static void ahci_unmap_fis_address(AHCIDevice *ad);\n>> +static const char *AHCIPortIRQ_lookup[AHCI_PORT_IRQ__END] = {\n>> + [AHCI_PORT_IRQ_BIT_DHRS] = \"DHRS\",\n>> + [AHCI_PORT_IRQ_BIT_PSS] = \"PSS\",\n>> + [AHCI_PORT_IRQ_BIT_DSS] = \"DSS\",\n>> + [AHCI_PORT_IRQ_BIT_SDBS] = \"SDBS\",\n>> + [AHCI_PORT_IRQ_BIT_UFS] = \"UFS\",\n>> + [AHCI_PORT_IRQ_BIT_DPS] = \"DPS\",\n>> + [AHCI_PORT_IRQ_BIT_PCS] = \"PCS\",\n>> + [AHCI_PORT_IRQ_BIT_DMPS] = \"DMPS\",\n>> + [8 ... 21] = \"RESERVED\",\n>> + [AHCI_PORT_IRQ_BIT_PRCS] = \"PRCS\",\n>> + [AHCI_PORT_IRQ_BIT_IPMS] = \"IPMS\",\n>> + [AHCI_PORT_IRQ_BIT_OFS] = \"OFS\",\n>> + [25] = \"RESERVED\",\n>> + [AHCI_PORT_IRQ_BIT_INFS] = \"INFS\",\n>> + [AHCI_PORT_IRQ_BIT_IFS] = \"IFS\",\n>> + [AHCI_PORT_IRQ_BIT_HBDS] = \"HBDS\",\n>> + [AHCI_PORT_IRQ_BIT_HBFS] = \"HBFS\",\n>> + [AHCI_PORT_IRQ_BIT_TFES] = \"TFES\",\n>> + [AHCI_PORT_IRQ_BIT_CPDS] = \"CPDS\"\n>> +};\n>> static uint32_t ahci_port_read(AHCIState *s, int port, int offset)\n>> {\n>> @@ -170,12 +191,18 @@ static void ahci_check_irq(AHCIState *s)\n>> }\n>> static void ahci_trigger_irq(AHCIState *s, AHCIDevice *d,\n>> - int irq_type)\n>> + enum AHCIPortIRQ irqbit)\n>> {\n>> - DPRINTF(d->port_no, \"trigger irq %#x -> %x\\n\",\n>> - irq_type, d->port_regs.irq_mask & irq_type);\n>> + g_assert(irqbit >= 0 && irqbit < 32);\n> \n> I still think this assert is superfluous, anyway (and having hard time\n> reading C99 statement before declarations - I need to grow):\n> \n> Reviewed-by: Philippe Mathieu-Daudé \n> \n\nLeft in because of my distrust of compilers as explained in my reply to\n#05. We'll get to the bottom of it ;)\n\nThank you for the reviews.\n\n--js","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ext-mx02.extmail.prod.ext.phx2.redhat.com;\n\tdmarc=none (p=none dis=none) header.from=redhat.com","ext-mx02.extmail.prod.ext.phx2.redhat.com;\n\tspf=fail smtp.mailfrom=jsnow@redhat.com"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xjMBr34Dsz9s7f\n\tfor ;\n\tThu, 31 Aug 2017 09:28:36 +1000 (AEST)","from localhost ([::1]:53210 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dnCPS-000261-IL\n\tfor incoming@patchwork.ozlabs.org; Wed, 30 Aug 2017 19:28:34 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:42824)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1dnCP6-00024n-MN\n\tfor qemu-devel@nongnu.org; Wed, 30 Aug 2017 19:28:13 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1dnCP5-0004hM-Ly\n\tfor qemu-devel@nongnu.org; Wed, 30 Aug 2017 19:28:12 -0400","from mx1.redhat.com ([209.132.183.28]:10091)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1dnCOz-0004dn-2u; Wed, 30 Aug 2017 19:28:05 -0400","from smtp.corp.redhat.com\n\t(int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby mx1.redhat.com (Postfix) with ESMTPS id F2F4E883AD;\n\tWed, 30 Aug 2017 23:28:03 +0000 (UTC)","from [10.18.17.130] (dhcp-17-130.bos.redhat.com [10.18.17.130])\n\tby smtp.corp.redhat.com (Postfix) with ESMTP id 7000D6A317;\n\tWed, 30 Aug 2017 23:28:03 +0000 (UTC)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mx1.redhat.com F2F4E883AD","To":"=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= ,\n\tqemu-block@nongnu.org","References":"<20170829204934.9039-1-jsnow@redhat.com>\n\t<20170829204934.9039-8-jsnow@redhat.com>\n\t<93538cee-a05c-44cc-cd69-3e3c8a0d168e@amsat.org>","From":"John Snow ","Message-ID":"<6a5e72c1-526d-0601-6590-08213b2362a6@redhat.com>","Date":"Wed, 30 Aug 2017 19:28:02 -0400","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"<93538cee-a05c-44cc-cd69-3e3c8a0d168e@amsat.org>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","X-Scanned-By":"MIMEDefang 2.79 on 10.5.11.16","X-Greylist":"Sender IP whitelisted, not delayed by milter-greylist-4.5.16\n\t(mx1.redhat.com [10.5.110.26]);\n\tWed, 30 Aug 2017 23:28:04 +0000 (UTC)","Content-Transfer-Encoding":"quoted-printable","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]","X-Received-From":"209.132.183.28","Subject":"Re: [Qemu-devel] [PATCH v2 7/9] AHCI: Rework IRQ constants","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"qemu-devel@nongnu.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}}]