[{"id":1760226,"web_url":"http://patchwork.ozlabs.org/comment/1760226/","msgid":"<20170830144409.qtewwaffwof34hai@flea.lan>","list_archive_url":null,"date":"2017-08-30T14:44:09","subject":"Re: [RESEND PATCH 1/2] arm64: allwinner: a64: add SPI nodes","submitter":{"id":12916,"url":"http://patchwork.ozlabs.org/api/people/12916/","name":"Maxime Ripard","email":"maxime.ripard@free-electrons.com"},"content":"Hi Stefan,\n\nOn Tue, Aug 29, 2017 at 10:26:51PM +0200, Stefan Brüns wrote:\n> The A64 SPI controllers are register compatible to the h3/h5 SPI\n> controllers.\n> \n> The A64 has two SPI controllers, each with a single chip select.\n> The handles for the DMA channels (23/24 for SPI0/SPI1) are omitted,\n> as the A64 DMA controller node is currently missing.\n> \n> Signed-off-by: Stefan Brüns \n> ---\n> arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 40 +++++++++++++++++++++++++++\n> 1 file changed, 40 insertions(+)\n> \n> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi\n> index bd0f33b77f57..373cd14f0206 100644\n> --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi\n> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi\n> @@ -325,6 +325,16 @@\n> \t\t\t\tdrive-strength = <40>;\n> \t\t\t};\n> \n> +\t\t\tspi0_pins: spi0 {\n> +\t\t\t\tpins = \"PC0\", \"PC1\", \"PC2\", \"PC3\";\n> +\t\t\t\tfunction = \"spi0\";\n> +\t\t\t};\n> +\n> +\t\t\tspi1_pins: spi1 {\n> +\t\t\t\tpins = \"PD0\", \"PD1\", \"PD2\", \"PD3\";\n> +\t\t\t\tfunction = \"spi1\";\n> +\t\t\t};\n> +\n> \t\t\tuart0_pins_a: uart0@0 {\n> \t\t\t\tpins = \"PB8\", \"PB9\";\n> \t\t\t\tfunction = \"uart0\";\n> @@ -527,5 +537,35 @@\n> \t\t\t#address-cells = <1>;\n> \t\t\t#size-cells = <0>;\n> \t\t};\n> +\n> +\t\tspi0: spi@01c68000 {\n> +\t\t\tcompatible = \"allwinner,sun8i-h3-spi\";\n> +\t\t\treg = <0x01c68000 0x1000>;\n> +\t\t\tinterrupts = ;\n> +\t\t\tclocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;\n> +\t\t\tclock-names = \"ahb\", \"mod\";\n> +\t\t\tpinctrl-names = \"default\";\n> +\t\t\tpinctrl-0 = <&spi0_pins>;\n> +\t\t\tresets = <&ccu RST_BUS_SPI0>;\n> +\t\t\tstatus = \"disabled\";\n> +\t\t\tnum-cs = <1>;\n> +\t\t\t#address-cells = <1>;\n> +\t\t\t#size-cells = <0>;\n> +\t\t};\n> +\n> +\t\tspi1: spi@01c69000 {\n> +\t\t\tcompatible = \"allwinner,sun8i-h3-spi\";\n> +\t\t\treg = <0x01c69000 0x1000>;\n> +\t\t\tinterrupts = ;\n> +\t\t\tclocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;\n> +\t\t\tclock-names = \"ahb\", \"mod\";\n> +\t\t\tpinctrl-names = \"default\";\n> +\t\t\tpinctrl-0 = <&spi1_pins>;\n> +\t\t\tresets = <&ccu RST_BUS_SPI1>;\n> +\t\t\tstatus = \"disabled\";\n> +\t\t\tnum-cs = <1>;\n> +\t\t\t#address-cells = <1>;\n> +\t\t\t#size-cells = <0>;\n> +\t\t};\n\nThose nodes are ordered by ascending physical base address, so they\nbelong a bit above were you placed them.\n\nMaxime","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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