[{"id":1759573,"web_url":"http://patchwork.ozlabs.org/comment/1759573/","msgid":"<3c7d6fae-25c9-7fc5-9613-281539814509@linaro.org>","list_archive_url":null,"date":"2017-08-29T17:40:39","subject":"Re: [Qemu-devel] [PATCH] tcg/softmmu: Increase size of TLB caches","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"content":"On 08/29/2017 10:23 AM, Pranith Kumar wrote:\n> This patch increases the number of entries cached in the TLB. I went\n> over a few architectures to see if increasing it is problematic. Only\n> armv6 seems to have a limitation that only 8 bits can be used for\n> indexing these entries. For other architectures, the number of TLB\n> entries is increased to a 4K-sized cache. The patch also doubles the\n> number of victim TLB entries.\n> \n> Some statistics collected from a build benchmark for various cache\n> sizes is listed below:\n> \n> | TLB bits\\vTLB entires | 8 | 16 | 32 |\n> | 8 | 952.94(+0.0%) | 929.99(+2.4%) | 919.02(+3.6%) |\n> | 10 | 898.92(+5.6%) | 886.13(+7.0%) | 887.03(+6.9%) |\n> | 12 | 878.56(+7.8%) | 873.53(+8.3%)* | 875.34(+8.1%) |\n> \n> The best combination for this workload came out to be 12 bits for the\n> TLB and a 16 entry vTLB cache.\n> \n> Signed-off-by: Pranith Kumar \n> ---\n> include/exec/cpu-defs.h | 6 +++---\n> tcg/aarch64/tcg-target.h | 1 +\n> tcg/arm/tcg-target.h | 1 +\n> tcg/i386/tcg-target.h | 2 ++\n> tcg/ia64/tcg-target.h | 1 +\n> tcg/mips/tcg-target.h | 2 ++\n> tcg/ppc/tcg-target.h | 1 +\n> tcg/s390/tcg-target.h | 1 +\n> tcg/sparc/tcg-target.h | 1 +\n> tcg/tci/tcg-target.h | 1 +\n> 10 files changed, 14 insertions(+), 3 deletions(-)\n\nReviewed-by: Richard Henderson \n\n\nr~","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"<20170829172326.1131-1-bobby.prani@gmail.com>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400e:c05::22a","Subject":"Re: [Qemu-devel] [PATCH] tcg/softmmu: Increase size of TLB caches","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"qemu-devel@nongnu.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1763686,"web_url":"http://patchwork.ozlabs.org/comment/1763686/","msgid":"","list_archive_url":null,"date":"2017-09-05T21:50:35","subject":"Re: [Qemu-devel] [PATCH] tcg/softmmu: Increase size of TLB caches","submitter":{"id":2222,"url":"http://patchwork.ozlabs.org/api/people/2222/","name":"Richard Henderson","email":"rth@twiddle.net"},"content":"On 08/29/2017 10:23 AM, Pranith Kumar wrote:\n> This patch increases the number of entries cached in the TLB. I went\n> over a few architectures to see if increasing it is problematic. Only\n> armv6 seems to have a limitation that only 8 bits can be used for\n> indexing these entries. For other architectures, the number of TLB\n> entries is increased to a 4K-sized cache. The patch also doubles the\n> number of victim TLB entries.\n> \n> Some statistics collected from a build benchmark for various cache\n> sizes is listed below:\n> \n> | TLB bits\\vTLB entires | 8 | 16 | 32 |\n> | 8 | 952.94(+0.0%) | 929.99(+2.4%) | 919.02(+3.6%) |\n> | 10 | 898.92(+5.6%) | 886.13(+7.0%) | 887.03(+6.9%) |\n> | 12 | 878.56(+7.8%) | 873.53(+8.3%)* | 875.34(+8.1%) |\n> \n> The best combination for this workload came out to be 12 bits for the\n> TLB and a 16 entry vTLB cache.\n\nThis significantly degrades performance of alpha-softmmu.\nIt spends about 25% of all cpu time in memset.\n\n\nr~","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"lsy/lllg\"; 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Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<20170829172326.1131-1-bobby.prani@gmail.com>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400e:c05::229","Subject":"Re: [Qemu-devel] [PATCH] tcg/softmmu: Increase size of TLB caches","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"qemu-devel@nongnu.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1763738,"web_url":"http://patchwork.ozlabs.org/comment/1763738/","msgid":"","list_archive_url":null,"date":"2017-09-06T00:33:35","subject":"Re: [Qemu-devel] [PATCH] tcg/softmmu: Increase size of TLB caches","submitter":{"id":64653,"url":"http://patchwork.ozlabs.org/api/people/64653/","name":"Pranith Kumar","email":"bobby.prani@gmail.com"},"content":"On Tue, Sep 5, 2017 at 5:50 PM, Richard Henderson wrote:\n> On 08/29/2017 10:23 AM, Pranith Kumar wrote:\n>> This patch increases the number of entries cached in the TLB. I went\n>> over a few architectures to see if increasing it is problematic. Only\n>> armv6 seems to have a limitation that only 8 bits can be used for\n>> indexing these entries. For other architectures, the number of TLB\n>> entries is increased to a 4K-sized cache. The patch also doubles the\n>> number of victim TLB entries.\n>>\n>> Some statistics collected from a build benchmark for various cache\n>> sizes is listed below:\n>>\n>> | TLB bits\\vTLB entires | 8 | 16 | 32 |\n>> | 8 | 952.94(+0.0%) | 929.99(+2.4%) | 919.02(+3.6%) |\n>> | 10 | 898.92(+5.6%) | 886.13(+7.0%) | 887.03(+6.9%) |\n>> | 12 | 878.56(+7.8%) | 873.53(+8.3%)* | 875.34(+8.1%) |\n>>\n>> The best combination for this workload came out to be 12 bits for the\n>> TLB and a 16 entry vTLB cache.\n>\n> This significantly degrades performance of alpha-softmmu.\n> It spends about 25% of all cpu time in memset.\n\nWhat workload does it degrade for? I will try to reproduce and see\nwhich memset is causing this.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"lkSXpeOm\"; dkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xn4NQ6qDCz9sNd\n\tfor ;\n\tWed, 6 Sep 2017 10:34:44 +1000 (AEST)","from localhost ([::1]:33642 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dpOIg-0003TF-AC\n\tfor incoming@patchwork.ozlabs.org; Tue, 05 Sep 2017 20:34:38 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:53292)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1dpOID-0003Sm-5t\n\tfor qemu-devel@nongnu.org; Tue, 05 Sep 2017 20:34:13 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1dpOIC-0000s6-7O\n\tfor qemu-devel@nongnu.org; Tue, 05 Sep 2017 20:34:09 -0400","from mail-it0-x241.google.com ([2607:f8b0:4001:c0b::241]:34971)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from )\n\tid 1dpOIC-0000rd-1g\n\tfor qemu-devel@nongnu.org; Tue, 05 Sep 2017 20:34:08 -0400","by mail-it0-x241.google.com with SMTP id b76so874107itb.2\n\tfor ; Tue, 05 Sep 2017 17:34:06 -0700 (PDT)","by 10.79.166.2 with HTTP; Tue, 5 Sep 2017 17:33:35 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=mime-version:in-reply-to:references:from:date:message-id:subject:to\n\t:cc; bh=lTpyjH+v59AEq1SxW1/hDb8JydQYXVpNsQiFXtKeRYY=;\n\tb=lkSXpeOm4xhuUxQ+QOtUKVCRtXoMz09pAEZB9Mo0cY/g/fSrFIl/XeJxj3UT+jrYeC\n\t16Ns0sOoGvaalZm5SmbDeohDGuXbvLQxoUBRLHnFY34bhwm8ftJWJy5hDiOEy2OcSU1u\n\t9LlKQRQ9clkh6K28wmg6+x+BHNJM23WcbBTy89w7hEgXjzMNbWjIfSjZtQCjNgN5CPDp\n\tkvdXj3WKFEyhW8boMlkzb2xsyaXJlVFaL0j/hGoYa60VttaZT940ByRlon2k2weH50J6\n\tDnY75OpgiNHnepksKIFQdDVoLNZ3zwb3lEbLEFS1ZGudEYT1ab1XStBW67kXIXE2i7xL\n\tvjSA==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:mime-version:in-reply-to:references:from:date\n\t:message-id:subject:to:cc;\n\tbh=lTpyjH+v59AEq1SxW1/hDb8JydQYXVpNsQiFXtKeRYY=;\n\tb=e6C6FEJ4pohLZqyh/LxtTBfJlb4oWsdRLYuMInpOGI53hN95E1jAzVLmI2oe4zMbx/\n\txjYf1CFSDNwxvtfjjEzhSkVjKXmMDu7yN8D9+9QkVEUpVEgUZp8KegfxraVdHVLx1F3d\n\tlizCNSoGizqage1dePsd7CFLvb1tMWwVZSACaa9bV/z9vVYG4HWkIipFUt8bZ6+doSlo\n\td7vz3dE2NRM+8KwQk9Y+K7USwJvMu4nZrAtBtG5JVeIiGZmrvA8DM/91CyPiyXPWKTwM\n\tYacGBY6NLa+qTolfvRAeKxHRaHcgfensBaYMHsuWNQJCsdSJYvxXML2caUJ4IlkjrqEg\n\tkyvQ==","X-Gm-Message-State":"AHPjjUgcxMQ1AUI+IMh43tmDDeRGxJzKyy3Zulw6ge1ZMe361rzoA420\n\tLrdXzTr4GqbUmWoFk4/O29D1f4Blhg==","X-Google-Smtp-Source":"ADKCNb4Kq8MdYIPnb9JAjUSGx4DggZgyiFsRuFWno6MhhqUiF4G5qbWfGLELMAmkJdBvHS8eDiAZnnVwMZIw+2zno3o=","X-Received":"by 10.36.74.66 with SMTP id k63mr1158432itb.133.1504658046025;\n\tTue, 05 Sep 2017 17:34:06 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"","References":"<20170829172326.1131-1-bobby.prani@gmail.com>\n\t","From":"Pranith Kumar ","Date":"Tue, 5 Sep 2017 20:33:35 -0400","Message-ID":"","To":"Richard Henderson ","Content-Type":"text/plain; charset=\"UTF-8\"","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:4001:c0b::241","Subject":"Re: [Qemu-devel] [PATCH] tcg/softmmu: Increase size of TLB caches","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"=?utf-8?q?Alex_Benn=C3=A9e?= ,\n\tqemu-devel ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1763913,"web_url":"http://patchwork.ozlabs.org/comment/1763913/","msgid":"<8ea5a586-4d19-82db-f4b7-058229dc4124@twiddle.net>","list_archive_url":null,"date":"2017-09-06T08:26:54","subject":"Re: [Qemu-devel] [PATCH] tcg/softmmu: Increase size of TLB caches","submitter":{"id":2222,"url":"http://patchwork.ozlabs.org/api/people/2222/","name":"Richard Henderson","email":"rth@twiddle.net"},"content":"On 09/05/2017 05:33 PM, Pranith Kumar wrote:\n>> This significantly degrades performance of alpha-softmmu.\n>> It spends about 25% of all cpu time in memset.\n> \n> What workload does it degrade for? I will try to reproduce and see\n> which memset is causing this.\n\nemerge --update --ask @world\n\nwhich is a lot of python, iirc.\n\nIt is the tlb flush memset that is causing this.\nThe tlb has grown from a few kB to 300kB with your patch.\n\n\nr~","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"l1E1Ztgn\"; dkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xnGvn01MCz9s81\n\tfor ;\n\tWed, 6 Sep 2017 18:29:09 +1000 (AEST)","from localhost ([::1]:34943 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dpVhr-00087a-4V\n\tfor incoming@patchwork.ozlabs.org; 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Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:4001:c0b::22c","Subject":"Re: [Qemu-devel] [PATCH] tcg/softmmu: Increase size of TLB caches","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"=?utf-8?q?Alex_Benn=C3=A9e?= ,\n\tqemu-devel ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1763928,"web_url":"http://patchwork.ozlabs.org/comment/1763928/","msgid":"<87ingwmcjw.fsf@linaro.org>","list_archive_url":null,"date":"2017-09-06T08:55:15","subject":"Re: [Qemu-devel] [PATCH] tcg/softmmu: Increase size of TLB caches","submitter":{"id":39532,"url":"http://patchwork.ozlabs.org/api/people/39532/","name":"Alex Bennée","email":"alex.bennee@linaro.org"},"content":"Richard Henderson writes:\n\n> On 09/05/2017 05:33 PM, Pranith Kumar wrote:\n>>> This significantly degrades performance of alpha-softmmu.\n>>> It spends about 25% of all cpu time in memset.\n>>\n>> What workload does it degrade for? I will try to reproduce and see\n>> which memset is causing this.\n>\n> emerge --update --ask @world\n>\n> which is a lot of python, iirc.\n>\n> It is the tlb flush memset that is causing this.\n> The tlb has grown from a few kB to 300kB with your patch.\n\nHmm I wonder if this is QEMU doing global flushes which could actually\nbe partial TLB flushes? emerge is quite a memory hog though so its\nconceivable we are generating a lot of churn as it runs.\n\n--\nAlex Bennée","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"Gom3drgw\"; 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emacs 25.2.50.3","From":"Alex =?utf-8?q?Benn=C3=A9e?= ","To":"Richard Henderson ","In-reply-to":"<8ea5a586-4d19-82db-f4b7-058229dc4124@twiddle.net>","Date":"Wed, 06 Sep 2017 09:55:15 +0100","Message-ID":"<87ingwmcjw.fsf@linaro.org>","MIME-Version":"1.0","Content-Type":"text/plain; charset=utf-8","Content-Transfer-Encoding":"8bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2a00:1450:400c:c09::22f","Subject":"Re: [Qemu-devel] [PATCH] tcg/softmmu: Increase size of TLB caches","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Pranith Kumar , qemu-devel ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}}]