[{"id":1760056,"web_url":"http://patchwork.ozlabs.org/comment/1760056/","msgid":"<20170830105955.GB4926@amd>","list_archive_url":null,"date":"2017-08-30T10:59:56","subject":"Re: [patch v4 1/2] mfd: Add Mellanox regmap core driver","submitter":{"id":2109,"url":"http://patchwork.ozlabs.org/api/people/2109/","name":"Pavel Machek","email":"pavel@ucw.cz"},"content":"Hi!\n\n> Cause of reset nodes:\n> - cpu_kernel_panic\n> - cpu_shutdown\n> - bmc_warm_reset\n\nThis is not really suitable for hwmon, right?\n\nCan you talk to\n\nDate: Mon, 28 Aug 2017 09:31:30 -0700\nFrom: Andrey Smirnov \nTo: linux-kernel@vger.kernel.org\nCc: Andrey Smirnov , cphealy@gmail.com,\nSubject: [PATCH v6 1/2] platform: Add driver for RAVE Supervisory Processor\n\n? He's currently trying to add very similar interface to the kernel,\ntoo.\n\n+What: /sys/devices/platform/*/serial*/serial*-*/reset_reason\n+Date: Aug 2017\n+Contact: \"Andrey Smirnov\" \n+Description: (RO) Indicates reason for last reset.\n+\n+ The following values can be reported:\n+ * 0 -> Normal Power Off\n+ * 1 -> Hardware Watchdog\n+ * 2 -> Software Watchdog\n+ * 3 -> Input Voltage Out Of Range\n+ * 4 -> Host Requested\n+ * 5 -> Temperature Out Of Range\n+ * 6 -> User Requested (via long Power Button\npress)\n+ * 7 -> Illegal Configuration Word\n+ * 8 -> Illegal Insturction\n+ * 9 -> Illegal Trap\n+ * 10 -> Unknown\n+ * 11 -> Crew Panel Requested\n+\n+ NOTE: Codes 7,8 and 9 pertain to exceptions happening\n+ in supervisory processor/its firmware and not host\n+ CPU.\n\nWe really want something common between different machines.\n\nThanks,\n\t\t\t\t\t\t\t\t\tPavel","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xj2b41kfHz9sMN\n\tfor ;\n\tWed, 30 Aug 2017 21:00:00 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751263AbdH3K76 (ORCPT\n\t);\n\tWed, 30 Aug 2017 06:59:58 -0400","from atrey.karlin.mff.cuni.cz ([195.113.26.193]:53800 \"EHLO\n\tatrey.karlin.mff.cuni.cz\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751302AbdH3K76 (ORCPT\n\t); Wed, 30 Aug 2017 06:59:58 -0400","by atrey.karlin.mff.cuni.cz (Postfix, from userid 512)\n\tid 8398F825AF; Wed, 30 Aug 2017 12:59:56 +0200 (CEST)"],"Date":"Wed, 30 Aug 2017 12:59:56 +0200","From":"Pavel Machek ","To":"Vadim Pasternak ","Cc":"lee.jones@linaro.org, robh+dt@kernel.org,\n\tdevicetree@vger.kernel.org, j.anaszewski@samsung.com,\n\trpurdie@rpsys.net, linux-leds@vger.kernel.org, jiri@resnulli.us,\n\tgregkh@linuxfoundation.org, platform-driver-x86@vger.kernel.org","Subject":"Re: [patch v4 1/2] mfd: Add Mellanox regmap core driver","Message-ID":"<20170830105955.GB4926@amd>","References":"<1504029616-192277-1-git-send-email-vadimp@mellanox.com>\n\t<1504029616-192277-2-git-send-email-vadimp@mellanox.com>","MIME-Version":"1.0","Content-Type":"multipart/signed; micalg=pgp-sha1;\n\tprotocol=\"application/pgp-signature\"; boundary=\"VrqPEDrXMn8OVzN4\"","Content-Disposition":"inline","In-Reply-To":"<1504029616-192277-2-git-send-email-vadimp@mellanox.com>","User-Agent":"Mutt/1.5.23 (2014-03-12)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1761789,"web_url":"http://patchwork.ozlabs.org/comment/1761789/","msgid":"<20170901161433.gpkrpjx53pjv4mid@rob-hp-laptop>","list_archive_url":null,"date":"2017-09-01T16:14:33","subject":"Re: [patch v4 1/2] mfd: Add Mellanox regmap core driver","submitter":{"id":62529,"url":"http://patchwork.ozlabs.org/api/people/62529/","name":"Rob Herring (Arm)","email":"robh@kernel.org"},"content":"On Tue, Aug 29, 2017 at 06:00:15PM +0000, Vadim Pasternak wrote:\n> This patch adds core regmap platform driver for Mellanox BMC cards with\n> the programmable devices based chassis control. The device logics,\n> controlled by software includes:\n> - Interrupt handling for chassis, ASIC, CPU events;\n> - LED handling;\n> - Exposes through sysfs mux, reset signals, reset cause notification;\n> The patch provides support for the access to programmable device through\n> the register map and allows dynamic device tree manipulation at runtime\n> for removable devices.\n> \n> This driver requires activator driver, which responsibility is to create\n> register map and pass it to regmap core. Such activator could be based for\n> example on I2C, SPI or MMIO interface.\n> \n> Drivers exposes the number of hwmon attributes to sysfs according to the\n> attribute groups, defined in the device tree. These attributes will be\n> located for example in /sys/class/hwmon/hwmonX folder, which is a symbolic\n> link to for example:\n> /sys/bus/i2c/devices/4-0072/mlxreg-core.1138/hwmon/hwmon10.\n> The attributes are divided to the groups, like in the below example:\n> MUX nodes\n> - safe_bios_disable\n> - spi_burn_bios_ci\n> - spi_burn_ncsi\n> - uart_sel\n> Reset nodes:\n> - sys_power_cycle\n> - bmc_upgrade\n> - asic_reset\n> Cause of reset nodes:\n> - cpu_kernel_panic\n> - cpu_shutdown\n> - bmc_warm_reset\n> General purpose RW nodes:\n> - version\n> \n> Drivers also probes LED and hotplug drivers, in case device tree\n> description contains LED and hotplug nodes.\n> \n> Signed-off-by: Vadim Pasternak \n> ---\n> v3->v4:\n> Comments pointed out by Lee:\n> - Split interrupt related logic into separate module and place this logic\n> within the existing Mellanox hotplug driver. Move for this reason this\n> driver from drivers/platform/x86 to drivers/platform/mellanox folder;\n> Comments pointed out by Rob:\n> - Make a separate patch /devicetree/bindings/vendor-prefixes.txt;\n> - Add .txt to Documentation/devicetree/bindings/mfd/mellanox,mlxreg-core\n> and send it within this series;\n\nWhy did you combine this? Bindings should be separate patches.\n\n> - Modify \"compatible\" property;\n> - Modify explanation for \"deferred\" property;\n> - Describe each subnode by its own section;\n> - Don't use underscore in attribute names;\n> Changes added by Vadim:\n> - Add mlxreg_hotplug_device and mlxreg_core_item structures to mlxreg.h\n> and modify mlxreg_core_led_platform_data structure;\n> v2->v3:\n> Changes added by Vadim:\n> - Change name of field led data in struct mlxreg_core_led_platform_data\n> in mlxreg.h;\n> - fix data position assignment in mlxreg_core_get;\n> - update name of field led data in mlxreg_core_set_led;\n> v1->v2:\n> Comments pointed out by Pavel:\n> - Remove extra new line in mellanox,mlxreg-core;\n> - Replace three NOT with one in mlxreg_core_attr_show;\n> - Make error message in mlxreg_core_work_helper shorter;\n> - Make attribute assignment more readable;\n> - Separate mellanox,mlxreg-core file for sending to DT maintainers.\n> Comments pointed out by Jacek:\n> - Since brightness_set_blocking is used instead of\n> brightness_set, three fields from mlxreg_core_led_data are removed.\n> ---\n> .../bindings/mfd/mellanox,mlxreg-core.txt | 367 +++++++++\n> MAINTAINERS | 7 +\n> drivers/mfd/Kconfig | 15 +\n> drivers/mfd/Makefile | 1 +\n> drivers/mfd/mlxreg-core.c | 839 +++++++++++++++++++++\n> include/linux/platform_data/mlxreg.h | 138 ++++\n> 6 files changed, 1367 insertions(+)\n> create mode 100644 Documentation/devicetree/bindings/mfd/mellanox,mlxreg-core.txt\n> create mode 100644 drivers/mfd/mlxreg-core.c\n> create mode 100644 include/linux/platform_data/mlxreg.h\n> \n> diff --git a/Documentation/devicetree/bindings/mfd/mellanox,mlxreg-core.txt b/Documentation/devicetree/bindings/mfd/mellanox,mlxreg-core.txt\n> new file mode 100644\n> index 0000000..f8c776a\n> --- /dev/null\n> +++ b/Documentation/devicetree/bindings/mfd/mellanox,mlxreg-core.txt\n> @@ -0,0 +1,367 @@\n> +Mellanox programmable device control.\n> +-------------------------------------\n> +This binding defines the device control interface over I2C bus for Mellanox BMC\n> +based switches.\n> +\n> +Required properties:\n> +- compatible = \"mellanox,mlxreg-i2c\" or\n> +\t\t\"mellanox,mlxreg-i2c-16\"\n> +\n> +- #address-cells : must be 1;\n> +- #size-cells : must be 0;\n> +- reg : I2C address;\n> +\n> +Optional properties:\n> +- interrupt-parent : phandle of parent interrupt controller;\n> +- interrupts : interrupt line;\n> +- deferred : I2C deferred bus phandle;\n> +\t I2C bus activation order enforce for the cases when hot-plug\n> +\t devices are attached to I2C bus, which is initialized after the\n> +\t I2C bus, where programmable device is attached;\n> +- cell : top aggregation register offset;\n> +- mask : top aggregation register mask;\n> +\n> +Optional nodes and their properties:\n> + - psu : power supply unit nodes:\n> +\tRequired properties:\n> +\t- aggr : effective bit in aggregation mask;\n> +\t- reg : register offset for all group members;\n> +\t- mask : register mask;\n> +\t- phandles - list of relevant device nodes;\n> + - fan : fan unit nodes:\n> +\tRequired properties:\n> +\t- aggr : effective bit in aggregation mask;\n> +\t- reg : register offset for all group members;\n> +\t- mask : register mask;\n> +\t- phandles - list of relevant device nodes;\n> + - pwr : power cable nodes:\n> +\tRequired properties:\n> +\t- aggr : effective bit in aggregation mask;\n> +\t- reg : register offset for all group members;\n> +\t- mask : register mask;\n> +\t- phandles : list of relevant device nodes;\n> + - host : host side nodes (CPU host side for BMC):\n> +\tRequired properties:\n> +\t- aggr : effective bit in aggregation mask;\n> +\t- reg : register offset for all group members;\n> +\t- mask : register mask;\n> +\t- phandles : list of relevant device nodes;\n> + - asic : asic nodes:\n> +\tRequired properties:\n> +\t- aggr : effective bit in aggregation mask;\n> +\t- regs : register offsets array per group member;\n> +\t- masks : register masks array per group member;\n> +\t- phandles : list of relevant device nodes;\n> + - reset : reset nodes:\n> +\tRequired properties:\n> +\t- #address-cells : must be 1;\n> +\t- #size-cells : must be 0;\n> +\t- reset control subnodes:\n> +\t\tRequired properties:\n> +\t\t- reg : register offset;\n> +\t\t- mask : attribute mask;\n> + - cause - reset cause nodes:\n> +\tRequired properties:\n> +\t- #address-cells : must be 1;\n> +\t- #size-cells : must be 0;\n> +\t- cause info subnodes:\n> +\t\tRequired properties:\n> +\t\t- reg : register offset;\n> +\t\t- mask : attribute mask;\n> + - mux - mux nodes:\n> +\tRequired properties:\n> +\t- #address-cells : must be 1;\n> +\t- #size-cells : must be 0;\n> +\t- mux control subnodes:\n> +\t\tRequired properties:\n> +\t\t- reg : register offset;\n> +\t\t- mask : attribute mask;\n> +\t\t- bit : effective bit;\n> +\tOptional property:\n> +\t\t- phandles : relevant device node;\n> + - gprw - general purpose register nodes:\n> +\tRequired properties:\n> +\t- #address-cells : must be 1;\n> +\t- #size-cells : must be 0;\n> +\t- general purpose read-write register subnodes:\n> +\t\tRequired properties:\n> +\t\t- reg : register offset;\n> +\t\t- mask : attribute mask;\n> + - gpro - general purpose register nodes:\n> +\tRequired properties:\n> +\t- #address-cells : must be 1;\n> +\t- #size-cells : must be 0;\n> +\t- general purpose read only register subnodes:\n> +\t\tRequired properties:\n> +\t\t- reg : register offset.\n> +\t\t- mask : attribute mask.\n> + - led - led nodes:\n> +\tRequired properties:\n> +\t- #address-cells : must be 1;\n> +\t- #size-cells : must be 0;\n> +\t- led control nodes:\n> +\t\tRequired properties:\n> +\t\t- label : symbolic name;\n> +\t\t- reg : register offset;\n> +\t\t- mask : attribute mask;\n> +\n> +Example:\n> +\tmlxcpld-mng-ctrl@71 {\n> +\t\t#address-cells = <1>;\n> +\t\t#size-cells = <0>;\n> +\t\tinterrupt-parent = <&gpio>;\n> +\t\tinterrupts = ;\n> +\t\tcompatible = \"mellanox,mlxcpld-ctrl-i2c\";\n> +\t\treg = <0x71>;\n> +\t\tdeferred = <&i2c6>;\n> +\t\tcell = <0x3a>;\n> +\t\tmask = <0x4c>;\n> +\n> +\t\tpsu {\n> +\t\t\taggr = <0x08>;\n> +\t\t\treg = <0x58>;\n> +\t\t\tmask = <0x03>;\n> +\t\t\tphandles = <&psu1_eeprom &psu2_eeprom>;\n> +\t\t};\n> +\n> +\t\tpwr {\n> +\t\t\taggr = <0x08>;\n> +\t\t\treg = <0x64>;\n> +\t\t\tmask = <0x03>;\n> +\t\t\tphandles = <&psu1_ctrl &psu2_ctrl>;\n> +\t\t};\n> +\n> +\t\tfan {\n> +\t\t\taggr = <0x40>;\n> +\t\t\treg = <0x88>;\n> +\t\t\tmask = <0x0f>;\n> +\t\t\tphandles = <&fan1_eeprom &fan2_eeprom &fan3_eeprom\n> +\t\t\t\t &fan4_eeprom>;\n> +\t\t};\n> +\n> +\t\tmux {\n> +\t\t\t#address-cells = <1>;\n> +\t\t\t#size-cells = <0>;\n> +\n> +\t\t\tuart_sel {\n> +\t\t\t\treg = <0x30>;\n> +\t\t\t\tmask = <0xef>;\n> +\t\t\t\tbit = <0x00>;\n> +\t\t\t};\n> +\t\t\tspi_burn_bios_ci {\n> +\t\t\t\treg = <0x32>;\n> +\t\t\t\tmask = <0xfe>;\n> +\t\t\t\tbit = <0x00>;\n> +\t\t\t\tphandles = <&spi2>;\n> +\t\t\t};\n> +\t\t\tspi_burn_ncsi {\n> +\t\t\t\treg = <0x32>;\n\nYou can't have duplicate reg values. This will also generate warnings. \nBuild your dtb with \"W=2\".\n\nAgain, this all looks too low level to me. You described the high level \ndifferences in terms of number of cards, fans, PSUs, etc., but I don't \nsee that here. This isn't reviewable for anyone not familiar with your \nsystems.\n\n> +\t\t\t\tmask = <0xfd>;\n> +\t\t\t\tbit = <0x00>;\n> +\t\t\t\tphandles = <&spi2>;\n\nNot a good name other than giving type information. Name it for what \nfunction is being provided (e.g. clocks, interrupts, gpios).\n\n> +\t\t\t};\n> +\t\t\tbmc_uart_en {\n> +\t\t\t\treg = <0x32>;\n> +\t\t\t\tmask = <0xdf>;\n> +\t\t\t\tbit = <0x00>;\n> +\t\t\t};\n> +\t\t\tsafe_bios1 {\n> +\t\t\t\treg = <0x35>;\n> +\t\t\t\tmask = <0xfb>;\n> +\t\t\t\tbit = <0x01>;\n> +\t\t\t};\n> +\t\t\tsafe_bios2 {\n> +\t\t\t\treg = <0x35>;\n> +\t\t\t\tmask = <0xf7>;\n> +\t\t\t\tbit = <0x01>;\n> +\t\t\t};\n> +\t\t\tsafe_bios_disable {\n> +\t\t\t\treg = <0x35>;\n> +\t\t\t\tmask = <0xdf>;\n> +\t\t\t\tbit = <0x01>;\n> +\t\t\t};\n> +\t\t};\n> +\n> +\t\tled {\n> +\t\t\t#address-cells = <1>;\n> +\t\t\t#size-cells = <0>;\n> +\t\t\tstatus-green {\n> +\t\t\t\treg = <0x20>;\n> +\t\t\t\tmask = <0xf0>;\n> +\t\t\t};\n> +\t\t\tstatus-red {\n> +\t\t\t\treg = <0x20>;\n> +\t\t\t\tmask = <0xf0>;\n> +\t\t\t};\n> +\t\t\tstatus-amber {\n> +\t\t\t\treg = <0x20>;\n> +\t\t\t\tmask = <0xf0>;\n> +\t\t\t};\n> +\t\t\tfan1-green {\n> +\t\t\t\treg = <0x21>;\n> +\t\t\t\tmask = <0xf0>;\n> +\t\t\t};\n> +\t\t\tfan1-red {\n> +\t\t\t\treg = <0x21>;\n> +\t\t\t\tmask = <0xf0>;\n> +\t\t\t};\n> +\t\t\tfan2-green {\n> +\t\t\t\treg = <0x21>;\n> +\t\t\t\tmask = <0x0f>;\n> +\t\t\t};\n> +\t\t\tfan2-red {\n> +\t\t\t\treg = <0x21>;\n> +\t\t\t\tmask = <0x0f>;\n> +\t\t\t};\n> +\t\t\tfan3-green {\n> +\t\t\t\treg = <0x22>;\n> +\t\t\t\tmask = <0xf0>;\n> +\t\t\t};\n> +\t\t\tfan3-red {\n> +\t\t\t\tlabel = \"fan3:red\";\n> +\t\t\t\treg = <0x22>;\n> +\t\t\t\tmask = <0xf0>;\n> +\t\t\t};\n> +\t\t\tfan4-green {\n> +\t\t\t\treg = <0x22>;\n> +\t\t\t\tmask = <0x0f>;\n> +\t\t\t};\n> +\t\t\tfan4-red {\n> +\t\t\t\treg = <0x22>;\n> +\t\t\t\tmask = <0x0f>;\n> +\t\t\t};\n> +\t\t};\n> +\n> +\t\treset {\n> +\t\t\t#address-cells = <1>;\n> +\t\t\t#size-cells = <0>;\n> +\t\t\tbmc_reset_soft {\n> +\t\t\t\treg = <0x17>;\n> +\t\t\t\tmask = <0xfd>;\n> +\t\t\t};\n> +\t\t\tsystem_reset_hard {\n> +\t\t\t\treg = <0x17>;\n> +\t\t\t\tmask = <0xfe>;\n> +\t\t\t};\n> +\t\t\tcpu_reset_soft {\n> +\t\t\t\treg = <0x17>;\n> +\t\t\t\tmask = <0xf7>;\n> +\t\t\t};\n> +\t\t\tps1_on {\n> +\t\t\t\treg = <0x30>;\n> +\t\t\t\tmask = <0xfe>;\n> +\t\t\t};\n> +\t\t\tps2_on {\n> +\t\t\t\tlabel = \"ps2_on\";\n> +\t\t\t\treg = <0x30>;\n> +\t\t\t\tmask = <0xfd>;\n> +\t\t\t};\n> +\t\t\tsys_power_cycle {\n> +\t\t\t\treg = <0x30>;\n> +\t\t\t\tmask = <0xfb>;\n> +\t\t\t};\n> +\t\t\tmng_pg_ovrd {\n> +\t\t\t\treg = <0x30>;\n> +\t\t\t\tmask = <0xf7>;\n> +\t\t\t};\n> +\t\t\tcpu_reset_hard {\n> +\t\t\t\treg = <0x30>;\n> +\t\t\t\tmask = <0xdf>;\n> +\t\t\t};\n> +\t\t};\n> +\n> +\t\tcause {\n> +\t\t\t#address-cells = <1>;\n> +\t\t\t#size-cells = <0>;\n> +\t\t\tac_power_cycle {\n> +\t\t\t\treg = <0x1d>;\n> +\t\t\t\tmask = <0xfe>;\n> +\t\t\t};\n> +\t\t\tdc_power_cycle {\n> +\t\t\t\treg = <0x1d>;\n> +\t\t\t\tmask = <0xfd>;\n> +\t\t\t};\n> +\t\t\tcpu_power_down {\n> +\t\t\t\treg = <0x1d>;\n> +\t\t\t\tmask = <0xfb>;\n> +\t\t\t};\n> +\t\t\tcpu_reboot {\n> +\t\t\t\treg = <0x1d>;\n> +\t\t\t\tmask = <0xf7>;\n> +\t\t\t};\n> +\t\t\tcpu_shutdown {\n> +\t\t\t\treg = <0x1d>;\n> +\t\t\t\tmask = <0xef>;\n> +\t\t\t};\n> +\t\t\tcpu_watchdog {\n> +\t\t\t\treg = <0x1d>;\n> +\t\t\t\tmask = <0xef>;\n> +\t\t\t};\n> +\t\t\tcpu_kernel_panic {\n> +\t\t\t\treg = <0x1d>;\n> +\t\t\t\tmask = <0xef>;\n> +\t\t\t};\n> +\t\t\tbmc_warm_reset {\n> +\t\t\t\treg = <0x71>;\n> +\t\t\t\tmask = <0xfe>;\n> +\t\t\t};\n> +\t\t\tbmc_upgrade {\n> +\t\t\t\treg = <0x2e>;\n> +\t\t\t\tmask = <0xf7>;\n> +\t\t\t};\n> +\t\t};\n> +\n> +\t\tgpro {\n> +\t\t\t#address-cells = <1>;\n> +\t\t\t#size-cells = <0>;\n> +\t\t\tversion {\n> +\t\t\t\treg = <0x00>;\n> +\t\t\t\tmask = <0xff>;\n> +\t\t\t\tbit = <0xff>;\n> +\t\t\t};\n> +\t\t};\n> +\t};\n> +\n> +\tmlxcpld-swb-ctrl@72 {\n> +\t\t#address-cells = <1>;\n> +\t\t#size-cells = <0>;\n> +\t\tinterrupt-parent = <&gpio>;\n> +\t\tinterrupts = ;\n> +\t\tcompatible = \"mellanox,mlxcpld-ctrl-i2c\";\n> +\t\treg = <0x72>;\n> +\t\tdeferred = <&i2c12>;\n> +\t\tcell = <0x40>;\n> +\t\tmask = <0x01>;\n> +\n> +\t\tasic {\n> +\t\t\taggr = <0x01>;\n> +\t\t\tregs = <0x50>;\n> +\t\t\tmasks = <0x03>;\n> +\t\t\tphandles = <&asic_thermal>;\n> +\t\t};\n> +\n> +\t\tgpro {\n> +\t\t\t#address-cells = <1>;\n> +\t\t\t#size-cells = <0>;\n> +\t\t\tversion {\n> +\t\t\t\treg = <0x01>;\n> +\t\t\t\tmask = <0xff>;\n> +\t\t\t\tbit = <0xff>;\n> +\t\t\t};\n> +\t\t};\n> +\n> +\t\treset {\n> +\t\t\t#address-cells = <1>;\n> +\t\t\t#size-cells = <0>;\n> +\n> +\t\t\tasic_reset {\n> +\t\t\t\treg = <0x19>;\n> +\t\t\t\tmask = <0xf7>;\n> +\t\t\t};\n> +\t\t\tphy_reset {\n> +\t\t\t\treg = <0x19>;\n> +\t\t\t\tmask = <0xef>;\n> +\t\t\t};\n> +\t\t};\n> +\n> +\t};\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xkPTC42Xtz9t1t\n\tfor ;\n\tSat, 2 Sep 2017 02:14:39 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751973AbdIAQOh (ORCPT\n\t);\n\tFri, 1 Sep 2017 12:14:37 -0400","from mail-oi0-f67.google.com ([209.85.218.67]:33094 \"EHLO\n\tmail-oi0-f67.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751968AbdIAQOg (ORCPT\n\t); Fri, 1 Sep 2017 12:14:36 -0400","by mail-oi0-f67.google.com with SMTP id t124so539757oih.0;\n\tFri, 01 Sep 2017 09:14:36 -0700 (PDT)","from localhost (216-188-254-6.dyn.grandenetworks.net.\n\t[216.188.254.6]) by smtp.gmail.com with ESMTPSA id\n\th125sm425095oic.54.2017.09.01.09.14.34\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tFri, 01 Sep 2017 09:14:34 -0700 (PDT)"],"X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:date:from:to:cc:subject:message-id:references\n\t:mime-version:content-disposition:in-reply-to:user-agent;\n\tbh=6iPXd1kIih5eCVXK0CKgUqDHRg4Nbg4XCiNJCfWtbZk=;\n\tb=ejVFYikeEX4gHSeGNZKwEDaTVGgDIM7gXOwxIxJqPnAZs7ScUz1vaRzbhfWeTbTbjq\n\tVchJZ1hWzuFDjASTn2jPaP9fNqhMUkiacy5XY/9jzMALG8FEtaaDs18ZnjX5mp/ToDHX\n\tlYhAoamJsyi1Nsn8mZYcjmQHScMTV0PpFQNV+Twj5GOKBWy8yH2UUSUQZ2MrKm/sHFI2\n\tx811QNM2WtDdOpl0Kpb4TTVlkkwopRNkE1YTECiM3/ulrR7sUdSD5semb1GUEyF14qV4\n\t1LJJOQt0oFzt+vc4x4HYjna3xo6kBAs4fmrWhB53UUGJHVwUypiNrTVqsRg1PbRfGItb\n\tBbGg==","X-Gm-Message-State":"AHPjjUj7uoR1X7RVNHHIfwQne+w+nXAPxMbee78GK+KlaSG6mJWb2mZH\n\tFsiD/qReqE73YHi4aN8=","X-Google-Smtp-Source":"ADKCNb7s5k+uwixGQbK70YA67xokjY2d9/FyePAcgKM/rUinPrldcy4LwKwZ+JT88OkS4bq2Wxr2Mw==","X-Received":"by 10.202.84.22 with SMTP id i22mr1215581oib.182.1504282475491; \n\tFri, 01 Sep 2017 09:14:35 -0700 (PDT)","Date":"Fri, 1 Sep 2017 11:14:33 -0500","From":"Rob Herring ","To":"Vadim Pasternak ","Cc":"lee.jones@linaro.org, pavel@ucw.cz, devicetree@vger.kernel.org,\n\tj.anaszewski@samsung.com, rpurdie@rpsys.net,\n\tlinux-leds@vger.kernel.org, jiri@resnulli.us,\n\tgregkh@linuxfoundation.org, platform-driver-x86@vger.kernel.org","Subject":"Re: [patch v4 1/2] mfd: Add Mellanox regmap core driver","Message-ID":"<20170901161433.gpkrpjx53pjv4mid@rob-hp-laptop>","References":"<1504029616-192277-1-git-send-email-vadimp@mellanox.com>\n\t<1504029616-192277-2-git-send-email-vadimp@mellanox.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<1504029616-192277-2-git-send-email-vadimp@mellanox.com>","User-Agent":"NeoMutt/20170113 (1.7.2)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1763551,"web_url":"http://patchwork.ozlabs.org/comment/1763551/","msgid":"","list_archive_url":null,"date":"2017-09-05T18:21:27","subject":"RE: [patch v4 1/2] mfd: Add Mellanox regmap core driver","submitter":{"id":69757,"url":"http://patchwork.ozlabs.org/api/people/69757/","name":"Vadim Pasternak","email":"vadimp@mellanox.com"},"content":"> > folder; Comments pointed out by Rob:\n> > - Make a separate patch /devicetree/bindings/vendor-prefixes.txt;\n> > - Add .txt to Documentation/devicetree/bindings/mfd/mellanox,mlxreg-\n> core\n> > and send it within this series;\n> \n> Why did you combine this? Bindings should be separate patches.\n\nAck.\n\n> \n> > +\t\t\tspi_burn_bios_ci {\n> > +\t\t\t\treg = <0x32>;\n> > +\t\t\t\tmask = <0xfe>;\n> > +\t\t\t\tbit = <0x00>;\n> > +\t\t\t\tphandles = <&spi2>;\n> > +\t\t\t};\n> > +\t\t\tspi_burn_ncsi {\n> > +\t\t\t\treg = <0x32>;\n> \n> You can't have duplicate reg values. This will also generate warnings.\n> Build your dtb with \"W=2\".\n\nCan I use some logical name for unit, like below?\n\t\t\tspi_burn_bios_ci: mux@1 {\n\t\t\t\treg = <0x32>;\n\t\t\t\tmask = <0xfe>;\n\t\t\t\tbit = <0x00>;\n\t\t\t\thotplugs = <&spi2>;\n\t\t\t};\n\t\t\tspi_burn_ncsi: mux@2 {\n\t\t\t\treg = <0x32>;\n\t\t\t\tmask = <0xfd>;\n\t\t\t\tbit = <0x00>;\n\t\t\t\thotplugs = <&spi2>;\n\t\t\t};\n\nI verified it with \"W=2\". Also I am running with CONFIG_OF_UNITTEST and\nI don't have unites issues.\n\n> \n> Again, this all looks too low level to me. You described the high level\n> differences in terms of number of cards, fans, PSUs, etc., but I don't see that\n> here. This isn't reviewable for anyone not familiar with your systems.\n\nThe below should describe signals, which triggers hotplugable device\nInsertion or removal.\n\t\tpwr: hotplugs@1 {\n\t\t\taggr = <0x08>;\n\t\t\treg = <0x64>;\n\t\t\tmask = <0x03>;\n\t\t\thotplugs = <&psu1_ctrl &psu2_ctrl>;\n\t\t};\n\n\t\tasic: hotplugs@3 {\n\t\t\taggr = <0x01>;\n\t\t\tregs = <0x50>;\n\t\t\tmask = <0x03>;\n\t\t\thotplugs = <&asic_thermal>;\n\t\t};\nIn DTS I have description for such devices in disabled state and they are\nConnected or disconnected dynamically:\n&i2c3 {\n...\n\tpsu1_ctrl: dps460@59 {\n\t\tcompatible = \"dps460\";\n\t\treg = <0x59>;\n\t\tstatus = \"disabled\";\n\t};\n''\n\n&i2c12 {\n...\n\tasic_thermal: mlxsw_minimal@48 {\n\t\tcompatible = \"mlxsw_minimal\";\n\t\treg = <0x48>;\n\t\tstatus = \"disabled\";\n ...\n\nAnd the same way I'd like to add spine and leaf cards, but I still don't\nHave support for them in my drivers.\n\n> \n> > +\t\t\t\tmask = <0xfd>;\n> > +\t\t\t\tbit = <0x00>;\n> > +\t\t\t\tphandles = <&spi2>;\n> \n> Not a good name other than giving type information. Name it for what\n> function is being provided (e.g. clocks, interrupts, gpios).\n\nWould it be OK if to use hotplugs instead of phandles?\nIt could be f.e. FAN EEPROM, PSU controller, ASIC, spine or leaf card, all these \nare hotplugable device, which could be inserted or removed.\nIt could be remote flashes, which are getting available after mux selection, like\nin the above example for spi_burn_bios_ci and spi_burn_ncsi.\nOr it could be some other device at the remote side, which is getting available to\nBMC, only when remote side (f.e. COMEX) is getting power good.\n\nThanks,\nVadim.\n \n \n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=Mellanox.com header.i=@Mellanox.com\n\theader.b=\"itJASfIs\"; dkim-atps=neutral","spf=none (sender IP is )\n\tsmtp.mailfrom=vadimp@mellanox.com; "],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xmw5t111Bz9t16\n\tfor ;\n\tWed, 6 Sep 2017 04:21:36 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752017AbdIESVe (ORCPT\n\t);\n\tTue, 5 Sep 2017 14:21:34 -0400","from mail-ve1eur01on0053.outbound.protection.outlook.com\n\t([104.47.1.53]:36649\n\t\"EHLO EUR01-VE1-obe.outbound.protection.outlook.com\"\n\trhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP\n\tid S1751959AbdIESVc (ORCPT );\n\tTue, 5 Sep 2017 14:21:32 -0400","from AM4PR05MB3330.eurprd05.prod.outlook.com (10.171.187.15) by\n\tAM4PR05MB1506.eurprd05.prod.outlook.com (10.164.79.148) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id\n\t15.20.13.10; Tue, 5 Sep 2017 18:21:29 +0000","from AM4PR05MB3330.eurprd05.prod.outlook.com\n\t([fe80::d922:8e31:a547:ebb6]) by\n\tAM4PR05MB3330.eurprd05.prod.outlook.com\n\t([fe80::d922:8e31:a547:ebb6%13]) with mapi id 15.20.0013.018;\n\tTue, 5 Sep 2017 18:21:29 +0000"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=Mellanox.com;\n\ts=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version;\n\tbh=R27Fb18omledXc6lox37tI+lGtVL2cOp0MrwnCJ2d/Q=;\n\tb=itJASfIssmaxht/zgU3vsL2r5bFIqVZHVFon6GAw/R8qgrtZ8FylTEhNDioCLMrm1AcBERm1tsSMoSGXMG3US0GRqOOLTvW2JFxxmO0qxfmlPj4296aEFA4ikHu7BHOEB0DBtNuIvUZl8SNTt2XjD4kLJ5oCi0byQrjBiCR8Tmo=","From":"Vadim Pasternak ","To":"Rob Herring ","CC":"\"lee.jones@linaro.org\" ,\n\t\"pavel@ucw.cz\" ,\n\t\"devicetree@vger.kernel.org\" ,\n\t\"j.anaszewski@samsung.com\" ,\n\t\"rpurdie@rpsys.net\" ,\n\t\"linux-leds@vger.kernel.org\" ,\n\t\"jiri@resnulli.us\" ,\n\t\"gregkh@linuxfoundation.org\" ,\n\t\"platform-driver-x86@vger.kernel.org\" \n\t","Subject":"RE: [patch v4 1/2] mfd: Add Mellanox regmap core driver","Thread-Topic":"[patch v4 1/2] mfd: Add Mellanox regmap core driver","Thread-Index":"AQHTIOBWMXXKdXrgdUGqJySTrNMG/aKgOQqAgAZUtBA=","Date":"Tue, 5 Sep 2017 18:21:27 +0000","Message-ID":"","References":"<1504029616-192277-1-git-send-email-vadimp@mellanox.com>\n\t<1504029616-192277-2-git-send-email-vadimp@mellanox.com>\n\t<20170901161433.gpkrpjx53pjv4mid@rob-hp-laptop>","In-Reply-To":"<20170901161433.gpkrpjx53pjv4mid@rob-hp-laptop>","Accept-Language":"en-US","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","authentication-results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=Mellanox.com header.i=@Mellanox.com\n\theader.b=\"itJASfIs\"; dkim-atps=neutral","spf=none (sender IP is )\n\tsmtp.mailfrom=vadimp@mellanox.com; "],"x-originating-ip":"[193.47.165.251]","x-ms-publictraffictype":"Email","x-microsoft-exchange-diagnostics":"1; AM4PR05MB1506;\n\t6:YJm5mbNtUYF8ozJEcr/1Lsr+Dku+WutEcq1teBruE/cVJBBNkvYHPMfDwRw+eqt6IF7Pzhc5VONAaH7vcskFjUqoxZ2ZD2nyHnxKJxjW56OToGA3wTTxS1WC2WIvNqRJThOvdGpfctG3hOWgtzSzEo3Pc+D1g9YM1Xk9uA+qVvsvMU0QXYEOupXOobSU/lMLGuXsjGUwG/sFUr/y7DNkew1V4WB8le67tkNDV1GmYLJX7Bo6AFaxwM7roRovvZZS4wuahB9qwfIV62SwAoogPxau1wJA3a7XpybGYFxQzkpwuJ5d1/pbaTsn9QMpD+1GwKEx74WFcWgurzMrN0pigg==;\n\t5:ZY7rGl6aMgU8IsTb7g4qjmA1JWPbL2zPFf550eGScQcV5228K3p0GhNmzlyXeLsVqytyyBYv5xHSYiscOoS17pTowZRxRZPz3p2UnqZpbZF1uuGllYmZFLhRAvlfRI+iB6xz57g8+TjCUu7ckBIU9g==;\n\t24:JF8US7rGsrDQHiX2HpLXmuUBV8UN1yATnEZ8/OK3/L2ia+eMbeL31JPIlArFzlGNYC2n+mBXg8j/742rxTIEto/PghRxntrqm+UkS6hx5hs=;\n\t7:WGWGuLSvLrQSvrsUcWTmTcQMwpEFxfJmJ0nnfd2HrApZW21UhbNS9fzoz9Kji0mGF0TzcI59CJmMEU4WEw+8O677boOKkMk5HPu8wVmHHBVc/GY+Ueq2u2kXOrxbZqrlHzNPX3jriWEuiA67lrrYgIrkaajQEfHxq01NivYhARg2vbSr/cX7GY2/j/IB9fdf2KCOUCww2pAw/O0SI3qoqBz6Oqnsnx/3OCsYcuqIQeU=","x-ms-exchange-antispam-srfa-diagnostics":"SSOS;","x-ms-office365-filtering-correlation-id":"b6257546-d7ed-4ec2-4120-08d4f48aed71","x-ms-office365-filtering-ht":"Tenant","x-microsoft-antispam":"UriScan:; BCL:0; PCL:0;\n\tRULEID:(300000500095)(300135000095)(300000501095)(300135300095)(22001)(300000502095)(300135100095)(2017030254152)(48565401081)(300000503095)(300135400095)(2017052603199)(201703131423075)(201703031133081)(201702281549075)(300000504095)(300135200095)(300000505095)(300135600095)(300000506095)(300135500095);\n\tSRVR:AM4PR05MB1506; ","x-ms-traffictypediagnostic":"AM4PR05MB1506:","x-exchange-antispam-report-test":"UriScan:;","x-microsoft-antispam-prvs":"","x-exchange-antispam-report-cfa-test":"BCL:0; PCL:0;\n\tRULEID:(100000700101)(100105000095)(100000701101)(100105300095)(100000702101)(100105100095)(6040450)(2401047)(8121501046)(5005006)(3002001)(100000703101)(100105400095)(10201501046)(93006095)(93001095)(6055026)(6041248)(20161123555025)(20161123558100)(201703131423075)(201702281528075)(201703061421075)(201703061406153)(20161123564025)(20161123560025)(20161123562025)(6072148)(201708071742011)(100000704101)(100105200095)(100000705101)(100105500095);\n\tSRVR:AM4PR05MB1506; BCL:0; PCL:0;\n\tRULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(100000804101)(100110200095)(100000805101)(100110500095);\n\tSRVR:AM4PR05MB1506; ","x-forefront-prvs":"0421BF7135","x-forefront-antispam-report":"SFV:NSPM;\n\tSFS:(10009020)(6009001)(39860400002)(189002)(199003)(66066001)(6436002)(76176999)(2950100002)(6916009)(229853002)(81156014)(81166006)(101416001)(54356999)(5250100002)(8936002)(189998001)(6506006)(8676002)(3280700002)(106356001)(105586002)(50986999)(3660700001)(2906002)(4326008)(25786009)(5660300001)(7696004)(110136004)(9686003)(74316002)(97736004)(14454004)(305945005)(54906002)(7416002)(7736002)(86362001)(33656002)(478600001)(102836003)(68736007)(99286003)(55016002)(2900100001)(53936002)(6246003)(6116002)(3846002);\n\tDIR:OUT; SFP:1101; SCL:1; SRVR:AM4PR05MB1506;\n\tH:AM4PR05MB3330.eurprd05.prod.outlook.com; FPR:; SPF:None;\n\tPTR:InfoNoRecords; MX:1; A:1; LANG:en; ","received-spf":"None (protection.outlook.com: mellanox.com does not designate\n\tpermitted sender hosts)","spamdiagnosticoutput":"1:99","spamdiagnosticmetadata":"NSPM","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"quoted-printable","MIME-Version":"1.0","X-OriginatorOrg":"Mellanox.com","X-MS-Exchange-CrossTenant-originalarrivaltime":"05 Sep 2017 18:21:28.0494\n\t(UTC)","X-MS-Exchange-CrossTenant-fromentityheader":"Hosted","X-MS-Exchange-CrossTenant-id":"a652971c-7d2e-4d9b-a6a4-d149256f461b","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"AM4PR05MB1506","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}}]