[{"id":1763293,"web_url":"http://patchwork.ozlabs.org/comment/1763293/","msgid":"","list_archive_url":null,"date":"2017-09-05T12:28:20","subject":"Re: [Qemu-devel] [PATCH] target/arm: Remove 5J architecture","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/people/5111/","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"content":"On 28 August 2017 at 23:19, Portia Stephens wrote:\n> This fixes the issue that any BXJ instruction will result in an illegal_op.\n> This is because the 5J archiecture is always unsupported.\n> 5J architecture doesn't have a feature set and ENABLE_ARCH_5J is hardcoded\n> to 0, causing any ARCH(5J) to result in an illegal_op. The only use of\n> ARCH(5J) is in the BXJ instruction disassembly.\n>\n> This patch replaces that ARCH(5J) with ARCH(6) and removes the 5J architecture,\n> this isn't technically correct since the v5J ISA does support the BXJ\n> instruction. This change means that running a BXJ instruction on any v5 will\n> cause an illegal_op but it is better than the current state where any\n> architecture running a BXJ would cause an illegal_op. The correct solution\n> would be to create a feature set for v5J but that doesn't seem worth it as the\n> v5J is so old.\n>\n> Signed-off-by: Portia Stephens \n> Reviewed-by: Alistair Francis \n> ---\n> target/arm/translate.c | 6 ++++--\n> 1 file changed, 4 insertions(+), 2 deletions(-)\n>\n> diff --git a/target/arm/translate.c b/target/arm/translate.c\n> index d1a5f56998..4a30c0d7e0 100644\n> --- a/target/arm/translate.c\n> +++ b/target/arm/translate.c\n> @@ -41,7 +41,6 @@\n> #define ENABLE_ARCH_5 arm_dc_feature(s, ARM_FEATURE_V5)\n> /* currently all emulated v5 cores are also v5TE, so don't bother */\n> #define ENABLE_ARCH_5TE arm_dc_feature(s, ARM_FEATURE_V5)\n> -#define ENABLE_ARCH_5J 0\n> #define ENABLE_ARCH_6 arm_dc_feature(s, ARM_FEATURE_V6)\n> #define ENABLE_ARCH_6K arm_dc_feature(s, ARM_FEATURE_V6K)\n> #define ENABLE_ARCH_6T2 arm_dc_feature(s, ARM_FEATURE_THUMB2)\n> @@ -8389,7 +8388,10 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)\n> break;\n> case 0x2:\n> if (op1 == 1) {\n> - ARCH(5J); /* bxj */\n> + /* This should actually be ARCH(5J) but there is currently no\n> + * 5J architecture in QEMU.\n> + */\n> + ARCH(6); /* bxj */\n> /* Trivial implementation equivalent to bx. */\n> tmp = load_reg(s, rm);\n> gen_bx(s, tmp);\n\nThanks for this patch. However we do have both v5-no-J\n(arm946, all the pxa2xx cores) and v5-with-J CPUs (arm926, arm1026),\nso I think it would be better to fix this bug by adding an\nextra ARM_FEATURE_JAZELLE, which would be set in\narm_cpu_realizefn() if ARM_FEATURE_V6 is set, and set in\nthe per-core realize functions for arm926 and arm1026.\nIt should be a fairly small patch overall I think.\n\nthanks\n-- PMM","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"QFB4UxCu\"; dkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xmmHV08l2z9sRV\n\tfor ;\n\tTue, 5 Sep 2017 22:29:26 +1000 (AEST)","from localhost ([::1]:58654 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dpCyq-0006BY-2B\n\tfor incoming@patchwork.ozlabs.org; Tue, 05 Sep 2017 08:29:24 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:48755)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1dpCyF-00066r-EV\n\tfor qemu-devel@nongnu.org; Tue, 05 Sep 2017 08:28:55 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1dpCyA-0005UL-Ly\n\tfor qemu-devel@nongnu.org; Tue, 05 Sep 2017 08:28:47 -0400","from mail-wr0-x236.google.com ([2a00:1450:400c:c0c::236]:38426)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from )\n\tid 1dpCyA-0005TF-Fp\n\tfor qemu-devel@nongnu.org; Tue, 05 Sep 2017 08:28:42 -0400","by mail-wr0-x236.google.com with SMTP id 108so8361449wra.5\n\tfor ; Tue, 05 Sep 2017 05:28:42 -0700 (PDT)","by 10.223.159.68 with HTTP; Tue, 5 Sep 2017 05:28:20 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=mime-version:in-reply-to:references:from:date:message-id:subject:to\n\t:cc; bh=iCFiqilpgd9SOaebqJic1eUs196VDxeLEg/+i8wqcVk=;\n\tb=QFB4UxCuh8cXwXdTEypiuzV9p7wQPKYy3ACTKUJO2OwWN86ovtycyZCL1KyVFKnDmL\n\tSYi4yopUGW6LFel1a+P0EpOL6YzxQwYTrae4UveHuY/HUJAtyGIR05gM8mr2gsutzW+S\n\t29R4KHzMKVxUFZa6YtFx1JwtSikyybY9AuMbM=","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:mime-version:in-reply-to:references:from:date\n\t:message-id:subject:to:cc;\n\tbh=iCFiqilpgd9SOaebqJic1eUs196VDxeLEg/+i8wqcVk=;\n\tb=Q7v5T5NQ72JQTZK2sKEO6k/c5Ljh9IetC79K8scrj7l4hhuBoTZXSTGGnEAZh6kEaX\n\t58FFoglnqAqOLBgVIuBw7lBWP8FMfEmLEREJVoG2AtBt7ZOYla41CnC7QiiuqIOTsb7Z\n\tr1QJSlPGOTqGQznYeBM+bgBSETQwPmoX4BaImPgmYwxG3vQjXovwXp+/tNR+89OOW4hP\n\te6YAvz7SbXCLHo2Ggh8SrDUv7AJYr6tqfKieCuz++bcYv7itzeYtLhoELQC/c5irESf4\n\t0MdDDO2caTbC6VKY5LznhxeEv+Zu0C1rqPnu7nrTBpOzB9UXWM1cH4YOd3VMqyNGt81n\n\tLr2A==","X-Gm-Message-State":"AHPjjUjsoo76NlCpwHEfPSuCkbhiX+GdPQo94Rx70Dnoct4XQaWj6r+g\n\tbPoQdQruEsWutTQsq/FPkHwh9CWvcu7Q","X-Google-Smtp-Source":"ADKCNb5ZCABSRgSvmwwk4OWPuJxBjTGljhsVefeGUUNboRgMQEO37yPUZREsb4b6i3nD6w9USCmtNuB/HuP2/DWO1CM=","X-Received":"by 10.223.145.41 with SMTP id j38mr2162183wrj.314.1504614521390; \n\tTue, 05 Sep 2017 05:28:41 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"<20170828221901.12827-1-portia.stephens@xilinx.com>","References":"<20170828221901.12827-1-portia.stephens@xilinx.com>","From":"Peter Maydell ","Date":"Tue, 5 Sep 2017 13:28:20 +0100","Message-ID":"","To":"Portia Stephens ","Content-Type":"text/plain; charset=\"UTF-8\"","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2a00:1450:400c:c0c::236","Subject":"Re: [Qemu-devel] [PATCH] target/arm: Remove 5J architecture","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"qemu-arm , QEMU Developers , \n\tstephensportia@gmail.com, Alistair Francis ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}}]