[{"id":1759147,"web_url":"http://patchwork.ozlabs.org/comment/1759147/","msgid":"<20170829090034.ytepjfv2jkkd2b3z@earth>","list_archive_url":null,"date":"2017-08-29T09:00:34","subject":"Re: [PATCH 14/17] ARM: dts: Add missing gpu node and binding for\n\tomap4","submitter":{"id":71508,"url":"http://patchwork.ozlabs.org/api/people/71508/","name":"Sebastian Reichel","email":"sebastian.reichel@collabora.co.uk"},"content":"Hi,\n\nOn Mon, Aug 28, 2017 at 02:19:15PM -0700, Tony Lindgren wrote:\n> On omap4 we're missing the PowerVR SGX GPU node with it's related\n> \"ti,hwmods\" property that the SoC interconnect code needs.\n> \n> Note that this will only show up as a bug with \"doesn't have\n> mpu register target base\" boot errors when the legacy platform\n> data is removed.\n> \n> Cc: Tomi Valkeinen \n> Signed-off-by: Tony Lindgren \n> ---\n\nI think OMAP3 & OMAP5 should also be documented and getting a\nnode in this series?\n\n-- Sebastian\n\n> .../devicetree/bindings/gpu/ti-powervr-sgx.txt | 34 ++++++++++++++++++++++\n> arch/arm/boot/dts/omap4.dtsi | 7 +++++\n> 2 files changed, 41 insertions(+)\n> create mode 100644 Documentation/devicetree/bindings/gpu/ti-powervr-sgx.txt\n> \n> diff --git a/Documentation/devicetree/bindings/gpu/ti-powervr-sgx.txt b/Documentation/devicetree/bindings/gpu/ti-powervr-sgx.txt\n> new file mode 100644\n> --- /dev/null\n> +++ b/Documentation/devicetree/bindings/gpu/ti-powervr-sgx.txt\n> @@ -0,0 +1,34 @@\n> +Texas Instruments PowevVR SGX binding\n> +\n> +SGX can be used for graphics acceleration on Texas Instruments SoCs.\n> +\n> +Note that the SGX binding is currently only used by the SoC interconnect\n> +code to idle the module on init and no open source driver is available\n> +for SGX. Please update this documentation if that changes.\n> +\n> +Required properties:\n> +\n> +compatible: Shall be one of the following:\n> +\t \"ti,omap4-gpu\"\n> +\n> +reg: Shall contain the device instance IO range\n> +\n> +interrupts: Shall contain the device instance interrupt\n> +\n> +\n> +Optional properties:\n> +\n> +reg-names: Shall contain the IO range names if multiple IO\n> +\t ranges are used by the SoC\n> +\n> +ti,hwmods: Shall contain the TI interconnect module name if needed\n> +\t by the SoC\n> +\n> +\n> +Example:\n> +\tgpu: gpu@56000000 {\n> +\t\tcompatible = \"ti,omap4-gpu\";\n> +\t\treg = <0x56000000 0x10000>;\n> +\t\tinterrupts = ;\n> +\t\tti,hwmods = \"gpu\";\n> +\t};\n> diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi\n> --- a/arch/arm/boot/dts/omap4.dtsi\n> +++ b/arch/arm/boot/dts/omap4.dtsi\n> @@ -1086,6 +1086,13 @@\n> \t\t\tstatus = \"disabled\";\n> \t\t};\n> \n> +\t\tgpu: gpu@56000000 {\n> +\t\t\tcompatible = \"ti,omap4-gpu\";\n> +\t\t\treg = <0x56000000 0x10000>;\n> +\t\t\tinterrupts = ;\n> +\t\t\tti,hwmods = \"gpu\";\n> +\t\t};\n> +\n> \t\tdss: dss@58000000 {\n> \t\t\tcompatible = \"ti,omap4-dss\";\n> \t\t\treg = <0x58000000 0x80>;\n> -- \n> 2.14.1\n> --\n> To unsubscribe from this list: send the line \"unsubscribe linux-omap\" in\n> the body of a message to majordomo@vger.kernel.org\n> More majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xhMzs0mmtz9sQl\n\tfor ;\n\tTue, 29 Aug 2017 19:00:41 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751409AbdH2JAj (ORCPT\n\t);\n\tTue, 29 Aug 2017 05:00:39 -0400","from bhuna.collabora.co.uk ([46.235.227.227]:55886 \"EHLO\n\tbhuna.collabora.co.uk\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1750909AbdH2JAi (ORCPT\n\t); Tue, 29 Aug 2017 05:00:38 -0400","from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender:\n\tsre) with ESMTPSA id D342C26C987"],"Date":"Tue, 29 Aug 2017 11:00:34 +0200","From":"Sebastian Reichel ","To":"Tony Lindgren ","Cc":"linux-omap@vger.kernel.org, =?iso-8859-1?q?Beno=EEt?=\n\tCousson , devicetree@vger.kernel.org,\n\tTomi Valkeinen ","Subject":"Re: [PATCH 14/17] ARM: dts: Add missing gpu node and binding for\n\tomap4","Message-ID":"<20170829090034.ytepjfv2jkkd2b3z@earth>","References":"<20170828211918.11573-1-tony@atomide.com>\n\t<20170828211918.11573-15-tony@atomide.com>","MIME-Version":"1.0","Content-Type":"multipart/signed; micalg=pgp-sha512;\n\tprotocol=\"application/pgp-signature\"; boundary=\"e5o7p4sjxzmzodys\"","Content-Disposition":"inline","In-Reply-To":"<20170828211918.11573-15-tony@atomide.com>","User-Agent":"NeoMutt/20170609 (1.8.3)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1759246,"web_url":"http://patchwork.ozlabs.org/comment/1759246/","msgid":"<201708291135.v7TBZCHH020827@dflxv15.itg.ti.com>","list_archive_url":null,"date":"2017-08-29T11:35:09","subject":"Re: [PATCH 14/17] ARM: dts: Add missing gpu node and binding for\n\tomap4","submitter":{"id":7026,"url":"http://patchwork.ozlabs.org/api/people/7026/","name":"Tomi Valkeinen","email":"tomi.valkeinen@ti.com"},"content":"This message contains a digitally signed email which can be read by opening the attachment.\nTexas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki\nOn 29/08/17 12:00, Sebastian Reichel wrote:\n> Hi,\n> \n> On Mon, Aug 28, 2017 at 02:19:15PM -0700, Tony Lindgren wrote:\n>> On omap4 we're missing the PowerVR SGX GPU node with it's related\n>> \"ti,hwmods\" property that the SoC interconnect code needs.\n>>\n>> Note that this will only show up as a bug with \"doesn't have\n>> mpu register target base\" boot errors when the legacy platform\n>> data is removed.\n>>\n>> Cc: Tomi Valkeinen \n>> Signed-off-by: Tony Lindgren \n>> ---\n> \n> I think OMAP3 & OMAP5 should also be documented and getting a\n> node in this series?\n\nDo we even want to add SGX to the .dts? We don't have proper drivers for\nSGX. If we ever do, who knows what kind of DT data they need. I know the\nDT data for SGX in TI's kernel tree has changed at least once.\n\n Tomi","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=ti.com header.i=@ti.com header.b=\"pyQJE9N3\"; \n\tdkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xhRQM22ksz9s3T\n\tfor ;\n\tTue, 29 Aug 2017 21:35:23 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752407AbdH2LfS (ORCPT\n\t);\n\tTue, 29 Aug 2017 07:35:18 -0400","from fllnx210.ext.ti.com ([198.47.19.17]:24556 \"EHLO\n\tfllnx210.ext.ti.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751840AbdH2LfR (ORCPT\n\t); Tue, 29 Aug 2017 07:35:17 -0400","from dflxv15.itg.ti.com ([128.247.5.124])\n\tby fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id v7TBZChL030443; \n\tTue, 29 Aug 2017 06:35:12 -0500","from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37])\n\tby dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7TBZCHH020827;\n\tTue, 29 Aug 2017 06:35:12 -0500","from DLEE110.ent.ti.com (157.170.170.21) by DLEE107.ent.ti.com\n\t(157.170.170.37) with Microsoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34;\n\tTue, 29 Aug 2017 06:35:11 -0500","from dflp33.itg.ti.com (10.64.6.16) by DLEE110.ent.ti.com\n\t(157.170.170.21) with Microsoft SMTP Server (version=TLS1_0,\n\tcipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend\n\tTransport; Tue, 29 Aug 2017 06:35:11 -0500","from [192.168.2.6] (ileax41-snat.itg.ti.com [10.172.224.153])\n\tby dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7TBZ9wb002802;\n\tTue, 29 Aug 2017 06:35:10 -0500"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com;\n\ts=ti-com-17Q1; t=1504006512;\n\tbh=aqEGKDZ5R5LtkRh7NP2k7bWXXXUQtF7zEqJ5nr9Su9E=;\n\th=Subject:To:CC:References:From:Date:In-Reply-To;\n\tb=pyQJE9N3oWfhFIkWl+PCyk8j5n+7+oLHTZZmNqugJ/B6B9EyRYDRksBS+N9oafuxL\n\t/DZ2+Wy7R3TI4RCGal2YKIE6curx5yLXzIE9YyNhr+xHlg70oae+ZgSENnMc3niws1\n\tvyBJqLJMLX8oZfLjG/Lh81D5QN6juSV4FvJZ7/aM=","Message-Id":"<201708291135.v7TBZCHH020827@dflxv15.itg.ti.com>","X-Sender":"tomi.valkeinen@ti.com","X-Receiver":["sebastian.reichel@collabora.co.uk","tony@atomide.com","linux-omap@vger.kernel.org","bcousson@baylibre.com","devicetree@vger.kernel.org"],"Subject":"Re: [PATCH 14/17] ARM: dts: Add missing gpu node and binding for\n\tomap4","To":"Sebastian Reichel ,\n\tTony Lindgren ","CC":", =?utf-8?q?Beno=C3=AEt_Cousson?=\n\t, ","References":"<20170828211918.11573-1-tony@atomide.com>\n\t<20170828211918.11573-15-tony@atomide.com>\n\t<20170829090034.ytepjfv2jkkd2b3z@earth>","From":"Tomi Valkeinen ","Date":"Tue, 29 Aug 2017 14:35:09 +0300","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"<20170829090034.ytepjfv2jkkd2b3z@earth>","Content-Type":"multipart/mixed;\n\tboundary=\"_ec08611b-5b20-425a-8d95-7f5ecfd35ddb_\"","X-EXCLAIMER-MD-CONFIG":"e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1759266,"web_url":"http://patchwork.ozlabs.org/comment/1759266/","msgid":"<20170829121041.dweciryplio5i4jr@earth>","list_archive_url":null,"date":"2017-08-29T12:10:41","subject":"Re: [PATCH 14/17] ARM: dts: Add missing gpu node and binding for\n\tomap4","submitter":{"id":71508,"url":"http://patchwork.ozlabs.org/api/people/71508/","name":"Sebastian Reichel","email":"sebastian.reichel@collabora.co.uk"},"content":"Hi,\n\nOn Tue, Aug 29, 2017 at 02:35:09PM +0300, Tomi Valkeinen wrote:\n> This message contains a digitally signed email which can be read by opening the attachment.\n> Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki\n\n> Date: Tue, 29 Aug 2017 14:35:09 +0300\n> From: Tomi Valkeinen \n> To: Sebastian Reichel , Tony Lindgren\n> \n> CC: linux-omap@vger.kernel.org, Benoît Cousson ,\n> devicetree@vger.kernel.org\n> Subject: Re: [PATCH 14/17] ARM: dts: Add missing gpu node and binding for\n> omap4\n> \n> On 29/08/17 12:00, Sebastian Reichel wrote:\n> > Hi,\n> > \n> > On Mon, Aug 28, 2017 at 02:19:15PM -0700, Tony Lindgren wrote:\n> >> On omap4 we're missing the PowerVR SGX GPU node with it's related\n> >> \"ti,hwmods\" property that the SoC interconnect code needs.\n> >>\n> >> Note that this will only show up as a bug with \"doesn't have\n> >> mpu register target base\" boot errors when the legacy platform\n> >> data is removed.\n> >>\n> >> Cc: Tomi Valkeinen \n> >> Signed-off-by: Tony Lindgren \n> >> ---\n> > \n> > I think OMAP3 & OMAP5 should also be documented and getting a\n> > node in this series?\n> \n> Do we even want to add SGX to the .dts? We don't have proper drivers for\n> SGX. If we ever do, who knows what kind of DT data they need. I know the\n> DT data for SGX in TI's kernel tree has changed at least once.\n\nI don't think reg or interrupts will be removed, so the properties\nadded by Tony look pretty safe?. I guess if we ever have a driver\nit would need some more properties and would bail out. Having no\nDT data is does not load at all, the result is the same. OTOH having\nthe node means the kernel can properly send the module to idle.\n\nI think this patchset should Cc Rob and Mark. \n\n-- Sebastian","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xhSCC5v3Hz9t1t\n\tfor ;\n\tTue, 29 Aug 2017 22:10:47 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1753279AbdH2MKq (ORCPT\n\t);\n\tTue, 29 Aug 2017 08:10:46 -0400","from bhuna.collabora.co.uk ([46.235.227.227]:56339 \"EHLO\n\tbhuna.collabora.co.uk\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1752863AbdH2MKp (ORCPT\n\t); Tue, 29 Aug 2017 08:10:45 -0400","from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender:\n\tsre) with ESMTPSA id 400C226C60B"],"Date":"Tue, 29 Aug 2017 14:10:41 +0200","From":"Sebastian Reichel ","To":"Tomi Valkeinen ","Cc":"Tony Lindgren , linux-omap@vger.kernel.org,\n\t=?iso-8859-1?q?Beno=EEt?= Cousson ,\n\tdevicetree@vger.kernel.org","Subject":"Re: [PATCH 14/17] ARM: dts: Add missing gpu node and binding for\n\tomap4","Message-ID":"<20170829121041.dweciryplio5i4jr@earth>","References":"<20170828211918.11573-1-tony@atomide.com>\n\t<20170828211918.11573-15-tony@atomide.com>\n\t<20170829090034.ytepjfv2jkkd2b3z@earth>\n\t<201708291135.v7TBZCHH020827@dflxv15.itg.ti.com>","MIME-Version":"1.0","Content-Type":"multipart/signed; micalg=pgp-sha512;\n\tprotocol=\"application/pgp-signature\"; boundary=\"nly25ubm6cbfj44w\"","Content-Disposition":"inline","In-Reply-To":"<201708291135.v7TBZCHH020827@dflxv15.itg.ti.com>","User-Agent":"NeoMutt/20170609 (1.8.3)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1759281,"web_url":"http://patchwork.ozlabs.org/comment/1759281/","msgid":"","list_archive_url":null,"date":"2017-08-29T12:24:52","subject":"Re: [PATCH 14/17] ARM: dts: Add missing gpu node and binding for\n\tomap4","submitter":{"id":7026,"url":"http://patchwork.ozlabs.org/api/people/7026/","name":"Tomi Valkeinen","email":"tomi.valkeinen@ti.com"},"content":"\nTexas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki\n\nOn 29/08/17 15:10, Sebastian Reichel wrote:\n\n>> Do we even want to add SGX to the .dts? We don't have proper drivers for\n>> SGX. If we ever do, who knows what kind of DT data they need. I know the\n>> DT data for SGX in TI's kernel tree has changed at least once.\n> \n> I don't think reg or interrupts will be removed, so the properties\n> added by Tony look pretty safe?. I guess if we ever have a driver\n\nMaybe. At the moment we have this in TI's tree for DRA7:\n\ngpu: gpu@56000000 {\n\tcompatible = \"ti,dra7-sgx544\", \"img,sgx544\";\n\treg = <0x56000000 0x10000>;\n\treg-names = \"gpu_ocp_base\";\n\tinterrupts = ;\n\tti,hwmods = \"gpu\";\n\tclocks = <&l3_iclk_div>, <&gpu_core_gclk_mux>,\n\t\t<&gpu_hyd_gclk_mux>;\n\tclock-names = \"iclk\", \"fclk1\", \"fclk2\";\n};\n\n> it would need some more properties and would bail out. Having no\n> DT data is does not load at all, the result is the same. OTOH having\n> the node means the kernel can properly send the module to idle.\n\nI just get uneasy when adding DT data that we're not really sure if it's\nok or not. I've been fighting with such data for ages. But, as you say,\nthis probably won't matter if the driver will just reject DT data that\ndoesn't have all the details.\n\nIf we need the DT node to idle SGX, and we don't even mean to actually\nuse an SGX driver with this data, it sounds fine to me.\n\n Tomi\n\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=ti.com header.i=@ti.com header.b=\"pfNX0+PJ\"; \n\tdkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xhSWd3kQjz9t1t\n\tfor ;\n\tTue, 29 Aug 2017 22:25:01 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1753403AbdH2MY7 (ORCPT\n\t);\n\tTue, 29 Aug 2017 08:24:59 -0400","from fllnx210.ext.ti.com ([198.47.19.17]:25856 \"EHLO\n\tfllnx210.ext.ti.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751600AbdH2MY7 (ORCPT\n\t); Tue, 29 Aug 2017 08:24:59 -0400","from dflxv15.itg.ti.com ([128.247.5.124])\n\tby fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id v7TCOs0O003835; \n\tTue, 29 Aug 2017 07:24:54 -0500","from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23])\n\tby dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7TCOswU018964;\n\tTue, 29 Aug 2017 07:24:54 -0500","from DLEE107.ent.ti.com (157.170.170.37) by DLEE112.ent.ti.com\n\t(157.170.170.23) with Microsoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34;\n\tTue, 29 Aug 2017 07:24:54 -0500","from dlep32.itg.ti.com (157.170.170.100) by DLEE107.ent.ti.com\n\t(157.170.170.37) with Microsoft SMTP Server (version=TLS1_0,\n\tcipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend\n\tTransport; Tue, 29 Aug 2017 07:24:54 -0500","from [192.168.2.6] (ileax41-snat.itg.ti.com [10.172.224.153])\n\tby dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7TCOrbQ031695;\n\tTue, 29 Aug 2017 07:24:53 -0500"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com;\n\ts=ti-com-17Q1; t=1504009494;\n\tbh=7LuasUOCkKFy3UYn2uZRMY4T7QukJufyH0wb8Cqkpvo=;\n\th=Subject:To:CC:References:From:Date:In-Reply-To;\n\tb=pfNX0+PJD6D58E+lg8CPoFSCja3Ot4Ds7whUbJDVlEKn66OZaG4JT+hvftVizM1hW\n\ttxeBsXSA9JWaeUsI50d3zpC70AXzpq4cdAnbOEaLZh3dAF/6SBK8EBJtYF2DtjGGyC\n\tOIDphnT6t5VgfvqLVtgIVLv2w0hxPogLl0mXHUfM=","Subject":"Re: [PATCH 14/17] ARM: dts: Add missing gpu node and binding for\n\tomap4","To":"Sebastian Reichel ","CC":"Tony Lindgren , ,\n\t=?utf-8?q?Beno=C3=AEt_Cousson?= ,\n\t","References":"<20170828211918.11573-1-tony@atomide.com>\n\t<20170828211918.11573-15-tony@atomide.com>\n\t<20170829090034.ytepjfv2jkkd2b3z@earth>\n\t<201708291135.v7TBZCHH020827@dflxv15.itg.ti.com>\n\t<20170829121041.dweciryplio5i4jr@earth>","From":"Tomi Valkeinen ","Message-ID":"","Date":"Tue, 29 Aug 2017 15:24:52 +0300","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"<20170829121041.dweciryplio5i4jr@earth>","Content-Type":"text/plain; charset=\"utf-8\"","Content-Language":"en-US","Content-Transfer-Encoding":"quoted-printable","X-EXCLAIMER-MD-CONFIG":"e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1759284,"web_url":"http://patchwork.ozlabs.org/comment/1759284/","msgid":"<5efc9078-5886-5826-834e-facd67ddfbe5@ti.com>","list_archive_url":null,"date":"2017-08-29T12:27:31","subject":"Re: [PATCH 14/17] ARM: dts: Add missing gpu node and binding for\n\tomap4","submitter":{"id":7026,"url":"http://patchwork.ozlabs.org/api/people/7026/","name":"Tomi Valkeinen","email":"tomi.valkeinen@ti.com"},"content":"\nTexas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki\n\nOn 29/08/17 15:10, Sebastian Reichel wrote:\n\n>> Do we even want to add SGX to the .dts? We don't have proper drivers for\n>> SGX. If we ever do, who knows what kind of DT data they need. I know the\n>> DT data for SGX in TI's kernel tree has changed at least once.\n> \n> I don't think reg or interrupts will be removed, so the properties\n> added by Tony look pretty safe?. I guess if we ever have a driver\n\nOh, and one more thing about the regs. I believe SGX consists of\nmultiple register blocks. But as it's not documented in any public docs,\nthere's just that single block in the DT data. I'm not sure if single\nblock or multiple blocks would be the right approach, but then, I guess\nwe can always live with just a single block and if needed split the\nblocks inside the driver.\n\n Tomi\n\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=ti.com header.i=@ti.com header.b=\"WlzXKJJR\"; \n\tdkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xhSbb5Hgrz9sNc\n\tfor ;\n\tTue, 29 Aug 2017 22:28:27 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751776AbdH2M20 (ORCPT\n\t);\n\tTue, 29 Aug 2017 08:28:26 -0400","from fllnx209.ext.ti.com ([198.47.19.16]:52230 \"EHLO\n\tfllnx209.ext.ti.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751356AbdH2M2Y (ORCPT\n\t); Tue, 29 Aug 2017 08:28:24 -0400","from dflxv15.itg.ti.com ([128.247.5.124])\n\tby fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id v7TCRdpY007568; \n\tTue, 29 Aug 2017 07:27:39 -0500","from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24])\n\tby dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7TCRY7J022534;\n\tTue, 29 Aug 2017 07:27:34 -0500","from DFLE100.ent.ti.com (10.64.6.21) by DFLE103.ent.ti.com\n\t(10.64.6.24) with Microsoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34;\n\tTue, 29 Aug 2017 07:27:34 -0500","from dlep33.itg.ti.com (157.170.170.75) by DFLE100.ent.ti.com\n\t(10.64.6.21) with Microsoft SMTP Server (version=TLS1_0,\n\tcipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend\n\tTransport; Tue, 29 Aug 2017 07:27:34 -0500","from [192.168.2.6] (ileax41-snat.itg.ti.com [10.172.224.153])\n\tby dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7TCRWxc009714;\n\tTue, 29 Aug 2017 07:27:32 -0500"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com;\n\ts=ti-com-17Q1; t=1504009659;\n\tbh=6UbI1IArKGg5SsWbkrjVD9T1MuhrmkaGuXkVfNB4rWw=;\n\th=Subject:To:CC:References:From:Date:In-Reply-To;\n\tb=WlzXKJJRGx49fnN5F34XGmSmRA7lfEDudDC7jqv6cgnmFdAFaM5ZOhSR9DG8T6J0t\n\tW0CxewWCzoznUik5hzfGhIbh0MNiz2ggCrgA1cZ4j2guNg+3PlSIHHSjRWQFwAdj9M\n\tIn4SG/wiulv/zW8r9IynCcyJ9qEs6bWtACiNbeAg=","Subject":"Re: [PATCH 14/17] ARM: dts: Add missing gpu node and binding for\n\tomap4","To":"Sebastian Reichel ","CC":"Tony Lindgren , ,\n\t=?utf-8?q?Beno=C3=AEt_Cousson?= ,\n\t","References":"<20170828211918.11573-1-tony@atomide.com>\n\t<20170828211918.11573-15-tony@atomide.com>\n\t<20170829090034.ytepjfv2jkkd2b3z@earth>\n\t<201708291135.v7TBZCHH020827@dflxv15.itg.ti.com>\n\t<20170829121041.dweciryplio5i4jr@earth>","From":"Tomi Valkeinen ","Message-ID":"<5efc9078-5886-5826-834e-facd67ddfbe5@ti.com>","Date":"Tue, 29 Aug 2017 15:27:31 +0300","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"<20170829121041.dweciryplio5i4jr@earth>","Content-Type":"text/plain; charset=\"utf-8\"","Content-Language":"en-US","Content-Transfer-Encoding":"quoted-printable","X-EXCLAIMER-MD-CONFIG":"e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1759394,"web_url":"http://patchwork.ozlabs.org/comment/1759394/","msgid":"<20170829143453.GV6008@atomide.com>","list_archive_url":null,"date":"2017-08-29T14:34:53","subject":"Re: [PATCH 14/17] ARM: dts: Add missing gpu node and binding for\n\tomap4","submitter":{"id":365,"url":"http://patchwork.ozlabs.org/api/people/365/","name":"Tony Lindgren","email":"tony@atomide.com"},"content":"* Tomi Valkeinen [170829 05:25]:\n> \n> Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki\n> \n> On 29/08/17 15:10, Sebastian Reichel wrote:\n> \n> >> Do we even want to add SGX to the .dts? We don't have proper drivers for\n> >> SGX. If we ever do, who knows what kind of DT data they need. I know the\n> >> DT data for SGX in TI's kernel tree has changed at least once.\n> > \n> > I don't think reg or interrupts will be removed, so the properties\n> > added by Tony look pretty safe?. I guess if we ever have a driver\n> \n> Maybe. At the moment we have this in TI's tree for DRA7:\n> \n> gpu: gpu@56000000 {\n> \tcompatible = \"ti,dra7-sgx544\", \"img,sgx544\";\n> \treg = <0x56000000 0x10000>;\n> \treg-names = \"gpu_ocp_base\";\n> \tinterrupts = ;\n> \tti,hwmods = \"gpu\";\n> \tclocks = <&l3_iclk_div>, <&gpu_core_gclk_mux>,\n> \t\t<&gpu_hyd_gclk_mux>;\n> \tclock-names = \"iclk\", \"fclk1\", \"fclk2\";\n> };\n> \n> > it would need some more properties and would bail out. Having no\n> > DT data is does not load at all, the result is the same. OTOH having\n> > the node means the kernel can properly send the module to idle.\n> \n> I just get uneasy when adding DT data that we're not really sure if it's\n> ok or not. I've been fighting with such data for ages. But, as you say,\n> this probably won't matter if the driver will just reject DT data that\n> doesn't have all the details.\n\nThe above example looks OK to me, the interrupt is different for omap4.\n\n> If we need the DT node to idle SGX, and we don't even mean to actually\n> use an SGX driver with this data, it sounds fine to me.\n\nWell ideally the SGX driver will make use of it too. Let me know\nif you want to leave out some parts of the above example from\nTI tree.\n\nRegards,\n\nTony\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xhWPZ628Qz9t38\n\tfor ;\n\tWed, 30 Aug 2017 00:34:58 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1753528AbdH2Oe5 (ORCPT\n\t);\n\tTue, 29 Aug 2017 10:34:57 -0400","from muru.com ([72.249.23.125]:38400 \"EHLO muru.com\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1751485AbdH2Oe4 (ORCPT );\n\tTue, 29 Aug 2017 10:34:56 -0400","from atomide.com (localhost [127.0.0.1])\n\tby muru.com (Postfix) with ESMTPS id 03C8D813A;\n\tTue, 29 Aug 2017 14:35:16 +0000 (UTC)"],"Date":"Tue, 29 Aug 2017 07:34:53 -0700","From":"Tony Lindgren ","To":"Tomi Valkeinen ","Cc":"Sebastian Reichel ,\n\tlinux-omap@vger.kernel.org, =?utf-8?q?Beno=C3=AEt?=\n\tCousson , devicetree@vger.kernel.org","Subject":"Re: [PATCH 14/17] ARM: dts: Add missing gpu node and binding for\n\tomap4","Message-ID":"<20170829143453.GV6008@atomide.com>","References":"<20170828211918.11573-1-tony@atomide.com>\n\t<20170828211918.11573-15-tony@atomide.com>\n\t<20170829090034.ytepjfv2jkkd2b3z@earth>\n\t<201708291135.v7TBZCHH020827@dflxv15.itg.ti.com>\n\t<20170829121041.dweciryplio5i4jr@earth>\n\t","MIME-Version":"1.0","Content-Type":"text/plain; charset=utf-8","Content-Disposition":"inline","Content-Transfer-Encoding":"8bit","In-Reply-To":"","User-Agent":"Mutt/1.8.3 (2017-05-23)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1759397,"web_url":"http://patchwork.ozlabs.org/comment/1759397/","msgid":"<20170829143723.GW6008@atomide.com>","list_archive_url":null,"date":"2017-08-29T14:37:23","subject":"Re: [PATCH 14/17] ARM: dts: Add missing gpu node and binding for\n\tomap4","submitter":{"id":365,"url":"http://patchwork.ozlabs.org/api/people/365/","name":"Tony Lindgren","email":"tony@atomide.com"},"content":"* Tomi Valkeinen [170829 05:28]:\n> \n> Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki\n> \n> On 29/08/17 15:10, Sebastian Reichel wrote:\n> \n> >> Do we even want to add SGX to the .dts? We don't have proper drivers for\n> >> SGX. If we ever do, who knows what kind of DT data they need. I know the\n> >> DT data for SGX in TI's kernel tree has changed at least once.\n> > \n> > I don't think reg or interrupts will be removed, so the properties\n> > added by Tony look pretty safe?. I guess if we ever have a driver\n> \n> Oh, and one more thing about the regs. I believe SGX consists of\n> multiple register blocks. But as it's not documented in any public docs,\n> there's just that single block in the DT data. I'm not sure if single\n> block or multiple blocks would be the right approach, but then, I guess\n> we can always live with just a single block and if needed split the\n> blocks inside the driver.\n\nOK, those register blocks can easily be child nodes of the module\nif needed. This is for the parent interconnect target module\nrevc/sysc/syss registers that we already have mapped in legacy\nplatform data for the interconnect code.\n\nRegards,\n\nTony\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xhWSS4BQtz9s7f\n\tfor ;\n\tWed, 30 Aug 2017 00:37:28 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1754473AbdH2Oh1 (ORCPT\n\t);\n\tTue, 29 Aug 2017 10:37:27 -0400","from muru.com ([72.249.23.125]:38414 \"EHLO muru.com\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1752746AbdH2Oh0 (ORCPT );\n\tTue, 29 Aug 2017 10:37:26 -0400","from atomide.com (localhost [127.0.0.1])\n\tby muru.com (Postfix) with ESMTPS id 5A3968394;\n\tTue, 29 Aug 2017 14:37:47 +0000 (UTC)"],"Date":"Tue, 29 Aug 2017 07:37:23 -0700","From":"Tony Lindgren ","To":"Tomi Valkeinen ","Cc":"Sebastian Reichel ,\n\tlinux-omap@vger.kernel.org, =?utf-8?q?Beno=C3=AEt?=\n\tCousson , devicetree@vger.kernel.org","Subject":"Re: [PATCH 14/17] ARM: dts: Add missing gpu node and binding for\n\tomap4","Message-ID":"<20170829143723.GW6008@atomide.com>","References":"<20170828211918.11573-1-tony@atomide.com>\n\t<20170828211918.11573-15-tony@atomide.com>\n\t<20170829090034.ytepjfv2jkkd2b3z@earth>\n\t<201708291135.v7TBZCHH020827@dflxv15.itg.ti.com>\n\t<20170829121041.dweciryplio5i4jr@earth>\n\t<5efc9078-5886-5826-834e-facd67ddfbe5@ti.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=utf-8","Content-Disposition":"inline","Content-Transfer-Encoding":"8bit","In-Reply-To":"<5efc9078-5886-5826-834e-facd67ddfbe5@ti.com>","User-Agent":"Mutt/1.8.3 (2017-05-23)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1759401,"web_url":"http://patchwork.ozlabs.org/comment/1759401/","msgid":"<20170829144205.GX6008@atomide.com>","list_archive_url":null,"date":"2017-08-29T14:42:05","subject":"Re: [PATCH 14/17] ARM: dts: Add missing gpu node and binding for\n\tomap4","submitter":{"id":365,"url":"http://patchwork.ozlabs.org/api/people/365/","name":"Tony Lindgren","email":"tony@atomide.com"},"content":"* Sebastian Reichel [170829 02:01]:\n> Hi,\n> \n> On Mon, Aug 28, 2017 at 02:19:15PM -0700, Tony Lindgren wrote:\n> > On omap4 we're missing the PowerVR SGX GPU node with it's related\n> > \"ti,hwmods\" property that the SoC interconnect code needs.\n> > \n> > Note that this will only show up as a bug with \"doesn't have\n> > mpu register target base\" boot errors when the legacy platform\n> > data is removed.\n> \n> I think OMAP3 & OMAP5 should also be documented and getting a\n> node in this series?\n\nLooks like we don't currently have any interconnect data defined\nfor those, but yeah sure I can add those.\n\nRegards,\n\nTony\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xhWYs61nnz9t3F\n\tfor ;\n\tWed, 30 Aug 2017 00:42:09 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1754319AbdH2OmI convert rfc822-to-8bit (ORCPT\n\t);\n\tTue, 29 Aug 2017 10:42:08 -0400","from muru.com ([72.249.23.125]:38426 \"EHLO muru.com\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1753807AbdH2OmI (ORCPT );\n\tTue, 29 Aug 2017 10:42:08 -0400","from atomide.com (localhost [127.0.0.1])\n\tby muru.com (Postfix) with ESMTPS id 0D4EB813A;\n\tTue, 29 Aug 2017 14:42:28 +0000 (UTC)"],"Date":"Tue, 29 Aug 2017 07:42:05 -0700","From":"Tony Lindgren ","To":"Sebastian Reichel ","Cc":"linux-omap@vger.kernel.org, =?utf-8?q?Beno=C3=AEt?=\n\tCousson , devicetree@vger.kernel.org,\n\tTomi Valkeinen ","Subject":"Re: [PATCH 14/17] ARM: dts: Add missing gpu node and binding for\n\tomap4","Message-ID":"<20170829144205.GX6008@atomide.com>","References":"<20170828211918.11573-1-tony@atomide.com>\n\t<20170828211918.11573-15-tony@atomide.com>\n\t<20170829090034.ytepjfv2jkkd2b3z@earth>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","Content-Transfer-Encoding":"8BIT","In-Reply-To":"<20170829090034.ytepjfv2jkkd2b3z@earth>","User-Agent":"Mutt/1.8.3 (2017-05-23)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1759458,"web_url":"http://patchwork.ozlabs.org/comment/1759458/","msgid":"","list_archive_url":null,"date":"2017-08-29T15:31:32","subject":"Re: [PATCH 14/17] ARM: dts: Add missing gpu node and binding for\n\tomap4","submitter":{"id":67132,"url":"http://patchwork.ozlabs.org/api/people/67132/","name":"Adam Ford","email":"aford173@gmail.com"},"content":"On Tue, Aug 29, 2017 at 9:42 AM, Tony Lindgren wrote:\n> * Sebastian Reichel [170829 02:01]:\n>> Hi,\n>>\n>> On Mon, Aug 28, 2017 at 02:19:15PM -0700, Tony Lindgren wrote:\n>> > On omap4 we're missing the PowerVR SGX GPU node with it's related\n>> > \"ti,hwmods\" property that the SoC interconnect code needs.\n>> >\n>> > Note that this will only show up as a bug with \"doesn't have\n>> > mpu register target base\" boot errors when the legacy platform\n>> > data is removed.\n>>\n>> I think OMAP3 & OMAP5 should also be documented and getting a\n>> node in this series?\n>\n> Looks like we don't currently have any interconnect data defined\n> for those, but yeah sure I can add those.\n>\n\nIf there is anything I can test, I had modified the SGX driver for the\nOMAP36, but abandoned my attempts since much of the device tree and\nreset stuff was missing. I'd love to see SGX work again. :-)\n\nadam\n\n> Regards,\n>\n> Tony\n> --\n> To unsubscribe from this list: send the line \"unsubscribe linux-omap\" in\n> the body of a message to majordomo@vger.kernel.org\n> More majordomo info at http://vger.kernel.org/majordomo-info.html\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"BsQGhPce\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xhXfw5PMqz9t38\n\tfor ;\n\tWed, 30 Aug 2017 01:31:36 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751388AbdH2Pbf (ORCPT\n\t);\n\tTue, 29 Aug 2017 11:31:35 -0400","from mail-vk0-f68.google.com ([209.85.213.68]:35743 \"EHLO\n\tmail-vk0-f68.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751377AbdH2Pbe (ORCPT\n\t); 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charset=\"UTF-8\"","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1759463,"web_url":"http://patchwork.ozlabs.org/comment/1759463/","msgid":"<20170829153522.GA6008@atomide.com>","list_archive_url":null,"date":"2017-08-29T15:35:22","subject":"Re: [PATCH 14/17] ARM: dts: Add missing gpu node and binding for\n\tomap4","submitter":{"id":365,"url":"http://patchwork.ozlabs.org/api/people/365/","name":"Tony Lindgren","email":"tony@atomide.com"},"content":"* Adam Ford [170829 08:31]:\n> On Tue, Aug 29, 2017 at 9:42 AM, Tony Lindgren wrote:\n> > * Sebastian Reichel [170829 02:01]:\n> >> Hi,\n> >>\n> >> On Mon, Aug 28, 2017 at 02:19:15PM -0700, Tony Lindgren wrote:\n> >> > On omap4 we're missing the PowerVR SGX GPU node with it's related\n> >> > \"ti,hwmods\" property that the SoC interconnect code needs.\n> >> >\n> >> > Note that this will only show up as a bug with \"doesn't have\n> >> > mpu register target base\" boot errors when the legacy platform\n> >> > data is removed.\n> >>\n> >> I think OMAP3 & OMAP5 should also be documented and getting a\n> >> node in this series?\n> >\n> > Looks like we don't currently have any interconnect data defined\n> > for those, but yeah sure I can add those.\n> >\n> \n> If there is anything I can test, I had modified the SGX driver for the\n> OMAP36, but abandoned my attempts since much of the device tree and\n> reset stuff was missing. I'd love to see SGX work again. :-)\n\nWell the resets can be handled using platform data callbacks\nfor now with pdata-quirks.c. Then when the reset driver is available,\nwe can just remove the platform data.\n\nAnd maybe push your changes to some tree so others can participate?\nI'm sure the n900 users would like to see it working too.\n\nRegards,\n\nTony\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xhXlM4npwz9t33\n\tfor ;\n\tWed, 30 Aug 2017 01:35:27 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751583AbdH2Pf0 (ORCPT\n\t);\n\tTue, 29 Aug 2017 11:35:26 -0400","from muru.com ([72.249.23.125]:38474 \"EHLO muru.com\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1751237AbdH2Pf0 (ORCPT );\n\tTue, 29 Aug 2017 11:35:26 -0400","from atomide.com (localhost [127.0.0.1])\n\tby muru.com (Postfix) with ESMTPS id 6D065813A;\n\tTue, 29 Aug 2017 15:35:46 +0000 (UTC)"],"Date":"Tue, 29 Aug 2017 08:35:22 -0700","From":"Tony Lindgren ","To":"Adam Ford ","Cc":"Sebastian Reichel ,\n\tlinux-omap@vger.kernel.org, =?utf-8?q?Beno=C3=AEt?=\n\tCousson , devicetree@vger.kernel.org,\n\tTomi Valkeinen ","Subject":"Re: [PATCH 14/17] ARM: dts: Add missing gpu node and binding for\n\tomap4","Message-ID":"<20170829153522.GA6008@atomide.com>","References":"<20170828211918.11573-1-tony@atomide.com>\n\t<20170828211918.11573-15-tony@atomide.com>\n\t<20170829090034.ytepjfv2jkkd2b3z@earth>\n\t<20170829144205.GX6008@atomide.com>\n\t","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"","User-Agent":"Mutt/1.8.3 (2017-05-23)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1759490,"web_url":"http://patchwork.ozlabs.org/comment/1759490/","msgid":"<20170829155738.GB6008@atomide.com>","list_archive_url":null,"date":"2017-08-29T15:57:38","subject":"Re: [PATCH 14/17] ARM: dts: Add missing gpu node and binding for\n\tomap4","submitter":{"id":365,"url":"http://patchwork.ozlabs.org/api/people/365/","name":"Tony Lindgren","email":"tony@atomide.com"},"content":"* Tony Lindgren [170829 07:35]:\n> * Tomi Valkeinen [170829 05:25]:\n> > Maybe. At the moment we have this in TI's tree for DRA7:\n> > \n> > gpu: gpu@56000000 {\n> > \tcompatible = \"ti,dra7-sgx544\", \"img,sgx544\";\n\nI'll leave out \"img,sgx544\" as that's the generic component\nthat's really a child of this interconnect target module.\n\nRegards,\n\nTony\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xhYF35kqDz9t3P\n\tfor ;\n\tWed, 30 Aug 2017 01:57:43 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751537AbdH2P5m (ORCPT\n\t);\n\tTue, 29 Aug 2017 11:57:42 -0400","from muru.com ([72.249.23.125]:38492 \"EHLO muru.com\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1751323AbdH2P5l (ORCPT );\n\tTue, 29 Aug 2017 11:57:41 -0400","from atomide.com (localhost [127.0.0.1])\n\tby muru.com (Postfix) with ESMTPS id 11238813A;\n\tTue, 29 Aug 2017 15:58:01 +0000 (UTC)"],"Date":"Tue, 29 Aug 2017 08:57:38 -0700","From":"Tony Lindgren ","To":"Tomi Valkeinen ","Cc":"Sebastian Reichel ,\n\tlinux-omap@vger.kernel.org, =?utf-8?q?Beno=C3=AEt?=\n\tCousson , devicetree@vger.kernel.org","Subject":"Re: [PATCH 14/17] ARM: dts: Add missing gpu node and binding for\n\tomap4","Message-ID":"<20170829155738.GB6008@atomide.com>","References":"<20170828211918.11573-1-tony@atomide.com>\n\t<20170828211918.11573-15-tony@atomide.com>\n\t<20170829090034.ytepjfv2jkkd2b3z@earth>\n\t<201708291135.v7TBZCHH020827@dflxv15.itg.ti.com>\n\t<20170829121041.dweciryplio5i4jr@earth>\n\t\n\t<20170829143453.GV6008@atomide.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170829143453.GV6008@atomide.com>","User-Agent":"Mutt/1.8.3 (2017-05-23)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1759513,"web_url":"http://patchwork.ozlabs.org/comment/1759513/","msgid":"<20170829162606.GC6008@atomide.com>","list_archive_url":null,"date":"2017-08-29T16:26:06","subject":"Re: [PATCH 14/17] ARM: dts: Add missing gpu node and binding for\n\tomap4","submitter":{"id":365,"url":"http://patchwork.ozlabs.org/api/people/365/","name":"Tony Lindgren","email":"tony@atomide.com"},"content":"* Tony Lindgren [170829 08:58]:\n> * Tony Lindgren [170829 07:35]:\n> > * Tomi Valkeinen [170829 05:25]:\n> > > Maybe. At the moment we have this in TI's tree for DRA7:\n> > > \n> > > gpu: gpu@56000000 {\n> > > \tcompatible = \"ti,dra7-sgx544\", \"img,sgx544\";\n> \n> I'll leave out \"img,sgx544\" as that's the generic component\n> that's really a child of this interconnect target module.\n\nAnd for the gpu clock, on omap4, it seems that the clocks\nare just the module clktrl with a mux option. So the top\nlevel module driver implementing runtime PM should be\nenough there. And on dra7, there are two functional clocks\nmaybe as the SGX instance is dual core. And the mainline\nkernel is using \"fck\" naming vs \"fclk\" naming. So more\nconsideration is for the clocks and I'll leave them out\nfor now.\n\nRegards,\n\nTony\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xhYsw08Rmz9t3F\n\tfor ;\n\tWed, 30 Aug 2017 02:26:12 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751376AbdH2Q0K (ORCPT\n\t);\n\tTue, 29 Aug 2017 12:26:10 -0400","from muru.com ([72.249.23.125]:38502 \"EHLO muru.com\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1751186AbdH2Q0J (ORCPT );\n\tTue, 29 Aug 2017 12:26:09 -0400","from atomide.com (localhost [127.0.0.1])\n\tby muru.com (Postfix) with ESMTPS id 46B18813A;\n\tTue, 29 Aug 2017 16:26:30 +0000 (UTC)"],"Date":"Tue, 29 Aug 2017 09:26:06 -0700","From":"Tony Lindgren ","To":"Tomi Valkeinen ","Cc":"Sebastian Reichel ,\n\tlinux-omap@vger.kernel.org, =?utf-8?q?Beno=C3=AEt?=\n\tCousson , devicetree@vger.kernel.org","Subject":"Re: [PATCH 14/17] ARM: dts: Add missing gpu node and binding for\n\tomap4","Message-ID":"<20170829162606.GC6008@atomide.com>","References":"<20170828211918.11573-1-tony@atomide.com>\n\t<20170828211918.11573-15-tony@atomide.com>\n\t<20170829090034.ytepjfv2jkkd2b3z@earth>\n\t<201708291135.v7TBZCHH020827@dflxv15.itg.ti.com>\n\t<20170829121041.dweciryplio5i4jr@earth>\n\t\n\t<20170829143453.GV6008@atomide.com>\n\t<20170829155738.GB6008@atomide.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170829155738.GB6008@atomide.com>","User-Agent":"Mutt/1.8.3 (2017-05-23)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}}]