[{"id":1758959,"web_url":"http://patchwork.ozlabs.org/comment/1758959/","msgid":"","list_archive_url":null,"date":"2017-08-29T00:38:31","subject":"Re: [PATCH, rs6000] Fix PR81833 (incorrect code gen for vec_msum)","submitter":{"id":6459,"url":"http://patchwork.ozlabs.org/api/people/6459/","name":"Bill Schmidt","email":"wschmidt@linux.vnet.ibm.com"},"content":"On Aug 28, 2017, at 3:56 PM, Bill Schmidt wrote:\n> \n> Hi, \n> \n> PR81833 identifies a problem with the little-endian vector multiply-sum\n> instructions. The original implementation is quite poor (and I am allowed\n> to say that, since it was mine). This patch fixes the code properly.\n> \n> The revised code still uses UNSPECs for these ops, which is not strictly\n> necessary, although descriptive rtl for them would be pretty complex. I've\n> put in a FIXME to make note of that for a future cleanup.\n> \n> Bootstrapped and tested on powerpc64le-linux-gnu with no regressions. I am\n> currently testing on powerpc64-linux-gnu for 32- and 64-bit. Provided that\n> testing succeeds, is this ok for trunk, and for eventual backport to all\n> supported releases?\n\nFYI, big-endian tests have completed successfully.\n\nBill\n> \n> Thanks,\n> Bill\n> \n> \n> [gcc]\n> \n> 2017-08-28 Bill Schmidt \n> \n> \tPR target/81833\n> \t* config/rs6000/altivec.md (altivec_vsum2sws): Convert from a\n> \tdefine_insn to a define_expand.\n> \t(altivec_vsum2sws_direct): New define_insn.\n> \t(altivec_vsumsws): Convert from a define_insn to a define_expand.\n> \n> [gcc/testsuite]\n> \n> 2017-08-28 Bill Schmidt \n> \n> \tPR target/81833\n> \t* gcc.target/powerpc/pr81833.c: New file.\n> \n> \n> Index: gcc/config/rs6000/altivec.md\n> ===================================================================\n> --- gcc/config/rs6000/altivec.md\t(revision 251369)\n> +++ gcc/config/rs6000/altivec.md\t(working copy)\n> @@ -1804,51 +1804,61 @@\n> \"vsum4ss %0,%1,%2\"\n> [(set_attr \"type\" \"veccomplex\")])\n> \n> -;; FIXME: For the following two patterns, the scratch should only be\n> -;; allocated for !VECTOR_ELT_ORDER_BIG, and the instructions should\n> -;; be emitted separately.\n> -(define_insn \"altivec_vsum2sws\"\n> - [(set (match_operand:V4SI 0 \"register_operand\" \"=v\")\n> - (unspec:V4SI [(match_operand:V4SI 1 \"register_operand\" \"v\")\n> - (match_operand:V4SI 2 \"register_operand\" \"v\")]\n> -\t\t UNSPEC_VSUM2SWS))\n> - (set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))\n> - (clobber (match_scratch:V4SI 3 \"=v\"))]\n> +(define_expand \"altivec_vsum2sws\"\n> + [(use (match_operand:V4SI 0 \"register_operand\"))\n> + (use (match_operand:V4SI 1 \"register_operand\"))\n> + (use (match_operand:V4SI 2 \"register_operand\"))]\n> \"TARGET_ALTIVEC\"\n> {\n> if (VECTOR_ELT_ORDER_BIG)\n> - return \"vsum2sws %0,%1,%2\";\n> + emit_insn (gen_altivec_vsum2sws_direct (operands[0], operands[1],\n> + operands[2]));\n> else\n> - return \"vsldoi %3,%2,%2,12\\n\\tvsum2sws %3,%1,%3\\n\\tvsldoi %0,%3,%3,4\";\n> -}\n> - [(set_attr \"type\" \"veccomplex\")\n> - (set (attr \"length\")\n> - (if_then_else\n> - (match_test \"VECTOR_ELT_ORDER_BIG\")\n> - (const_string \"4\")\n> - (const_string \"12\")))])\n> + {\n> + rtx tmp1 = gen_reg_rtx (V4SImode);\n> + rtx tmp2 = gen_reg_rtx (V4SImode);\n> + emit_insn (gen_altivec_vsldoi_v4si (tmp1, operands[2],\n> + operands[2], GEN_INT (12)));\n> + emit_insn (gen_altivec_vsum2sws_direct (tmp2, operands[1], tmp1));\n> + emit_insn (gen_altivec_vsldoi_v4si (operands[0], tmp2, tmp2,\n> + GEN_INT (4)));\n> + }\n> + DONE;\n> +})\n> \n> -(define_insn \"altivec_vsumsws\"\n> +; FIXME: This can probably be expressed without an UNSPEC.\n> +(define_insn \"altivec_vsum2sws_direct\"\n> [(set (match_operand:V4SI 0 \"register_operand\" \"=v\")\n> (unspec:V4SI [(match_operand:V4SI 1 \"register_operand\" \"v\")\n> - (match_operand:V4SI 2 \"register_operand\" \"v\")]\n> -\t\t UNSPEC_VSUMSWS))\n> - (set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))\n> - (clobber (match_scratch:V4SI 3 \"=v\"))]\n> +\t (match_operand:V4SI 2 \"register_operand\" \"v\")]\n> +\t\t UNSPEC_VSUM2SWS))]\n> \"TARGET_ALTIVEC\"\n> + \"vsum2sws %0,%1,%2\"\n> + [(set_attr \"type\" \"veccomplex\")\n> + (set_attr \"length\" \"4\")])\n> +\n> +(define_expand \"altivec_vsumsws\"\n> + [(use (match_operand:V4SI 0 \"register_operand\"))\n> + (use (match_operand:V4SI 1 \"register_operand\"))\n> + (use (match_operand:V4SI 2 \"register_operand\"))]\n> + \"TARGET_ALTIVEC\"\n> {\n> if (VECTOR_ELT_ORDER_BIG)\n> - return \"vsumsws %0,%1,%2\";\n> + emit_insn (gen_altivec_vsumsws_direct (operands[0], operands[1],\n> + operands[2]));\n> else\n> - return \"vspltw %3,%2,0\\n\\tvsumsws %3,%1,%3\\n\\tvsldoi %0,%3,%3,12\";\n> -}\n> - [(set_attr \"type\" \"veccomplex\")\n> - (set (attr \"length\")\n> - (if_then_else\n> - (match_test \"(VECTOR_ELT_ORDER_BIG)\")\n> - (const_string \"4\")\n> - (const_string \"12\")))])\n> + {\n> + rtx tmp1 = gen_reg_rtx (V4SImode);\n> + rtx tmp2 = gen_reg_rtx (V4SImode);\n> + emit_insn (gen_altivec_vspltw_direct (tmp1, operands[2], const0_rtx));\n> + emit_insn (gen_altivec_vsumsws_direct (tmp2, operands[1], tmp1));\n> + emit_insn (gen_altivec_vsldoi_v4si (operands[0], tmp2, tmp2,\n> + GEN_INT (12)));\n> + }\n> + DONE;\n> +})\n> \n> +; FIXME: This can probably be expressed without an UNSPEC.\n> (define_insn \"altivec_vsumsws_direct\"\n> [(set (match_operand:V4SI 0 \"register_operand\" \"=v\")\n> (unspec:V4SI [(match_operand:V4SI 1 \"register_operand\" \"v\")\n> Index: gcc/testsuite/gcc.target/powerpc/pr81833.c\n> ===================================================================\n> --- gcc/testsuite/gcc.target/powerpc/pr81833.c\t(nonexistent)\n> +++ gcc/testsuite/gcc.target/powerpc/pr81833.c\t(working copy)\n> @@ -0,0 +1,54 @@\n> +/* PR81833: This used to fail due to improper implementation of vec_msum. */\n> +\n> +/* { dg-do run {target { lp64 } } } */\n> +/* { dg-require-effective-target powerpc_altivec_ok } */\n> +\n> +#include \n> +\n> +#define vec_u8 vector unsigned char\n> +#define vec_s8 vector signed char\n> +#define vec_u16 vector unsigned short\n> +#define vec_s16 vector signed short\n> +#define vec_u32 vector unsigned int\n> +#define vec_s32 vector signed int\n> +#define vec_f vector float\n> +\n> +#define LOAD_ZERO const vec_u8 zerov = vec_splat_u8 (0)\n> +\n> +#define zero_u8v (vec_u8) zerov\n> +#define zero_s8v (vec_s8) zerov\n> +#define zero_u16v (vec_u16) zerov\n> +#define zero_s16v (vec_s16) zerov\n> +#define zero_u32v (vec_u32) zerov\n> +#define zero_s32v (vec_s32) zerov\n> +\n> +signed int __attribute__((noinline))\n> +scalarproduct_int16_vsx (const signed short *v1, const signed short *v2,\n> +\t\t\t int order)\n> +{\n> + int i;\n> + LOAD_ZERO;\n> + register vec_s16 vec1;\n> + register vec_s32 res = vec_splat_s32 (0), t;\n> + signed int ires;\n> +\n> + for (i = 0; i < order; i += 8) {\n> + vec1 = vec_vsx_ld (0, v1);\n> + t = vec_msum (vec1, vec_ld (0, v2), zero_s32v);\n> + res = vec_sums (t, res);\n> + v1 += 8;\n> + v2 += 8;\n> + }\n> + res = vec_splat (res, 3);\n> + vec_ste (res, 0, &ires);\n> +\n> + return ires;\n> +}\n> +\n> +int main(void)\n> +{\n> + const signed short test_vec[] = { 1, 1, 1, 1, 1, 1, 1, 1 };\n> + if (scalarproduct_int16_vsx (test_vec, test_vec, 8) != 8)\n> + __builtin_abort ();\n> + return 0;\n> +}\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list gcc-patches@gcc.gnu.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=gcc-patches-return-461055-incoming=patchwork.ozlabs.org@gcc.gnu.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org\n\theader.b=\"fRnR8zDz\"; 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The original implementation is quite poor (and I am allowed\n> to say that, since it was mine). This patch fixes the code properly.\n> \n> The revised code still uses UNSPECs for these ops, which is not strictly\n> necessary, although descriptive rtl for them would be pretty complex. I've\n> put in a FIXME to make note of that for a future cleanup.\n\nThere is ss_plus, but that is the saturated sum of two things, not of\nfive resp. three as we need for vsumsws and vsum2sws.\n\nIf you convert to double-width, then add, then clamp, the result will\nbe correct; but then, very often some of that will be folded away (say,\nwhen combine works on these patterns), and then you need a lot of\ndifferent patterns to catch all of this.\n\nSo we really need an ss_plus that has more than two arguments. We could\nhave an unspec for that as well (instead of the unspecs that work on\nvectors, unspecs that work on the elements), that may work.\n\nOr perhaps it will work best as-is: the only way we get these unspecs\nis via intrinsics, maybe we should just trust the user.\n\n> \tPR target/81833\n> \t* config/rs6000/altivec.md (altivec_vsum2sws): Convert from a\n> \tdefine_insn to a define_expand.\n> \t(altivec_vsum2sws_direct): New define_insn.\n> \t(altivec_vsumsws): Convert from a define_insn to a define_expand.\n> \n> [gcc/testsuite]\n> \n> 2017-08-28 Bill Schmidt \n> \n> \tPR target/81833\n> \t* gcc.target/powerpc/pr81833.c: New file.\n\n\n> +; FIXME: This can probably be expressed without an UNSPEC.\n> +(define_insn \"altivec_vsum2sws_direct\"\n> [(set (match_operand:V4SI 0 \"register_operand\" \"=v\")\n> (unspec:V4SI [(match_operand:V4SI 1 \"register_operand\" \"v\")\n> +\t (match_operand:V4SI 2 \"register_operand\" \"v\")]\n> +\t\t UNSPEC_VSUM2SWS))]\n> \"TARGET_ALTIVEC\"\n> + \"vsum2sws %0,%1,%2\"\n> + [(set_attr \"type\" \"veccomplex\")\n> + (set_attr \"length\" \"4\")])\n\nThis no longer writes to VSCR, please fix that. \"length\" 4 is the\ndefault, just leave it.\n\nvsumsws has both of these correct already.\n\n> --- gcc/testsuite/gcc.target/powerpc/pr81833.c\t(nonexistent)\n> +++ gcc/testsuite/gcc.target/powerpc/pr81833.c\t(working copy)\n> @@ -0,0 +1,54 @@\n> +/* PR81833: This used to fail due to improper implementation of vec_msum. */\n> +\n> +/* { dg-do run {target { lp64 } } } */\n\nDoes this need lp64? I don't at first glance see anything that would\nneed it. Oh, vec_vsx_ld perhaps?\n\nOkay for trunk and branches with the above fixes. Thanks!\n\n\nSegher","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list gcc-patches@gcc.gnu.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=gcc-patches-return-461080-incoming=patchwork.ozlabs.org@gcc.gnu.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org\n\theader.b=\"Uf4p1B7Z\"; dkim-atps=neutral","sourceware.org; auth=none"],"Received":["from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xhS272MT8z9t1t\n\tfor ;\n\tTue, 29 Aug 2017 22:02:47 +1000 (AEST)","(qmail 102468 invoked by alias); 29 Aug 2017 12:02:38 -0000","(qmail 102443 invoked by uid 89); 29 Aug 2017 12:02:37 -0000","from gate.crashing.org (HELO gate.crashing.org) (63.228.1.57) by\n\tsourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP;\n\tTue, 29 Aug 2017 12:02:26 +0000","from gate.crashing.org (localhost.localdomain [127.0.0.1])\tby\n\tgate.crashing.org (8.14.1/8.13.8) with ESMTP id\n\tv7TC2G88008690; Tue, 29 Aug 2017 07:02:16 -0500","(from segher@localhost)\tby gate.crashing.org\n\t(8.14.1/8.14.1/Submit) id v7TC2C1L008686;\n\tTue, 29 Aug 2017 07:02:12 -0500"],"DomainKey-Signature":"a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender:date\n\t:from:to:cc:subject:message-id:references:mime-version\n\t:content-type:in-reply-to; q=dns; s=default; b=ZNcA37hhtCp4OUS79\n\tmWkVeiWxsC9Tz/phuBDfu4TJVy6IYQCB59S3+NW/mkOGv3MJmnHEhJhVeRyumKZK\n\t6uoiqIYNNPdxE+1V+BBjNwb6Er0IStpDpDuV02ctuDe88q8YEX6OLBrD4FeuJxp5\n\t5CD7g0s9+HYz2bKhNf2I/+cQVE=","DKIM-Signature":"v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender:date\n\t:from:to:cc:subject:message-id:references:mime-version\n\t:content-type:in-reply-to; s=default; bh=EJz2EyGQH/UR45DgV6XNBnU\n\tCwJc=; b=Uf4p1B7ZrRfXXZoB2tTHVlQ1VQ9Dr4RZ1Ym15K8HjheVfDsypU1qAMo\n\tg8G3FAavHydhZCGUIVsEi6dInZ/HaOhIHt8ZXTKJxinp6vyjoRNMVbn8YPrsulmt\n\t/8JfcyFfC09dUavn9jBhwbrzZB6brbmuKpa+Zmlb6rTWt0gGEjFE=","Mailing-List":"contact gcc-patches-help@gcc.gnu.org; run by ezmlm","Precedence":"bulk","List-Id":"","List-Unsubscribe":"","List-Archive":"","List-Post":"","List-Help":"","Sender":"gcc-patches-owner@gcc.gnu.org","X-Virus-Found":"No","X-Spam-SWARE-Status":"No, score=-11.1 required=5.0 tests=AWL, BAYES_00,\n\tGIT_PATCH_2, GIT_PATCH_3,\n\tRP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=five","X-HELO":"gate.crashing.org","Date":"Tue, 29 Aug 2017 07:02:11 -0500","From":"Segher Boessenkool ","To":"Bill Schmidt ","Cc":"GCC Patches , David Edelsohn ","Subject":"Re: [PATCH, rs6000] Fix PR81833 (incorrect code gen for vec_msum)","Message-ID":"<20170829120210.GI13471@gate.crashing.org>","References":"<3b753f75-ada4-6f84-a497-8fce45187ae9@linux.vnet.ibm.com>","Mime-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<3b753f75-ada4-6f84-a497-8fce45187ae9@linux.vnet.ibm.com>","User-Agent":"Mutt/1.4.2.3i","X-IsSubscribed":"yes"}}]