[{"id":1761052,"web_url":"http://patchwork.ozlabs.org/comment/1761052/","msgid":"","list_archive_url":null,"date":"2017-08-31T14:23:29","subject":"Re: [PATCH v3 2/2] dt-bindings: designware: add binding for\n\tDesignware PCIe in ECAM mode","submitter":{"id":62529,"url":"http://patchwork.ozlabs.org/api/people/62529/","name":"Rob Herring (Arm)","email":"robh@kernel.org"},"content":"On Mon, Aug 28, 2017 at 1:04 PM, Ard Biesheuvel\n wrote:\n> Describe the binding for firmware-configured instances of the Synopsys\n> Designware PCIe controller in RC mode, that are almost but not quite\n> ECAM compliant.\n>\n> Cc: Rob Herring \n> Signed-off-by: Ard Biesheuvel \n> ---\n> Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt | 42 ++++++++++++++++++++\n> 1 file changed, 42 insertions(+)\n\nAcked-by: Rob Herring \n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","mail.kernel.org;\n\tdmarc=none (p=none dis=none) header.from=kernel.org","mail.kernel.org;\n\tspf=none smtp.mailfrom=robh@kernel.org"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xjl3s487pz9s83\n\tfor ;\n\tFri, 1 Sep 2017 00:23:53 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751346AbdHaOXw (ORCPT\n\t);\n\tThu, 31 Aug 2017 10:23:52 -0400","from mail.kernel.org ([198.145.29.99]:53110 \"EHLO mail.kernel.org\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1751086AbdHaOXv (ORCPT );\n\tThu, 31 Aug 2017 10:23:51 -0400","from mail-qt0-f172.google.com (mail-qt0-f172.google.com\n\t[209.85.216.172])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\tby mail.kernel.org (Postfix) with ESMTPSA id CD5AD21A69;\n\tThu, 31 Aug 2017 14:23:50 +0000 (UTC)","by mail-qt0-f172.google.com with SMTP id h15so3563654qta.4;\n\tThu, 31 Aug 2017 07:23:50 -0700 (PDT)","by 10.12.153.1 with HTTP; Thu, 31 Aug 2017 07:23:29 -0700 (PDT)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mail.kernel.org CD5AD21A69","X-Gm-Message-State":"AHYfb5iwQrOLCh3dbqIAYexNcHwNlRcTfyW0IMH6G1GLre5sZabTnNjp\n\tfOsoDbzGGLR/PgHuiLV7akY4JHq4EA==","X-Google-Smtp-Source":"ADKCNb7viyHge8teyA177KAaYyC+eeKrfWWRjMjZW6H/JnJMG7L5fwnjFNPiVH4pCwje1Kz73Nnd+kyRjTNjlefr3hM=","X-Received":"by 10.237.62.82 with SMTP id m18mr7846099qtf.29.1504189429920;\n\tThu, 31 Aug 2017 07:23:49 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"<20170828180437.2646-3-ard.biesheuvel@linaro.org>","References":"<20170828180437.2646-1-ard.biesheuvel@linaro.org>\n\t<20170828180437.2646-3-ard.biesheuvel@linaro.org>","From":"Rob Herring ","Date":"Thu, 31 Aug 2017 09:23:29 -0500","X-Gmail-Original-Message-ID":"","Message-ID":"","Subject":"Re: [PATCH v3 2/2] dt-bindings: designware: add binding for\n\tDesignware PCIe in ECAM mode","To":"Ard Biesheuvel ","Cc":"\"linux-pci@vger.kernel.org\" ,\n\t\"devicetree@vger.kernel.org\" ,\n\tMarcin Wojtas ,\n\tLeif Lindholm , \n\tGraeme Gregory ,\n\tBjorn Helgaas , Jingoo Han ,\n\tJoao Pinto ","Content-Type":"text/plain; charset=\"UTF-8\"","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}}]