[{"id":1758880,"web_url":"http://patchwork.ozlabs.org/comment/1758880/","msgid":"","list_archive_url":null,"date":"2017-08-28T21:57:54","subject":"Re: [Qemu-devel] [Qemu devel v7 PATCH 4/5] msf2: Add Smartfusion2\n\tSoC","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/people/64571/","name":"Alistair Francis","email":"alistair23@gmail.com"},"content":"On Mon, Aug 28, 2017 at 9:38 AM, Subbaraya Sundeep\n wrote:\n> Smartfusion2 SoC has hardened Microcontroller subsystem\n> and flash based FPGA fabric. This patch adds support for\n> Microcontroller subsystem in the SoC.\n>\n> Signed-off-by: Subbaraya Sundeep \n\nIt looks like I have reviewed this one previously as well. Unless\nthere were any major changes since then you can re-add my reviewed by\ntag.\n\nThanks,\nAlistair\n\n> ---\n> default-configs/arm-softmmu.mak | 1 +\n> hw/arm/Makefile.objs | 1 +\n> hw/arm/msf2-soc.c | 215 ++++++++++++++++++++++++++++++++++++++++\n> include/hw/arm/msf2-soc.h | 66 ++++++++++++\n> 4 files changed, 283 insertions(+)\n> create mode 100644 hw/arm/msf2-soc.c\n> create mode 100644 include/hw/arm/msf2-soc.h\n>\n> diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak\n> index bbdd3c1..5059d13 100644\n> --- a/default-configs/arm-softmmu.mak\n> +++ b/default-configs/arm-softmmu.mak\n> @@ -129,3 +129,4 @@ CONFIG_ACPI=y\n> CONFIG_SMBIOS=y\n> CONFIG_ASPEED_SOC=y\n> CONFIG_GPIO_KEY=y\n> +CONFIG_MSF2=y\n> diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs\n> index a2e56ec..df36a03 100644\n> --- a/hw/arm/Makefile.objs\n> +++ b/hw/arm/Makefile.objs\n> @@ -19,3 +19,4 @@ obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o\n> obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o\n> obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o\n> obj-$(CONFIG_MPS2) += mps2.o\n> +obj-$(CONFIG_MSF2) += msf2-soc.o\n> diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c\n> new file mode 100644\n> index 0000000..276eec5\n> --- /dev/null\n> +++ b/hw/arm/msf2-soc.c\n> @@ -0,0 +1,215 @@\n> +/*\n> + * SmartFusion2 SoC emulation.\n> + *\n> + * Copyright (c) 2017 Subbaraya Sundeep \n> + *\n> + * Permission is hereby granted, free of charge, to any person obtaining a copy\n> + * of this software and associated documentation files (the \"Software\"), to deal\n> + * in the Software without restriction, including without limitation the rights\n> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n> + * copies of the Software, and to permit persons to whom the Software is\n> + * furnished to do so, subject to the following conditions:\n> + *\n> + * The above copyright notice and this permission notice shall be included in\n> + * all copies or substantial portions of the Software.\n> + *\n> + * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n> + * THE SOFTWARE.\n> + */\n> +\n> +#include \"qemu/osdep.h\"\n> +#include \"qapi/error.h\"\n> +#include \"qemu-common.h\"\n> +#include \"hw/arm/arm.h\"\n> +#include \"exec/address-spaces.h\"\n> +#include \"hw/char/serial.h\"\n> +#include \"hw/boards.h\"\n> +#include \"sysemu/block-backend.h\"\n> +#include \"qemu/cutils.h\"\n> +#include \"hw/arm/msf2-soc.h\"\n> +\n> +#define MSF2_TIMER_BASE 0x40004000\n> +#define MSF2_SYSREG_BASE 0x40038000\n> +\n> +#define ENVM_BASE_ADDRESS 0x60000000\n> +\n> +#define SRAM_BASE_ADDRESS 0x20000000\n> +\n> +#define MSF2_ENVM_SIZE (512 * K_BYTE)\n> +#define MSF2_ESRAM_SIZE (64 * K_BYTE)\n> +\n> +static const uint32_t spi_addr[MSF2_NUM_SPIS] = { 0x40001000 , 0x40011000 };\n> +static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x40000000 , 0x40010000 };\n> +\n> +static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 };\n> +static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 };\n> +static const int timer_irq[MSF2_NUM_TIMERS] = { 14, 15 };\n> +\n> +static void m2sxxx_soc_initfn(Object *obj)\n> +{\n> + MSF2State *s = MSF2_SOC(obj);\n> + int i;\n> +\n> + object_initialize(&s->armv7m, sizeof(s->armv7m), TYPE_ARMV7M);\n> + qdev_set_parent_bus(DEVICE(&s->armv7m), sysbus_get_default());\n> +\n> + object_initialize(&s->sysreg, sizeof(s->sysreg), TYPE_MSF2_SYSREG);\n> + qdev_set_parent_bus(DEVICE(&s->sysreg), sysbus_get_default());\n> +\n> + object_initialize(&s->timer, sizeof(s->timer), TYPE_MSS_TIMER);\n> + qdev_set_parent_bus(DEVICE(&s->timer), sysbus_get_default());\n> +\n> + for (i = 0; i < MSF2_NUM_SPIS; i++) {\n> + object_initialize(&s->spi[i], sizeof(s->spi[i]),\n> + TYPE_MSS_SPI);\n> + qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());\n> + }\n> +}\n> +\n> +static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)\n> +{\n> + MSF2State *s = MSF2_SOC(dev_soc);\n> + DeviceState *dev, *armv7m;\n> + SysBusDevice *busdev;\n> + Error *err = NULL;\n> + int i;\n> +\n> + MemoryRegion *system_memory = get_system_memory();\n> + MemoryRegion *nvm = g_new(MemoryRegion, 1);\n> + MemoryRegion *nvm_alias = g_new(MemoryRegion, 1);\n> + MemoryRegion *sram = g_new(MemoryRegion, 1);\n> +\n> + memory_region_init_ram(nvm, NULL, \"MSF2.eNVM\", s->envm_size,\n> + &error_fatal);\n> +\n> + /*\n> + * On power-on, the eNVM region 0x60000000 is automatically\n> + * remapped to the Cortex-M3 processor executable region\n> + * start address (0x0). We do not support remapping other eNVM,\n> + * eSRAM and DDR regions by guest(via Sysreg) currently.\n> + */\n> + memory_region_init_alias(nvm_alias, NULL, \"MSF2.eNVM.alias\",\n> + nvm, 0, s->envm_size);\n> +\n> + memory_region_set_readonly(nvm, true);\n> + memory_region_set_readonly(nvm_alias, true);\n> +\n> + memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS, nvm);\n> + memory_region_add_subregion(system_memory, 0, nvm_alias);\n> +\n> + memory_region_init_ram(sram, NULL, \"MSF2.eSRAM\", s->esram_size,\n> + &error_fatal);\n> + memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);\n> +\n> + armv7m = DEVICE(&s->armv7m);\n> + qdev_prop_set_uint32(armv7m, \"num-irq\", 81);\n> + qdev_prop_set_string(armv7m, \"cpu-model\", \"cortex-m3\");\n> + object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),\n> + \"memory\", &error_abort);\n> + object_property_set_bool(OBJECT(&s->armv7m), true, \"realized\", &err);\n> + if (err != NULL) {\n> + error_propagate(errp, err);\n> + return;\n> + }\n> +\n> + system_clock_scale = NANOSECONDS_PER_SECOND / s->m3clk;\n> +\n> + for (i = 0; i < MSF2_NUM_UARTS; i++) {\n> + if (serial_hds[i]) {\n> + serial_mm_init(get_system_memory(), uart_addr[i], 2,\n> + qdev_get_gpio_in(armv7m, uart_irq[i]),\n> + 115200, serial_hds[i], DEVICE_NATIVE_ENDIAN);\n> + }\n> + }\n> +\n> + dev = DEVICE(&s->timer);\n> + /* APB0 clock is the timer input clock */\n> + qdev_prop_set_uint32(dev, \"clock-frequency\", s->m3clk / s->apb0div);\n> + object_property_set_bool(OBJECT(&s->timer), true, \"realized\", &err);\n> + if (err != NULL) {\n> + error_propagate(errp, err);\n> + return;\n> + }\n> + busdev = SYS_BUS_DEVICE(dev);\n> + sysbus_mmio_map(busdev, 0, MSF2_TIMER_BASE);\n> + sysbus_connect_irq(busdev, 0,\n> + qdev_get_gpio_in(armv7m, timer_irq[0]));\n> + sysbus_connect_irq(busdev, 1,\n> + qdev_get_gpio_in(armv7m, timer_irq[1]));\n> +\n> + dev = DEVICE(&s->sysreg);\n> + qdev_prop_set_uint32(dev, \"apb0divisor\", s->apb0div);\n> + qdev_prop_set_uint32(dev, \"apb1divisor\", s->apb1div);\n> + object_property_set_bool(OBJECT(&s->sysreg), true, \"realized\", &err);\n> + if (err != NULL) {\n> + error_propagate(errp, err);\n> + return;\n> + }\n> + busdev = SYS_BUS_DEVICE(dev);\n> + sysbus_mmio_map(busdev, 0, MSF2_SYSREG_BASE);\n> +\n> + for (i = 0; i < MSF2_NUM_SPIS; i++) {\n> + gchar *bus_name = g_strdup_printf(\"spi%d\", i);\n> +\n> + object_property_set_bool(OBJECT(&s->spi[i]), true, \"realized\", &err);\n> + if (err != NULL) {\n> + g_free(bus_name);\n> + error_propagate(errp, err);\n> + return;\n> + }\n> +\n> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);\n> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,\n> + qdev_get_gpio_in(armv7m, spi_irq[i]));\n> +\n> + /* Alias controller SPI bus to the SoC itself */\n> + object_property_add_alias(OBJECT(s), bus_name,\n> + OBJECT(&s->spi[i]), \"spi\",\n> + &error_abort);\n> + g_free(bus_name);\n> + }\n> +}\n> +\n> +static Property m2sxxx_soc_properties[] = {\n> + /*\n> + * part name specifies the type of SmartFusion2 device variant(this\n> + * property is for information purpose only.\n> + */\n> + DEFINE_PROP_STRING(\"part-name\", MSF2State, part_name),\n> + DEFINE_PROP_UINT64(\"eNVM-size\", MSF2State, envm_size, MSF2_ENVM_SIZE),\n> + DEFINE_PROP_UINT64(\"eSRAM-size\", MSF2State, esram_size, MSF2_ESRAM_SIZE),\n> + /* Libero GUI shows 100Mhz as default for clocks */\n> + DEFINE_PROP_UINT32(\"m3clk\", MSF2State, m3clk, 100 * 1000000),\n> + /* default divisors in Libero GUI */\n> + DEFINE_PROP_UINT32(\"apb0div\", MSF2State, apb0div, 2),\n> + DEFINE_PROP_UINT32(\"apb1div\", MSF2State, apb1div, 2),\n> + DEFINE_PROP_END_OF_LIST(),\n> +};\n> +\n> +static void m2sxxx_soc_class_init(ObjectClass *klass, void *data)\n> +{\n> + DeviceClass *dc = DEVICE_CLASS(klass);\n> +\n> + dc->realize = m2sxxx_soc_realize;\n> + dc->props = m2sxxx_soc_properties;\n> +}\n> +\n> +static const TypeInfo m2sxxx_soc_info = {\n> + .name = TYPE_MSF2_SOC,\n> + .parent = TYPE_SYS_BUS_DEVICE,\n> + .instance_size = sizeof(MSF2State),\n> + .instance_init = m2sxxx_soc_initfn,\n> + .class_init = m2sxxx_soc_class_init,\n> +};\n> +\n> +static void m2sxxx_soc_types(void)\n> +{\n> + type_register_static(&m2sxxx_soc_info);\n> +}\n> +\n> +type_init(m2sxxx_soc_types)\n> diff --git a/include/hw/arm/msf2-soc.h b/include/hw/arm/msf2-soc.h\n> new file mode 100644\n> index 0000000..eb239fa\n> --- /dev/null\n> +++ b/include/hw/arm/msf2-soc.h\n> @@ -0,0 +1,66 @@\n> +/*\n> + * Microsemi Smartfusion2 SoC\n> + *\n> + * Copyright (c) 2017 Subbaraya Sundeep \n> + *\n> + * Permission is hereby granted, free of charge, to any person obtaining a copy\n> + * of this software and associated documentation files (the \"Software\"), to deal\n> + * in the Software without restriction, including without limitation the rights\n> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n> + * copies of the Software, and to permit persons to whom the Software is\n> + * furnished to do so, subject to the following conditions:\n> + *\n> + * The above copyright notice and this permission notice shall be included in\n> + * all copies or substantial portions of the Software.\n> + *\n> + * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n> + * THE SOFTWARE.\n> + */\n> +\n> +#ifndef HW_ARM_MSF2_SOC_H\n> +#define HW_ARM_MSF2_SOC_H\n> +\n> +#include \"hw/arm/armv7m.h\"\n> +#include \"hw/timer/mss-timer.h\"\n> +#include \"hw/misc/msf2-sysreg.h\"\n> +#include \"hw/ssi/mss-spi.h\"\n> +\n> +#define TYPE_MSF2_SOC \"msf2-soc\"\n> +#define MSF2_SOC(obj) OBJECT_CHECK(MSF2State, (obj), TYPE_MSF2_SOC)\n> +\n> +#define MSF2_NUM_SPIS 2\n> +#define MSF2_NUM_UARTS 2\n> +\n> +/*\n> + * System timer consists of two programmable 32-bit\n> + * decrementing counters that generate individual interrupts to\n> + * the Cortex-M3 processor\n> + */\n> +#define MSF2_NUM_TIMERS 2\n> +\n> +typedef struct MSF2State {\n> + /*< private >*/\n> + SysBusDevice parent_obj;\n> + /*< public >*/\n> +\n> + ARMv7MState armv7m;\n> +\n> + char *part_name;\n> + uint64_t envm_size;\n> + uint64_t esram_size;\n> +\n> + uint32_t m3clk;\n> + uint32_t apb0div;\n> + uint32_t apb1div;\n> +\n> + MSF2SysregState sysreg;\n> + MSSTimerState timer;\n> + MSSSpiState spi[MSF2_NUM_SPIS];\n> +} MSF2State;\n> +\n> +#endif\n> --\n> 2.5.0\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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charset=\"UTF-8\"","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2a00:1450:400c:c0c::244","Subject":"Re: [Qemu-devel] [Qemu devel v7 PATCH 4/5] msf2: Add Smartfusion2\n\tSoC","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Peter Maydell , =?utf-8?q?Philippe_Mathieu-D?=\n\t=?utf-8?b?YXVkw6k=?= , \tqemu-arm ,\n\t\"qemu-devel@nongnu.org Developers\" , \n\tPeter Crosthwaite ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1759853,"web_url":"http://patchwork.ozlabs.org/comment/1759853/","msgid":"<10da5552-c90a-21e6-43ac-829932f64930@amsat.org>","list_archive_url":null,"date":"2017-08-30T02:45:38","subject":"Re: [Qemu-devel] [Qemu devel v7 PATCH 4/5] msf2: Add Smartfusion2\n\tSoC","submitter":{"id":70924,"url":"http://patchwork.ozlabs.org/api/people/70924/","name":"Philippe Mathieu-Daudé","email":"f4bug@amsat.org"},"content":"Hi Subbaraya,\n\nOn 08/28/2017 01:38 PM, Subbaraya Sundeep wrote:\n> Smartfusion2 SoC has hardened Microcontroller subsystem\n> and flash based FPGA fabric. This patch adds support for\n> Microcontroller subsystem in the SoC.\n> \n> Signed-off-by: Subbaraya Sundeep \n> ---\n> default-configs/arm-softmmu.mak | 1 +\n> hw/arm/Makefile.objs | 1 +\n> hw/arm/msf2-soc.c | 215 ++++++++++++++++++++++++++++++++++++++++\n> include/hw/arm/msf2-soc.h | 66 ++++++++++++\n> 4 files changed, 283 insertions(+)\n> create mode 100644 hw/arm/msf2-soc.c\n> create mode 100644 include/hw/arm/msf2-soc.h\n> \n> diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak\n> index bbdd3c1..5059d13 100644\n> --- a/default-configs/arm-softmmu.mak\n> +++ b/default-configs/arm-softmmu.mak\n> @@ -129,3 +129,4 @@ CONFIG_ACPI=y\n> CONFIG_SMBIOS=y\n> CONFIG_ASPEED_SOC=y\n> CONFIG_GPIO_KEY=y\n> +CONFIG_MSF2=y\n> diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs\n> index a2e56ec..df36a03 100644\n> --- a/hw/arm/Makefile.objs\n> +++ b/hw/arm/Makefile.objs\n> @@ -19,3 +19,4 @@ obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o\n> obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o\n> obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o\n> obj-$(CONFIG_MPS2) += mps2.o\n> +obj-$(CONFIG_MSF2) += msf2-soc.o\n> diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c\n> new file mode 100644\n> index 0000000..276eec5\n> --- /dev/null\n> +++ b/hw/arm/msf2-soc.c\n> @@ -0,0 +1,215 @@\n> +/*\n> + * SmartFusion2 SoC emulation.\n> + *\n> + * Copyright (c) 2017 Subbaraya Sundeep \n> + *\n> + * Permission is hereby granted, free of charge, to any person obtaining a copy\n> + * of this software and associated documentation files (the \"Software\"), to deal\n> + * in the Software without restriction, including without limitation the rights\n> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n> + * copies of the Software, and to permit persons to whom the Software is\n> + * furnished to do so, subject to the following conditions:\n> + *\n> + * The above copyright notice and this permission notice shall be included in\n> + * all copies or substantial portions of the Software.\n> + *\n> + * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n> + * THE SOFTWARE.\n> + */\n> +\n> +#include \"qemu/osdep.h\"\n> +#include \"qapi/error.h\"\n> +#include \"qemu-common.h\"\n> +#include \"hw/arm/arm.h\"\n> +#include \"exec/address-spaces.h\"\n> +#include \"hw/char/serial.h\"\n> +#include \"hw/boards.h\"\n> +#include \"sysemu/block-backend.h\"\n> +#include \"qemu/cutils.h\"\n> +#include \"hw/arm/msf2-soc.h\"\n> +\n> +#define MSF2_TIMER_BASE 0x40004000\n> +#define MSF2_SYSREG_BASE 0x40038000\n> +\n> +#define ENVM_BASE_ADDRESS 0x60000000\n> +\n> +#define SRAM_BASE_ADDRESS 0x20000000\n> +\n> +#define MSF2_ENVM_SIZE (512 * K_BYTE)\n> +#define MSF2_ESRAM_SIZE (64 * K_BYTE)\n\nEventually you should name those _SIZE_MAX.\n\nI miscorrected you in v4, 64kB is true with SECDED disabled, else the \nSoC is designed for 80kB. Not a big deal, we can add a \"SECDED not \nsupported\" warning later.\nCan you add a comment about it?\n\n> +\n> +static const uint32_t spi_addr[MSF2_NUM_SPIS] = { 0x40001000 , 0x40011000 };\n> +static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x40000000 , 0x40010000 };\n> +\n> +static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 };\n> +static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 };\n> +static const int timer_irq[MSF2_NUM_TIMERS] = { 14, 15 };\n> +\n> +static void m2sxxx_soc_initfn(Object *obj)\n> +{\n> + MSF2State *s = MSF2_SOC(obj);\n> + int i;\n> +\n> + object_initialize(&s->armv7m, sizeof(s->armv7m), TYPE_ARMV7M);\n> + qdev_set_parent_bus(DEVICE(&s->armv7m), sysbus_get_default());\n> +\n> + object_initialize(&s->sysreg, sizeof(s->sysreg), TYPE_MSF2_SYSREG);\n> + qdev_set_parent_bus(DEVICE(&s->sysreg), sysbus_get_default());\n> +\n> + object_initialize(&s->timer, sizeof(s->timer), TYPE_MSS_TIMER);\n> + qdev_set_parent_bus(DEVICE(&s->timer), sysbus_get_default());\n> +\n\nWhat about the UARTs?\n\n> + for (i = 0; i < MSF2_NUM_SPIS; i++) {\n> + object_initialize(&s->spi[i], sizeof(s->spi[i]),\n> + TYPE_MSS_SPI);\n> + qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());\n> + }\n> +}\n> +\n> +static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)\n> +{\n> + MSF2State *s = MSF2_SOC(dev_soc);\n> + DeviceState *dev, *armv7m;\n> + SysBusDevice *busdev;\n> + Error *err = NULL;\n> + int i;\n> +\n> + MemoryRegion *system_memory = get_system_memory();\n> + MemoryRegion *nvm = g_new(MemoryRegion, 1);\n> + MemoryRegion *nvm_alias = g_new(MemoryRegion, 1);\n> + MemoryRegion *sram = g_new(MemoryRegion, 1);\n> +\n> + memory_region_init_ram(nvm, NULL, \"MSF2.eNVM\", s->envm_size,\n> + &error_fatal);\n\nWhy do you initialize as RAM? I'd rather use \nmemory_region_init_rom_device() here, so you can boot a dumped eNVM flash.\n\n> +\n> + /*\n> + * On power-on, the eNVM region 0x60000000 is automatically\n> + * remapped to the Cortex-M3 processor executable region\n> + * start address (0x0). We do not support remapping other eNVM,\n> + * eSRAM and DDR regions by guest(via Sysreg) currently.\n> + */\n> + memory_region_init_alias(nvm_alias, NULL, \"MSF2.eNVM.alias\",\n> + nvm, 0, s->envm_size);\n> +\n> + memory_region_set_readonly(nvm, true);\n> + memory_region_set_readonly(nvm_alias, true);\n\nHmmm not sure the alias needs this.\n\n> +\n> + memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS, nvm);\n> + memory_region_add_subregion(system_memory, 0, nvm_alias);\n> +\n> + memory_region_init_ram(sram, NULL, \"MSF2.eSRAM\", s->esram_size,\n> + &error_fatal);\n> + memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);\n> +\n> + armv7m = DEVICE(&s->armv7m);\n> + qdev_prop_set_uint32(armv7m, \"num-irq\", 81);\n> + qdev_prop_set_string(armv7m, \"cpu-model\", \"cortex-m3\");\n> + object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),\n> + \"memory\", &error_abort);\n> + object_property_set_bool(OBJECT(&s->armv7m), true, \"realized\", &err);\n> + if (err != NULL) {\n> + error_propagate(errp, err);\n> + return;\n> + }\n> +\n> + system_clock_scale = NANOSECONDS_PER_SECOND / s->m3clk;\n> +\n> + for (i = 0; i < MSF2_NUM_UARTS; i++) {\n> + if (serial_hds[i]) {\n\nI think they might be issues if you start QEMU without -serial and then \nuse a firmware polling for an uart, the device won't be mapped and the \nmemory accesses are mostly ignored.\n\nI'd rather use:\n\n for (i = 0; i < MSF2_NUM_UARTS && i < MAX_SERIAL_PORTS; i++) {\n static const char *serial[] = {\"serial0\", \"serial1\"};\n\n if (!serial_hds[i]) {\n serial_hds[i] = qemu_chr_new(serial[i], \"null\");\n }\n\n> + serial_mm_init(get_system_memory(), uart_addr[i], 2,\n> + qdev_get_gpio_in(armv7m, uart_irq[i]),\n> + 115200, serial_hds[i], DEVICE_NATIVE_ENDIAN);\n> + }\n> + }\n> +\n> + dev = DEVICE(&s->timer);\n> + /* APB0 clock is the timer input clock */\n> + qdev_prop_set_uint32(dev, \"clock-frequency\", s->m3clk / s->apb0div);\n> + object_property_set_bool(OBJECT(&s->timer), true, \"realized\", &err);\n> + if (err != NULL) {\n> + error_propagate(errp, err);\n> + return;\n> + }\n> + busdev = SYS_BUS_DEVICE(dev);\n> + sysbus_mmio_map(busdev, 0, MSF2_TIMER_BASE);\n> + sysbus_connect_irq(busdev, 0,\n> + qdev_get_gpio_in(armv7m, timer_irq[0]));\n> + sysbus_connect_irq(busdev, 1,\n> + qdev_get_gpio_in(armv7m, timer_irq[1]));\n> +\n> + dev = DEVICE(&s->sysreg);\n> + qdev_prop_set_uint32(dev, \"apb0divisor\", s->apb0div);\n> + qdev_prop_set_uint32(dev, \"apb1divisor\", s->apb1div);\n> + object_property_set_bool(OBJECT(&s->sysreg), true, \"realized\", &err);\n> + if (err != NULL) {\n> + error_propagate(errp, err);\n> + return;\n> + }\n> + busdev = SYS_BUS_DEVICE(dev);\n> + sysbus_mmio_map(busdev, 0, MSF2_SYSREG_BASE);\n> +\n> + for (i = 0; i < MSF2_NUM_SPIS; i++) {\n> + gchar *bus_name = g_strdup_printf(\"spi%d\", i);\n\nmove g_strdup_printf() down ...\n\n> +\n> + object_property_set_bool(OBJECT(&s->spi[i]), true, \"realized\", &err);\n> + if (err != NULL) {\n> + g_free(bus_name);\n\nso this g_free() is not needed.\n\n> + error_propagate(errp, err);\n> + return;\n> + }\n> +\n> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);\n> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,\n> + qdev_get_gpio_in(armv7m, spi_irq[i]));\n> +\n> + /* Alias controller SPI bus to the SoC itself */\n\nHere:\n bus_name = g_strdup_printf(\"spi%d\", i);\n\n> + object_property_add_alias(OBJECT(s), bus_name,\n> + OBJECT(&s->spi[i]), \"spi\",\n> + &error_abort);\n> + g_free(bus_name);\n> + }\n> +}\n> +\n> +static Property m2sxxx_soc_properties[] = {\n> + /*\n> + * part name specifies the type of SmartFusion2 device variant(this\n> + * property is for information purpose only.\n> + */\n> + DEFINE_PROP_STRING(\"part-name\", MSF2State, part_name),\n> + DEFINE_PROP_UINT64(\"eNVM-size\", MSF2State, envm_size, MSF2_ENVM_SIZE),\n> + DEFINE_PROP_UINT64(\"eSRAM-size\", MSF2State, esram_size, MSF2_ESRAM_SIZE),\n> + /* Libero GUI shows 100Mhz as default for clocks */\n> + DEFINE_PROP_UINT32(\"m3clk\", MSF2State, m3clk, 100 * 1000000),\n> + /* default divisors in Libero GUI */\n> + DEFINE_PROP_UINT32(\"apb0div\", MSF2State, apb0div, 2),\n> + DEFINE_PROP_UINT32(\"apb1div\", MSF2State, apb1div, 2),\n> + DEFINE_PROP_END_OF_LIST(),\n> +};\n> +\n> +static void m2sxxx_soc_class_init(ObjectClass *klass, void *data)\n> +{\n> + DeviceClass *dc = DEVICE_CLASS(klass);\n> +\n> + dc->realize = m2sxxx_soc_realize;\n> + dc->props = m2sxxx_soc_properties;\n> +}\n> +\n> +static const TypeInfo m2sxxx_soc_info = {\n> + .name = TYPE_MSF2_SOC,\n> + .parent = TYPE_SYS_BUS_DEVICE,\n> + .instance_size = sizeof(MSF2State),\n> + .instance_init = m2sxxx_soc_initfn,\n> + .class_init = m2sxxx_soc_class_init,\n> +};\n> +\n> +static void m2sxxx_soc_types(void)\n> +{\n> + type_register_static(&m2sxxx_soc_info);\n> +}\n> +\n> +type_init(m2sxxx_soc_types)\n> diff --git a/include/hw/arm/msf2-soc.h b/include/hw/arm/msf2-soc.h\n> new file mode 100644\n> index 0000000..eb239fa\n> --- /dev/null\n> +++ b/include/hw/arm/msf2-soc.h\n> @@ -0,0 +1,66 @@\n> +/*\n> + * Microsemi Smartfusion2 SoC\n> + *\n> + * Copyright (c) 2017 Subbaraya Sundeep \n> + *\n> + * Permission is hereby granted, free of charge, to any person obtaining a copy\n> + * of this software and associated documentation files (the \"Software\"), to deal\n> + * in the Software without restriction, including without limitation the rights\n> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n> + * copies of the Software, and to permit persons to whom the Software is\n> + * furnished to do so, subject to the following conditions:\n> + *\n> + * The above copyright notice and this permission notice shall be included in\n> + * all copies or substantial portions of the Software.\n> + *\n> + * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n> + * THE SOFTWARE.\n> + */\n> +\n> +#ifndef HW_ARM_MSF2_SOC_H\n> +#define HW_ARM_MSF2_SOC_H\n> +\n> +#include \"hw/arm/armv7m.h\"\n> +#include \"hw/timer/mss-timer.h\"\n> +#include \"hw/misc/msf2-sysreg.h\"\n> +#include \"hw/ssi/mss-spi.h\"\n> +\n> +#define TYPE_MSF2_SOC \"msf2-soc\"\n> +#define MSF2_SOC(obj) OBJECT_CHECK(MSF2State, (obj), TYPE_MSF2_SOC)\n> +\n> +#define MSF2_NUM_SPIS 2\n> +#define MSF2_NUM_UARTS 2\n> +\n> +/*\n> + * System timer consists of two programmable 32-bit\n> + * decrementing counters that generate individual interrupts to\n> + * the Cortex-M3 processor\n> + */\n> +#define MSF2_NUM_TIMERS 2\n> +\n> +typedef struct MSF2State {\n> + /*< private >*/\n> + SysBusDevice parent_obj;\n> + /*< public >*/\n> +\n> + ARMv7MState armv7m;\n> +\n> + char *part_name;\n> + uint64_t envm_size;\n> + uint64_t esram_size;\n> +\n> + uint32_t m3clk;\n> + uint32_t apb0div;\n> + uint32_t apb1div;\n> +\n> + MSF2SysregState sysreg;\n> + MSSTimerState timer;\n> + MSSSpiState spi[MSF2_NUM_SPIS];\n> +} MSF2State;\n> +\n> +#endif\n\nAlmost there :)\n\nAre you OK to:\n- register eNVM as ROM\n- check UARTs?\n\nRegards,\n\nPhil.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1503938283-12404-5-git-send-email-sundeep.lkml@gmail.com>","Content-Type":"text/plain; charset=utf-8; format=flowed","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400d:c09::241","Subject":"Re: [Qemu-devel] [Qemu devel v7 PATCH 4/5] msf2: Add Smartfusion2\n\tSoC","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"peter.maydell@linaro.org, alistair23@gmail.com,\n\tcrosthwaite.peter@gmail.com","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1760108,"web_url":"http://patchwork.ozlabs.org/comment/1760108/","msgid":"","list_archive_url":null,"date":"2017-08-30T12:23:18","subject":"Re: [Qemu-devel] [Qemu devel v7 PATCH 4/5] msf2: Add Smartfusion2\n\tSoC","submitter":{"id":64324,"url":"http://patchwork.ozlabs.org/api/people/64324/","name":"sundeep subbaraya","email":"sundeep.lkml@gmail.com"},"content":"Hi Philippe,\n\nOn Wed, Aug 30, 2017 at 8:15 AM, Philippe Mathieu-Daudé \nwrote:\n\n> Hi Subbaraya,\n>\n>\n> On 08/28/2017 01:38 PM, Subbaraya Sundeep wrote:\n>\n>> Smartfusion2 SoC has hardened Microcontroller subsystem\n>> and flash based FPGA fabric. This patch adds support for\n>> Microcontroller subsystem in the SoC.\n>>\n>> Signed-off-by: Subbaraya Sundeep \n>> ---\n>> default-configs/arm-softmmu.mak | 1 +\n>> hw/arm/Makefile.objs | 1 +\n>> hw/arm/msf2-soc.c | 215 ++++++++++++++++++++++++++++++\n>> ++++++++++\n>> include/hw/arm/msf2-soc.h | 66 ++++++++++++\n>> 4 files changed, 283 insertions(+)\n>> create mode 100644 hw/arm/msf2-soc.c\n>> create mode 100644 include/hw/arm/msf2-soc.h\n>>\n>> diff --git a/default-configs/arm-softmmu.mak\n>> b/default-configs/arm-softmmu.mak\n>> index bbdd3c1..5059d13 100644\n>> --- a/default-configs/arm-softmmu.mak\n>> +++ b/default-configs/arm-softmmu.mak\n>> @@ -129,3 +129,4 @@ CONFIG_ACPI=y\n>> CONFIG_SMBIOS=y\n>> CONFIG_ASPEED_SOC=y\n>> CONFIG_GPIO_KEY=y\n>> +CONFIG_MSF2=y\n>> diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs\n>> index a2e56ec..df36a03 100644\n>> --- a/hw/arm/Makefile.objs\n>> +++ b/hw/arm/Makefile.objs\n>> @@ -19,3 +19,4 @@ obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o\n>> obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o\n>> obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o\n>> obj-$(CONFIG_MPS2) += mps2.o\n>> +obj-$(CONFIG_MSF2) += msf2-soc.o\n>> diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c\n>> new file mode 100644\n>> index 0000000..276eec5\n>> --- /dev/null\n>> +++ b/hw/arm/msf2-soc.c\n>> @@ -0,0 +1,215 @@\n>> +/*\n>> + * SmartFusion2 SoC emulation.\n>> + *\n>> + * Copyright (c) 2017 Subbaraya Sundeep \n>> + *\n>> + * Permission is hereby granted, free of charge, to any person obtaining\n>> a copy\n>> + * of this software and associated documentation files (the \"Software\"),\n>> to deal\n>> + * in the Software without restriction, including without limitation the\n>> rights\n>> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or\n>> sell\n>> + * copies of the Software, and to permit persons to whom the Software is\n>> + * furnished to do so, subject to the following conditions:\n>> + *\n>> + * The above copyright notice and this permission notice shall be\n>> included in\n>> + * all copies or substantial portions of the Software.\n>> + *\n>> + * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n>> EXPRESS OR\n>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n>> MERCHANTABILITY,\n>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT\n>> SHALL\n>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR\n>> OTHER\n>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,\n>> ARISING FROM,\n>> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n>> DEALINGS IN\n>> + * THE SOFTWARE.\n>> + */\n>> +\n>> +#include \"qemu/osdep.h\"\n>> +#include \"qapi/error.h\"\n>> +#include \"qemu-common.h\"\n>> +#include \"hw/arm/arm.h\"\n>> +#include \"exec/address-spaces.h\"\n>> +#include \"hw/char/serial.h\"\n>> +#include \"hw/boards.h\"\n>> +#include \"sysemu/block-backend.h\"\n>> +#include \"qemu/cutils.h\"\n>> +#include \"hw/arm/msf2-soc.h\"\n>> +\n>> +#define MSF2_TIMER_BASE 0x40004000\n>> +#define MSF2_SYSREG_BASE 0x40038000\n>> +\n>> +#define ENVM_BASE_ADDRESS 0x60000000\n>> +\n>> +#define SRAM_BASE_ADDRESS 0x20000000\n>> +\n>> +#define MSF2_ENVM_SIZE (512 * K_BYTE)\n>> +#define MSF2_ESRAM_SIZE (64 * K_BYTE)\n>>\n>\n> Eventually you should name those _SIZE_MAX.\n\n\nI agree and will change to SIZE_MAX\n\n>\n\n\n> I miscorrected you in v4, 64kB is true with SECDED disabled, else the SoC\n> is designed for 80kB. Not a big deal, we can add a \"SECDED not supported\"\n> warning later.\n> Can you add a comment about it?\n\n\nSure will add a comment about it.\n\n>\n>\n> +\n>> +static const uint32_t spi_addr[MSF2_NUM_SPIS] = { 0x40001000 ,\n>> 0x40011000 };\n>> +static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x40000000 ,\n>> 0x40010000 };\n>> +\n>> +static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 };\n>> +static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 };\n>> +static const int timer_irq[MSF2_NUM_TIMERS] = { 14, 15 };\n>> +\n>> +static void m2sxxx_soc_initfn(Object *obj)\n>> +{\n>> + MSF2State *s = MSF2_SOC(obj);\n>> + int i;\n>> +\n>> + object_initialize(&s->armv7m, sizeof(s->armv7m), TYPE_ARMV7M);\n>> + qdev_set_parent_bus(DEVICE(&s->armv7m), sysbus_get_default());\n>> +\n>> + object_initialize(&s->sysreg, sizeof(s->sysreg), TYPE_MSF2_SYSREG);\n>> + qdev_set_parent_bus(DEVICE(&s->sysreg), sysbus_get_default());\n>> +\n>> + object_initialize(&s->timer, sizeof(s->timer), TYPE_MSS_TIMER);\n>> + qdev_set_parent_bus(DEVICE(&s->timer), sysbus_get_default());\n>> +\n>>\n>\n> What about the UARTs?\n>\n> + for (i = 0; i < MSF2_NUM_SPIS; i++) {\n>> + object_initialize(&s->spi[i], sizeof(s->spi[i]),\n>> + TYPE_MSS_SPI);\n>> + qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());\n>> + }\n>> +}\n>> +\n>> +static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)\n>> +{\n>> + MSF2State *s = MSF2_SOC(dev_soc);\n>> + DeviceState *dev, *armv7m;\n>> + SysBusDevice *busdev;\n>> + Error *err = NULL;\n>> + int i;\n>> +\n>> + MemoryRegion *system_memory = get_system_memory();\n>> + MemoryRegion *nvm = g_new(MemoryRegion, 1);\n>> + MemoryRegion *nvm_alias = g_new(MemoryRegion, 1);\n>> + MemoryRegion *sram = g_new(MemoryRegion, 1);\n>> +\n>> + memory_region_init_ram(nvm, NULL, \"MSF2.eNVM\", s->envm_size,\n>> + &error_fatal);\n>>\n>\n> Why do you initialize as RAM? I'd rather use memory_region_init_rom_device()\n> here, so you can boot a dumped eNVM flash.\n\n\nJust followed other SoC(like stm32), booting a dumped eNVM flash? I am not\nclear about this how to do that?\n\n>\n>\n> +\n>> + /*\n>> + * On power-on, the eNVM region 0x60000000 is automatically\n>> + * remapped to the Cortex-M3 processor executable region\n>> + * start address (0x0). We do not support remapping other eNVM,\n>> + * eSRAM and DDR regions by guest(via Sysreg) currently.\n>> + */\n>> + memory_region_init_alias(nvm_alias, NULL, \"MSF2.eNVM.alias\",\n>> + nvm, 0, s->envm_size);\n>> +\n>> + memory_region_set_readonly(nvm, true);\n>> + memory_region_set_readonly(nvm_alias, true);\n>>\n>\n> Hmmm not sure the alias needs this.\n\n\nOnce we change to rom then memory_region_set_readonly will go away.\n\n>\n>\n> +\n>> + memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS, nvm);\n>> + memory_region_add_subregion(system_memory, 0, nvm_alias);\n>> +\n>> + memory_region_init_ram(sram, NULL, \"MSF2.eSRAM\", s->esram_size,\n>> + &error_fatal);\n>> + memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);\n>> +\n>> + armv7m = DEVICE(&s->armv7m);\n>> + qdev_prop_set_uint32(armv7m, \"num-irq\", 81);\n>> + qdev_prop_set_string(armv7m, \"cpu-model\", \"cortex-m3\");\n>> + object_property_set_link(OBJECT(&s->armv7m),\n>> OBJECT(get_system_memory()),\n>> + \"memory\", &error_abort);\n>> + object_property_set_bool(OBJECT(&s->armv7m), true, \"realized\",\n>> &err);\n>> + if (err != NULL) {\n>> + error_propagate(errp, err);\n>> + return;\n>> + }\n>> +\n>> + system_clock_scale = NANOSECONDS_PER_SECOND / s->m3clk;\n>> +\n>> + for (i = 0; i < MSF2_NUM_UARTS; i++) {\n>> + if (serial_hds[i]) {\n>>\n>\n> I think they might be issues if you start QEMU without -serial and then\n> use a firmware polling for an uart, the device won't be mapped and the\n> memory accesses are mostly ignored.\n>\n> I'd rather use:\n>\n> for (i = 0; i < MSF2_NUM_UARTS && i < MAX_SERIAL_PORTS; i++) {\n> static const char *serial[] = {\"serial0\", \"serial1\"};\n>\n> if (!serial_hds[i]) {\n> serial_hds[i] = qemu_chr_new(serial[i], \"null\");\n>\n> }\n>\n\nI agree. I will go through this and change.\n\n>\n> + serial_mm_init(get_system_memory(), uart_addr[i], 2,\n>> + qdev_get_gpio_in(armv7m, uart_irq[i]),\n>> + 115200, serial_hds[i], DEVICE_NATIVE_ENDIAN);\n>> + }\n>> + }\n>> +\n>> + dev = DEVICE(&s->timer);\n>> + /* APB0 clock is the timer input clock */\n>> + qdev_prop_set_uint32(dev, \"clock-frequency\", s->m3clk / s->apb0div);\n>> + object_property_set_bool(OBJECT(&s->timer), true, \"realized\", &err);\n>> + if (err != NULL) {\n>> + error_propagate(errp, err);\n>> + return;\n>> + }\n>> + busdev = SYS_BUS_DEVICE(dev);\n>> + sysbus_mmio_map(busdev, 0, MSF2_TIMER_BASE);\n>> + sysbus_connect_irq(busdev, 0,\n>> + qdev_get_gpio_in(armv7m, timer_irq[0]));\n>> + sysbus_connect_irq(busdev, 1,\n>> + qdev_get_gpio_in(armv7m, timer_irq[1]));\n>> +\n>> + dev = DEVICE(&s->sysreg);\n>> + qdev_prop_set_uint32(dev, \"apb0divisor\", s->apb0div);\n>> + qdev_prop_set_uint32(dev, \"apb1divisor\", s->apb1div);\n>> + object_property_set_bool(OBJECT(&s->sysreg), true, \"realized\",\n>> &err);\n>> + if (err != NULL) {\n>> + error_propagate(errp, err);\n>> + return;\n>> + }\n>> + busdev = SYS_BUS_DEVICE(dev);\n>> + sysbus_mmio_map(busdev, 0, MSF2_SYSREG_BASE);\n>> +\n>> + for (i = 0; i < MSF2_NUM_SPIS; i++) {\n>> + gchar *bus_name = g_strdup_printf(\"spi%d\", i);\n>>\n>\n> move g_strdup_printf() down ...\n>\n> +\n>> + object_property_set_bool(OBJECT(&s->spi[i]), true, \"realized\",\n>> &err);\n>> + if (err != NULL) {\n>> + g_free(bus_name);\n>>\n>\n> so this g_free() is not needed.\n>\n> + error_propagate(errp, err);\n>> + return;\n>> + }\n>> +\n>> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);\n>> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,\n>> + qdev_get_gpio_in(armv7m, spi_irq[i]));\n>> +\n>> + /* Alias controller SPI bus to the SoC itself */\n>>\n>\n> Here:\n> bus_name = g_strdup_printf(\"spi%d\", i);\n\n\nOk will modify.\n\n>\n> + object_property_add_alias(OBJECT(s), bus_name,\n>>\n>> + OBJECT(&s->spi[i]), \"spi\",\n>> + &error_abort);\n>> + g_free(bus_name);\n>> + }\n>> +}\n>> +\n>> +static Property m2sxxx_soc_properties[] = {\n>> + /*\n>> + * part name specifies the type of SmartFusion2 device variant(this\n>> + * property is for information purpose only.\n>> + */\n>> + DEFINE_PROP_STRING(\"part-name\", MSF2State, part_name),\n>> + DEFINE_PROP_UINT64(\"eNVM-size\", MSF2State, envm_size,\n>> MSF2_ENVM_SIZE),\n>> + DEFINE_PROP_UINT64(\"eSRAM-size\", MSF2State, esram_size,\n>> MSF2_ESRAM_SIZE),\n>> + /* Libero GUI shows 100Mhz as default for clocks */\n>> + DEFINE_PROP_UINT32(\"m3clk\", MSF2State, m3clk, 100 * 1000000),\n>> + /* default divisors in Libero GUI */\n>> + DEFINE_PROP_UINT32(\"apb0div\", MSF2State, apb0div, 2),\n>> + DEFINE_PROP_UINT32(\"apb1div\", MSF2State, apb1div, 2),\n>> + DEFINE_PROP_END_OF_LIST(),\n>> +};\n>> +\n>> +static void m2sxxx_soc_class_init(ObjectClass *klass, void *data)\n>> +{\n>> + DeviceClass *dc = DEVICE_CLASS(klass);\n>> +\n>> + dc->realize = m2sxxx_soc_realize;\n>> + dc->props = m2sxxx_soc_properties;\n>> +}\n>> +\n>> +static const TypeInfo m2sxxx_soc_info = {\n>> + .name = TYPE_MSF2_SOC,\n>> + .parent = TYPE_SYS_BUS_DEVICE,\n>> + .instance_size = sizeof(MSF2State),\n>> + .instance_init = m2sxxx_soc_initfn,\n>> + .class_init = m2sxxx_soc_class_init,\n>> +};\n>> +\n>> +static void m2sxxx_soc_types(void)\n>> +{\n>> + type_register_static(&m2sxxx_soc_info);\n>> +}\n>> +\n>> +type_init(m2sxxx_soc_types)\n>> diff --git a/include/hw/arm/msf2-soc.h b/include/hw/arm/msf2-soc.h\n>> new file mode 100644\n>> index 0000000..eb239fa\n>> --- /dev/null\n>> +++ b/include/hw/arm/msf2-soc.h\n>> @@ -0,0 +1,66 @@\n>> +/*\n>> + * Microsemi Smartfusion2 SoC\n>> + *\n>> + * Copyright (c) 2017 Subbaraya Sundeep \n>> + *\n>> + * Permission is hereby granted, free of charge, to any person obtaining\n>> a copy\n>> + * of this software and associated documentation files (the \"Software\"),\n>> to deal\n>> + * in the Software without restriction, including without limitation the\n>> rights\n>> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or\n>> sell\n>> + * copies of the Software, and to permit persons to whom the Software is\n>> + * furnished to do so, subject to the following conditions:\n>> + *\n>> + * The above copyright notice and this permission notice shall be\n>> included in\n>> + * all copies or substantial portions of the Software.\n>> + *\n>> + * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n>> EXPRESS OR\n>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n>> MERCHANTABILITY,\n>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT\n>> SHALL\n>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR\n>> OTHER\n>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,\n>> ARISING FROM,\n>> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n>> DEALINGS IN\n>> + * THE SOFTWARE.\n>> + */\n>> +\n>> +#ifndef HW_ARM_MSF2_SOC_H\n>> +#define HW_ARM_MSF2_SOC_H\n>> +\n>> +#include \"hw/arm/armv7m.h\"\n>> +#include \"hw/timer/mss-timer.h\"\n>> +#include \"hw/misc/msf2-sysreg.h\"\n>> +#include \"hw/ssi/mss-spi.h\"\n>> +\n>> +#define TYPE_MSF2_SOC \"msf2-soc\"\n>> +#define MSF2_SOC(obj) OBJECT_CHECK(MSF2State, (obj), TYPE_MSF2_SOC)\n>> +\n>> +#define MSF2_NUM_SPIS 2\n>> +#define MSF2_NUM_UARTS 2\n>> +\n>> +/*\n>> + * System timer consists of two programmable 32-bit\n>> + * decrementing counters that generate individual interrupts to\n>> + * the Cortex-M3 processor\n>> + */\n>> +#define MSF2_NUM_TIMERS 2\n>> +\n>> +typedef struct MSF2State {\n>> + /*< private >*/\n>> + SysBusDevice parent_obj;\n>> + /*< public >*/\n>> +\n>> + ARMv7MState armv7m;\n>> +\n>> + char *part_name;\n>> + uint64_t envm_size;\n>> + uint64_t esram_size;\n>> +\n>> + uint32_t m3clk;\n>> + uint32_t apb0div;\n>> + uint32_t apb1div;\n>> +\n>> + MSF2SysregState sysreg;\n>> + MSSTimerState timer;\n>> + MSSSpiState spi[MSF2_NUM_SPIS];\n>> +} MSF2State;\n>> +\n>> +#endif\n>>\n>\n> Almost there :)\n>\n> Are you OK to:\n> - register eNVM as ROM\n> - check UARTs?\n>\n\nYeah I will change. Thank you :)\n\nSundeep\n\n\n>\n> Regards,\n>\n> Phil.\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"OaTkboEO\"; dkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xj4Rp6sDrz9sN5\n\tfor ;\n\tWed, 30 Aug 2017 22:23:49 +1000 (AEST)","from localhost ([::1]:50289 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dn226-0007kD-76\n\tfor incoming@patchwork.ozlabs.org; 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charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable","X-Content-Filtered-By":"Mailman/MimeDel 2.1.21","Subject":"Re: [Qemu-devel] [Qemu devel v7 PATCH 4/5] msf2: Add Smartfusion2\n\tSoC","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Peter Maydell , qemu-arm ,\n\tQEMU Developers ,\n\tAlistair Francis ,\n\tPeter Crosthwaite ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1760112,"web_url":"http://patchwork.ozlabs.org/comment/1760112/","msgid":"","list_archive_url":null,"date":"2017-08-30T12:26:12","subject":"Re: [Qemu-devel] [Qemu devel v7 PATCH 4/5] msf2: Add Smartfusion2\n\tSoC","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/people/5111/","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"content":"On 30 August 2017 at 03:45, Philippe Mathieu-Daudé wrote:\n> I think they might be issues if you start QEMU without -serial and then use\n> a firmware polling for an uart, the device won't be mapped and the memory\n> accesses are mostly ignored.\n>\n> I'd rather use:\n>\n> for (i = 0; i < MSF2_NUM_UARTS && i < MAX_SERIAL_PORTS; i++) {\n> static const char *serial[] = {\"serial0\", \"serial1\"};\n>\n> if (!serial_hds[i]) {\n> serial_hds[i] = qemu_chr_new(serial[i], \"null\");\n>\n> }\n>\n>> + serial_mm_init(get_system_memory(), uart_addr[i], 2,\n>> + qdev_get_gpio_in(armv7m, uart_irq[i]),\n>> + 115200, serial_hds[i], DEVICE_NATIVE_ENDIAN);\n>> + }\n>> + }\n\nIt would be better to fix serial_mm_init() to handle having\na NULL chardev pointer, because we already have a lot of\nSoC code that just passes it serial_hds[] regardless.\n\nI'd leave this code as it is and we can fix serial_mm_init\nseparately (somebody pointed out this issue for a xilinx\nboard recently).\n\nthanks\n-- PMM","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"b3hHJWJF\"; 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charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2a00:1450:400c:c0c::236","Subject":"Re: [Qemu-devel] [Qemu devel v7 PATCH 4/5] msf2: Add Smartfusion2\n\tSoC","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Alistair Francis ,\n\tPeter Crosthwaite ,\n\tqemu-arm , QEMU Developers , \n\tSubbaraya Sundeep ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1760231,"web_url":"http://patchwork.ozlabs.org/comment/1760231/","msgid":"<40ca8d07-75e5-e0b3-021e-5abaffd16b78@amsat.org>","list_archive_url":null,"date":"2017-08-30T14:47:07","subject":"Re: [Qemu-devel] [Qemu devel v7 PATCH 4/5] msf2: Add Smartfusion2\n\tSoC","submitter":{"id":70924,"url":"http://patchwork.ozlabs.org/api/people/70924/","name":"Philippe Mathieu-Daudé","email":"f4bug@amsat.org"},"content":"On 08/30/2017 09:26 AM, Peter Maydell wrote:\n> On 30 August 2017 at 03:45, Philippe Mathieu-Daudé wrote:\n>> I think they might be issues if you start QEMU without -serial and then use\n>> a firmware polling for an uart, the device won't be mapped and the memory\n>> accesses are mostly ignored.\n>>\n>> I'd rather use:\n>>\n>> for (i = 0; i < MSF2_NUM_UARTS && i < MAX_SERIAL_PORTS; i++) {\n>> static const char *serial[] = {\"serial0\", \"serial1\"};\n>>\n>> if (!serial_hds[i]) {\n>> serial_hds[i] = qemu_chr_new(serial[i], \"null\");\n>>\n>> }\n>>\n>>> + serial_mm_init(get_system_memory(), uart_addr[i], 2,\n>>> + qdev_get_gpio_in(armv7m, uart_irq[i]),\n>>> + 115200, serial_hds[i], DEVICE_NATIVE_ENDIAN);\n>>> + }\n>>> + }\n> \n> It would be better to fix serial_mm_init() to handle having\n> a NULL chardev pointer, because we already have a lot of\n> SoC code that just passes it serial_hds[] regardless.\n\nclever :)\n\n> I'd leave this code as it is and we can fix serial_mm_init\n> separately (somebody pointed out this issue for a xilinx\n> board recently).\n\nSure.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"rb+gg0a0\"; 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Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"","Content-Type":"text/plain; charset=utf-8; format=flowed","Content-Language":"en-US","Content-Transfer-Encoding":"8bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400d:c0d::242","Subject":"Re: [Qemu-devel] [Qemu devel v7 PATCH 4/5] msf2: Add Smartfusion2\n\tSoC","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Alistair Francis ,\n\tPeter Crosthwaite ,\n\tqemu-arm , QEMU Developers , \n\tSubbaraya Sundeep ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1761366,"web_url":"http://patchwork.ozlabs.org/comment/1761366/","msgid":"","list_archive_url":null,"date":"2017-08-31T23:02:03","subject":"Re: [Qemu-devel] [Qemu devel v7 PATCH 4/5] msf2: Add Smartfusion2\n\tSoC","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/people/64571/","name":"Alistair Francis","email":"alistair23@gmail.com"},"content":"On Wed, Aug 30, 2017 at 7:47 AM, Philippe Mathieu-Daudé wrote:\n> On 08/30/2017 09:26 AM, Peter Maydell wrote:\n>>\n>> On 30 August 2017 at 03:45, Philippe Mathieu-Daudé \n>> wrote:\n>>>\n>>> I think they might be issues if you start QEMU without -serial and then\n>>> use\n>>> a firmware polling for an uart, the device won't be mapped and the memory\n>>> accesses are mostly ignored.\n>>>\n>>> I'd rather use:\n>>>\n>>> for (i = 0; i < MSF2_NUM_UARTS && i < MAX_SERIAL_PORTS; i++) {\n>>> static const char *serial[] = {\"serial0\", \"serial1\"};\n>>>\n>>> if (!serial_hds[i]) {\n>>> serial_hds[i] = qemu_chr_new(serial[i], \"null\");\n>>>\n>>> }\n>>>\n>>>> + serial_mm_init(get_system_memory(), uart_addr[i], 2,\n>>>> + qdev_get_gpio_in(armv7m, uart_irq[i]),\n>>>> + 115200, serial_hds[i],\n>>>> DEVICE_NATIVE_ENDIAN);\n>>>> + }\n>>>> + }\n>>\n>>\n>> It would be better to fix serial_mm_init() to handle having\n>> a NULL chardev pointer, because we already have a lot of\n>> SoC code that just passes it serial_hds[] regardless.\n>\n>\n> clever :)\n>\n>> I'd leave this code as it is and we can fix serial_mm_init\n>> separately (somebody pointed out this issue for a xilinx\n>> board recently).\n\nAh, I'll look into this then.\n\nThanks,\nAlistair\n\n>\n>\n> Sure.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2a00:1450:400c:c0c::243","Subject":"Re: [Qemu-devel] [Qemu devel v7 PATCH 4/5] msf2: Add Smartfusion2\n\tSoC","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Peter Maydell ,\n\tPeter Crosthwaite ,\n\tqemu-arm , QEMU Developers , \n\tSubbaraya Sundeep ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1761378,"web_url":"http://patchwork.ozlabs.org/comment/1761378/","msgid":"","list_archive_url":null,"date":"2017-08-31T23:40:32","subject":"Re: [Qemu-devel] [Qemu devel v7 PATCH 4/5] msf2: Add Smartfusion2\n\tSoC","submitter":{"id":70924,"url":"http://patchwork.ozlabs.org/api/people/70924/","name":"Philippe Mathieu-Daudé","email":"f4bug@amsat.org"},"content":"Hi Alistair,\n\nOn 08/31/2017 08:02 PM, Alistair Francis wrote:\n> On Wed, Aug 30, 2017 at 7:47 AM, Philippe Mathieu-Daudé wrote:\n>> On 08/30/2017 09:26 AM, Peter Maydell wrote:\n>>>\n>>> On 30 August 2017 at 03:45, Philippe Mathieu-Daudé \n>>> wrote:\n>>>>\n>>>> I think they might be issues if you start QEMU without -serial and then\n>>>> use\n>>>> a firmware polling for an uart, the device won't be mapped and the memory\n>>>> accesses are mostly ignored.\n>>>>\n>>>> I'd rather use:\n>>>>\n>>>> for (i = 0; i < MSF2_NUM_UARTS && i < MAX_SERIAL_PORTS; i++) {\n>>>> static const char *serial[] = {\"serial0\", \"serial1\"};\n>>>>\n>>>> if (!serial_hds[i]) {\n>>>> serial_hds[i] = qemu_chr_new(serial[i], \"null\");\n>>>>\n>>>> }\n>>>>\n>>>>> + serial_mm_init(get_system_memory(), uart_addr[i], 2,\n>>>>> + qdev_get_gpio_in(armv7m, uart_irq[i]),\n>>>>> + 115200, serial_hds[i],\n>>>>> DEVICE_NATIVE_ENDIAN);\n>>>>> + }\n>>>>> + }\n>>>\n>>>\n>>> It would be better to fix serial_mm_init() to handle having\n>>> a NULL chardev pointer, because we already have a lot of\n>>> SoC code that just passes it serial_hds[] regardless.\n>>\n>>\n>> clever :)\n>>\n>>> I'd leave this code as it is and we can fix serial_mm_init\n>>> separately (somebody pointed out this issue for a xilinx\n>>> board recently).\n> \n> Ah, I'll look into this then.\n\nI already sent a series to take care of this:\n\nhttp://lists.nongnu.org/archive/html/qemu-devel/2017-08/msg06325.html\n\nI'll respin a v2 shortly.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"","Content-Type":"text/plain; charset=utf-8; format=flowed","Content-Language":"en-US","Content-Transfer-Encoding":"8bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400d:c09::243","Subject":"Re: [Qemu-devel] [Qemu devel v7 PATCH 4/5] msf2: Add Smartfusion2\n\tSoC","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Peter Maydell ,\n\tPeter Crosthwaite ,\n\tqemu-arm , QEMU Developers , \n\tSubbaraya Sundeep ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1761380,"web_url":"http://patchwork.ozlabs.org/comment/1761380/","msgid":"","list_archive_url":null,"date":"2017-08-31T23:43:53","subject":"Re: [Qemu-devel] [Qemu devel v7 PATCH 4/5] msf2: Add Smartfusion2\n\tSoC","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/people/64571/","name":"Alistair Francis","email":"alistair23@gmail.com"},"content":"On Thu, Aug 31, 2017 at 4:40 PM, Philippe Mathieu-Daudé wrote:\n> Hi Alistair,\n>\n>\n> On 08/31/2017 08:02 PM, Alistair Francis wrote:\n>>\n>> On Wed, Aug 30, 2017 at 7:47 AM, Philippe Mathieu-Daudé \n>> wrote:\n>>>\n>>> On 08/30/2017 09:26 AM, Peter Maydell wrote:\n>>>>\n>>>>\n>>>> On 30 August 2017 at 03:45, Philippe Mathieu-Daudé \n>>>> wrote:\n>>>>>\n>>>>>\n>>>>> I think they might be issues if you start QEMU without -serial and then\n>>>>> use\n>>>>> a firmware polling for an uart, the device won't be mapped and the\n>>>>> memory\n>>>>> accesses are mostly ignored.\n>>>>>\n>>>>> I'd rather use:\n>>>>>\n>>>>> for (i = 0; i < MSF2_NUM_UARTS && i < MAX_SERIAL_PORTS; i++) {\n>>>>> static const char *serial[] = {\"serial0\", \"serial1\"};\n>>>>>\n>>>>> if (!serial_hds[i]) {\n>>>>> serial_hds[i] = qemu_chr_new(serial[i], \"null\");\n>>>>>\n>>>>> }\n>>>>>\n>>>>>> + serial_mm_init(get_system_memory(), uart_addr[i], 2,\n>>>>>> + qdev_get_gpio_in(armv7m, uart_irq[i]),\n>>>>>> + 115200, serial_hds[i],\n>>>>>> DEVICE_NATIVE_ENDIAN);\n>>>>>> + }\n>>>>>> + }\n>>>>\n>>>>\n>>>>\n>>>> It would be better to fix serial_mm_init() to handle having\n>>>> a NULL chardev pointer, because we already have a lot of\n>>>> SoC code that just passes it serial_hds[] regardless.\n>>>\n>>>\n>>>\n>>> clever :)\n>>>\n>>>> I'd leave this code as it is and we can fix serial_mm_init\n>>>> separately (somebody pointed out this issue for a xilinx\n>>>> board recently).\n>>\n>>\n>> Ah, I'll look into this then.\n>\n>\n> I already sent a series to take care of this:\n>\n> http://lists.nongnu.org/archive/html/qemu-devel/2017-08/msg06325.html\n\nThat was quick.\n\nCan you CC me on the next version?\n\nThanks,\nAlistair\n\n>\n> I'll respin a v2 shortly.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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