[{"id":1758871,"web_url":"http://patchwork.ozlabs.org/comment/1758871/","msgid":"","list_archive_url":null,"date":"2017-08-28T21:53:55","subject":"Re: [Qemu-devel] [Qemu devel v7 PATCH 1/5] msf2: Add Smartfusion2\n\tSystem timer","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/people/64571/","name":"Alistair Francis","email":"alistair23@gmail.com"},"content":"On Mon, Aug 28, 2017 at 9:37 AM, Subbaraya Sundeep\n wrote:\n> Modelled System Timer in Microsemi's Smartfusion2 Soc.\n> Timer has two 32bit down counters and two interrupts.\n>\n> Signed-off-by: Subbaraya Sundeep \n\nI had already reviewed this patch in v6. As long as you have made all\nof the changes mentioned their you can add my reviewed-by to the next\nversion (as long as there are no other significant changes).\n\nCan you please ensure you do add and keep reviewed-by tags, it's a\npain to have to do it multiple times.\n\nThanks,\nAlistair\n\n> ---\n> hw/timer/Makefile.objs | 1 +\n> hw/timer/mss-timer.c | 289 +++++++++++++++++++++++++++++++++++++++++++\n> include/hw/timer/mss-timer.h | 64 ++++++++++\n> 3 files changed, 354 insertions(+)\n> create mode 100644 hw/timer/mss-timer.c\n> create mode 100644 include/hw/timer/mss-timer.h\n>\n> diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs\n> index 15cce1c..8c19eac 100644\n> --- a/hw/timer/Makefile.objs\n> +++ b/hw/timer/Makefile.objs\n> @@ -42,3 +42,4 @@ common-obj-$(CONFIG_ASPEED_SOC) += aspeed_timer.o\n>\n> common-obj-$(CONFIG_SUN4V_RTC) += sun4v-rtc.o\n> common-obj-$(CONFIG_CMSDK_APB_TIMER) += cmsdk-apb-timer.o\n> +common-obj-$(CONFIG_MSF2) += mss-timer.o\n> diff --git a/hw/timer/mss-timer.c b/hw/timer/mss-timer.c\n> new file mode 100644\n> index 0000000..60f1213\n> --- /dev/null\n> +++ b/hw/timer/mss-timer.c\n> @@ -0,0 +1,289 @@\n> +/*\n> + * Block model of System timer present in\n> + * Microsemi's SmartFusion2 and SmartFusion SoCs.\n> + *\n> + * Copyright (c) 2017 Subbaraya Sundeep .\n> + *\n> + * Permission is hereby granted, free of charge, to any person obtaining a copy\n> + * of this software and associated documentation files (the \"Software\"), to deal\n> + * in the Software without restriction, including without limitation the rights\n> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n> + * copies of the Software, and to permit persons to whom the Software is\n> + * furnished to do so, subject to the following conditions:\n> + *\n> + * The above copyright notice and this permission notice shall be included in\n> + * all copies or substantial portions of the Software.\n> + *\n> + * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n> + * THE SOFTWARE.\n> + */\n> +\n> +#include \"qemu/osdep.h\"\n> +#include \"qemu/main-loop.h\"\n> +#include \"qemu/log.h\"\n> +#include \"hw/timer/mss-timer.h\"\n> +\n> +#ifndef MSS_TIMER_ERR_DEBUG\n> +#define MSS_TIMER_ERR_DEBUG 0\n> +#endif\n> +\n> +#define DB_PRINT_L(lvl, fmt, args...) do { \\\n> + if (MSS_TIMER_ERR_DEBUG >= lvl) { \\\n> + qemu_log(\"%s: \" fmt \"\\n\", __func__, ## args); \\\n> + } \\\n> +} while (0);\n> +\n> +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)\n> +\n> +#define R_TIM_VAL 0\n> +#define R_TIM_LOADVAL 1\n> +#define R_TIM_BGLOADVAL 2\n> +#define R_TIM_CTRL 3\n> +#define R_TIM_RIS 4\n> +#define R_TIM_MIS 5\n> +\n> +#define TIMER_CTRL_ENBL (1 << 0)\n> +#define TIMER_CTRL_ONESHOT (1 << 1)\n> +#define TIMER_CTRL_INTR (1 << 2)\n> +#define TIMER_RIS_ACK (1 << 0)\n> +#define TIMER_RST_CLR (1 << 6)\n> +#define TIMER_MODE (1 << 0)\n> +\n> +static void timer_update_irq(struct Msf2Timer *st)\n> +{\n> + bool isr, ier;\n> +\n> + isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK);\n> + ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR);\n> + qemu_set_irq(st->irq, (ier && isr));\n> +}\n> +\n> +static void timer_update(struct Msf2Timer *st)\n> +{\n> + uint64_t count;\n> +\n> + if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL)) {\n> + ptimer_stop(st->ptimer);\n> + return;\n> + }\n> +\n> + count = st->regs[R_TIM_LOADVAL];\n> + ptimer_set_limit(st->ptimer, count, 1);\n> + ptimer_run(st->ptimer, 1);\n> +}\n> +\n> +static uint64_t\n> +timer_read(void *opaque, hwaddr offset, unsigned int size)\n> +{\n> + MSSTimerState *t = opaque;\n> + hwaddr addr;\n> + struct Msf2Timer *st;\n> + uint32_t ret = 0;\n> + int timer = 0;\n> + int isr;\n> + int ier;\n> +\n> + addr = offset >> 2;\n> + /*\n> + * Two independent timers has same base address.\n> + * Based on address passed figure out which timer is being used.\n> + */\n> + if ((addr >= R_TIM1_MAX) && (addr < NUM_TIMERS * R_TIM1_MAX)) {\n> + timer = 1;\n> + addr -= R_TIM1_MAX;\n> + }\n> +\n> + st = &t->timers[timer];\n> +\n> + switch (addr) {\n> + case R_TIM_VAL:\n> + ret = ptimer_get_count(st->ptimer);\n> + break;\n> +\n> + case R_TIM_MIS:\n> + isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK);\n> + ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR);\n> + ret = ier & isr;\n> + break;\n> +\n> + default:\n> + if (addr < R_TIM1_MAX) {\n> + ret = st->regs[addr];\n> + } else {\n> + qemu_log_mask(LOG_GUEST_ERROR,\n> + TYPE_MSS_TIMER\": 64-bit mode not supported\\n\");\n> + return ret;\n> + }\n> + break;\n> + }\n> +\n> + DB_PRINT(\"timer=%d 0x%\" HWADDR_PRIx \"=0x%\" PRIx32, timer, offset,\n> + ret);\n> + return ret;\n> +}\n> +\n> +static void\n> +timer_write(void *opaque, hwaddr offset,\n> + uint64_t val64, unsigned int size)\n> +{\n> + MSSTimerState *t = opaque;\n> + hwaddr addr;\n> + struct Msf2Timer *st;\n> + int timer = 0;\n> + uint32_t value = val64;\n> +\n> + addr = offset >> 2;\n> + /*\n> + * Two independent timers has same base address.\n> + * Based on addr passed figure out which timer is being used.\n> + */\n> + if ((addr >= R_TIM1_MAX) && (addr < NUM_TIMERS * R_TIM1_MAX)) {\n> + timer = 1;\n> + addr -= R_TIM1_MAX;\n> + }\n> +\n> + st = &t->timers[timer];\n> +\n> + DB_PRINT(\"addr=0x%\" HWADDR_PRIx \" val=0x%\" PRIx32 \" (timer=%d)\", offset,\n> + value, timer);\n> +\n> + switch (addr) {\n> + case R_TIM_CTRL:\n> + st->regs[R_TIM_CTRL] = value;\n> + timer_update(st);\n> + break;\n> +\n> + case R_TIM_RIS:\n> + if (value & TIMER_RIS_ACK) {\n> + st->regs[R_TIM_RIS] &= ~TIMER_RIS_ACK;\n> + }\n> + break;\n> +\n> + case R_TIM_LOADVAL:\n> + st->regs[R_TIM_LOADVAL] = value;\n> + if (st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL) {\n> + timer_update(st);\n> + }\n> + break;\n> +\n> + case R_TIM_BGLOADVAL:\n> + st->regs[R_TIM_BGLOADVAL] = value;\n> + st->regs[R_TIM_LOADVAL] = value;\n> + break;\n> +\n> + case R_TIM_VAL:\n> + case R_TIM_MIS:\n> + break;\n> +\n> + default:\n> + if (addr < R_TIM1_MAX) {\n> + st->regs[addr] = value;\n> + } else {\n> + qemu_log_mask(LOG_GUEST_ERROR,\n> + TYPE_MSS_TIMER\": 64-bit mode not supported\\n\");\n> + return;\n> + }\n> + break;\n> + }\n> + timer_update_irq(st);\n> +}\n> +\n> +static const MemoryRegionOps timer_ops = {\n> + .read = timer_read,\n> + .write = timer_write,\n> + .endianness = DEVICE_NATIVE_ENDIAN,\n> + .valid = {\n> + .min_access_size = 1,\n> + .max_access_size = 4\n> + }\n> +};\n> +\n> +static void timer_hit(void *opaque)\n> +{\n> + struct Msf2Timer *st = opaque;\n> +\n> + st->regs[R_TIM_RIS] |= TIMER_RIS_ACK;\n> +\n> + if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ONESHOT)) {\n> + timer_update(st);\n> + }\n> + timer_update_irq(st);\n> +}\n> +\n> +static void mss_timer_init(Object *obj)\n> +{\n> + MSSTimerState *t = MSS_TIMER(obj);\n> + int i;\n> +\n> + /* Init all the ptimers. */\n> + for (i = 0; i < NUM_TIMERS; i++) {\n> + struct Msf2Timer *st = &t->timers[i];\n> +\n> + st->bh = qemu_bh_new(timer_hit, st);\n> + st->ptimer = ptimer_init(st->bh, PTIMER_POLICY_DEFAULT);\n> + ptimer_set_freq(st->ptimer, t->freq_hz);\n> + sysbus_init_irq(SYS_BUS_DEVICE(obj), &st->irq);\n> + }\n> +\n> + memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, TYPE_MSS_TIMER,\n> + NUM_TIMERS * R_TIM1_MAX * 4);\n> + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &t->mmio);\n> +}\n> +\n> +static const VMStateDescription vmstate_timers = {\n> + .name = \"mss-timer-block\",\n> + .version_id = 1,\n> + .minimum_version_id = 1,\n> + .fields = (VMStateField[]) {\n> + VMSTATE_PTIMER(ptimer, struct Msf2Timer),\n> + VMSTATE_UINT32_ARRAY(regs, struct Msf2Timer, R_TIM1_MAX),\n> + VMSTATE_END_OF_LIST()\n> + }\n> +};\n> +\n> +static const VMStateDescription vmstate_mss_timer = {\n> + .name = TYPE_MSS_TIMER,\n> + .version_id = 1,\n> + .minimum_version_id = 1,\n> + .fields = (VMStateField[]) {\n> + VMSTATE_UINT32(freq_hz, MSSTimerState),\n> + VMSTATE_STRUCT_ARRAY(timers, MSSTimerState, NUM_TIMERS, 0,\n> + vmstate_timers, struct Msf2Timer),\n> + VMSTATE_END_OF_LIST()\n> + }\n> +};\n> +\n> +static Property mss_timer_properties[] = {\n> + /* Libero GUI shows 100Mhz as default for clocks */\n> + DEFINE_PROP_UINT32(\"clock-frequency\", MSSTimerState, freq_hz,\n> + 100 * 1000000),\n> + DEFINE_PROP_END_OF_LIST(),\n> +};\n> +\n> +static void mss_timer_class_init(ObjectClass *klass, void *data)\n> +{\n> + DeviceClass *dc = DEVICE_CLASS(klass);\n> +\n> + dc->props = mss_timer_properties;\n> + dc->vmsd = &vmstate_mss_timer;\n> +}\n> +\n> +static const TypeInfo mss_timer_info = {\n> + .name = TYPE_MSS_TIMER,\n> + .parent = TYPE_SYS_BUS_DEVICE,\n> + .instance_size = sizeof(MSSTimerState),\n> + .instance_init = mss_timer_init,\n> + .class_init = mss_timer_class_init,\n> +};\n> +\n> +static void mss_timer_register_types(void)\n> +{\n> + type_register_static(&mss_timer_info);\n> +}\n> +\n> +type_init(mss_timer_register_types)\n> diff --git a/include/hw/timer/mss-timer.h b/include/hw/timer/mss-timer.h\n> new file mode 100644\n> index 0000000..d15d173\n> --- /dev/null\n> +++ b/include/hw/timer/mss-timer.h\n> @@ -0,0 +1,64 @@\n> +/*\n> + * Microsemi SmartFusion2 Timer.\n> + *\n> + * Copyright (c) 2017 Subbaraya Sundeep \n> + *\n> + * Permission is hereby granted, free of charge, to any person obtaining a copy\n> + * of this software and associated documentation files (the \"Software\"), to deal\n> + * in the Software without restriction, including without limitation the rights\n> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n> + * copies of the Software, and to permit persons to whom the Software is\n> + * furnished to do so, subject to the following conditions:\n> + *\n> + * The above copyright notice and this permission notice shall be included in\n> + * all copies or substantial portions of the Software.\n> + *\n> + * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n> + * THE SOFTWARE.\n> + */\n> +\n> +#ifndef HW_MSS_TIMER_H\n> +#define HW_MSS_TIMER_H\n> +\n> +#include \"hw/sysbus.h\"\n> +#include \"hw/ptimer.h\"\n> +\n> +#define TYPE_MSS_TIMER \"mss-timer\"\n> +#define MSS_TIMER(obj) OBJECT_CHECK(MSSTimerState, \\\n> + (obj), TYPE_MSS_TIMER)\n> +\n> +/*\n> + * There are two 32-bit down counting timers.\n> + * Timers 1 and 2 can be concatenated into a single 64-bit Timer\n> + * that operates either in Periodic mode or in One-shot mode.\n> + * Writing 1 to the TIM64_MODE register bit 0 sets the Timers in 64-bit mode.\n> + * In 64-bit mode, writing to the 32-bit registers has no effect.\n> + * Similarly, in 32-bit mode, writing to the 64-bit mode registers\n> + * has no effect. Only two 32-bit timers are supported currently.\n> + */\n> +#define NUM_TIMERS 2\n> +\n> +#define R_TIM1_MAX 6\n> +\n> +struct Msf2Timer {\n> + QEMUBH *bh;\n> + ptimer_state *ptimer;\n> +\n> + uint32_t regs[R_TIM1_MAX];\n> + qemu_irq irq;\n> +};\n> +\n> +typedef struct MSSTimerState {\n> + SysBusDevice parent_obj;\n> +\n> + MemoryRegion mmio;\n> + uint32_t freq_hz;\n> + struct Msf2Timer timers[NUM_TIMERS];\n> +} MSSTimerState;\n> +\n> +#endif /* HW_MSS_TIMER_H */\n> --\n> 2.5.0\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"Xa3LSXdJ\"; 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\n\tMon, 28 Aug 2017 14:54:25 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"<1503938283-12404-2-git-send-email-sundeep.lkml@gmail.com>","References":"<1503938283-12404-1-git-send-email-sundeep.lkml@gmail.com>\n\t<1503938283-12404-2-git-send-email-sundeep.lkml@gmail.com>","From":"Alistair Francis ","Date":"Mon, 28 Aug 2017 14:53:55 -0700","Message-ID":"","To":"Subbaraya Sundeep ","Content-Type":"text/plain; charset=\"UTF-8\"","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2a00:1450:400c:c0c::241","Subject":"Re: [Qemu-devel] [Qemu devel v7 PATCH 1/5] msf2: Add Smartfusion2\n\tSystem timer","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Peter Maydell , =?utf-8?q?Philippe_Mathieu-D?=\n\t=?utf-8?b?YXVkw6k=?= , \tqemu-arm ,\n\t\"qemu-devel@nongnu.org Developers\" , \n\tPeter Crosthwaite ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1759040,"web_url":"http://patchwork.ozlabs.org/comment/1759040/","msgid":"","list_archive_url":null,"date":"2017-08-29T05:32:26","subject":"Re: [Qemu-devel] [Qemu devel v7 PATCH 1/5] msf2: Add Smartfusion2\n\tSystem timer","submitter":{"id":64324,"url":"http://patchwork.ozlabs.org/api/people/64324/","name":"sundeep subbaraya","email":"sundeep.lkml@gmail.com"},"content":"Hi Alistair,\n\nOn Tue, Aug 29, 2017 at 3:23 AM, Alistair Francis \nwrote:\n\n> On Mon, Aug 28, 2017 at 9:37 AM, Subbaraya Sundeep\n> wrote:\n> > Modelled System Timer in Microsemi's Smartfusion2 Soc.\n> > Timer has two 32bit down counters and two interrupts.\n> >\n> > Signed-off-by: Subbaraya Sundeep \n>\n> I had already reviewed this patch in v6. As long as you have made all\n> of the changes mentioned their you can add my reviewed-by to the next\n> version (as long as there are no other significant changes).\n>\n> Can you please ensure you do add and keep reviewed-by tags, it's a\n> pain to have to do it multiple times.\n>\n\nSorry I was not aware that I can add reviewed by tag myself and send.\nI will add your reviewed by since I fixed all your comments.\nDo I need to send another version v8 with your Reviewed-by ?\n\nThanks,\nSundeep\n\n\n>\n> Thanks,\n> Alistair\n>\n> > ---\n> > hw/timer/Makefile.objs | 1 +\n> > hw/timer/mss-timer.c | 289 ++++++++++++++++++++++++++++++\n> +++++++++++++\n> > include/hw/timer/mss-timer.h | 64 ++++++++++\n> > 3 files changed, 354 insertions(+)\n> > create mode 100644 hw/timer/mss-timer.c\n> > create mode 100644 include/hw/timer/mss-timer.h\n> >\n> > diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs\n> > index 15cce1c..8c19eac 100644\n> > --- a/hw/timer/Makefile.objs\n> > +++ b/hw/timer/Makefile.objs\n> > @@ -42,3 +42,4 @@ common-obj-$(CONFIG_ASPEED_SOC) += aspeed_timer.o\n> >\n> > common-obj-$(CONFIG_SUN4V_RTC) += sun4v-rtc.o\n> > common-obj-$(CONFIG_CMSDK_APB_TIMER) += cmsdk-apb-timer.o\n> > +common-obj-$(CONFIG_MSF2) += mss-timer.o\n> > diff --git a/hw/timer/mss-timer.c b/hw/timer/mss-timer.c\n> > new file mode 100644\n> > index 0000000..60f1213\n> > --- /dev/null\n> > +++ b/hw/timer/mss-timer.c\n> > @@ -0,0 +1,289 @@\n> > +/*\n> > + * Block model of System timer present in\n> > + * Microsemi's SmartFusion2 and SmartFusion SoCs.\n> > + *\n> > + * Copyright (c) 2017 Subbaraya Sundeep .\n> > + *\n> > + * Permission is hereby granted, free of charge, to any person\n> obtaining a copy\n> > + * of this software and associated documentation files (the\n> \"Software\"), to deal\n> > + * in the Software without restriction, including without limitation\n> the rights\n> > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or\n> sell\n> > + * copies of the Software, and to permit persons to whom the Software is\n> > + * furnished to do so, subject to the following conditions:\n> > + *\n> > + * The above copyright notice and this permission notice shall be\n> included in\n> > + * all copies or substantial portions of the Software.\n> > + *\n> > + * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n> EXPRESS OR\n> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n> MERCHANTABILITY,\n> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT\n> SHALL\n> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR\n> OTHER\n> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,\n> ARISING FROM,\n> > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n> DEALINGS IN\n> > + * THE SOFTWARE.\n> > + */\n> > +\n> > +#include \"qemu/osdep.h\"\n> > +#include \"qemu/main-loop.h\"\n> > +#include \"qemu/log.h\"\n> > +#include \"hw/timer/mss-timer.h\"\n> > +\n> > +#ifndef MSS_TIMER_ERR_DEBUG\n> > +#define MSS_TIMER_ERR_DEBUG 0\n> > +#endif\n> > +\n> > +#define DB_PRINT_L(lvl, fmt, args...) do { \\\n> > + if (MSS_TIMER_ERR_DEBUG >= lvl) { \\\n> > + qemu_log(\"%s: \" fmt \"\\n\", __func__, ## args); \\\n> > + } \\\n> > +} while (0);\n> > +\n> > +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)\n> > +\n> > +#define R_TIM_VAL 0\n> > +#define R_TIM_LOADVAL 1\n> > +#define R_TIM_BGLOADVAL 2\n> > +#define R_TIM_CTRL 3\n> > +#define R_TIM_RIS 4\n> > +#define R_TIM_MIS 5\n> > +\n> > +#define TIMER_CTRL_ENBL (1 << 0)\n> > +#define TIMER_CTRL_ONESHOT (1 << 1)\n> > +#define TIMER_CTRL_INTR (1 << 2)\n> > +#define TIMER_RIS_ACK (1 << 0)\n> > +#define TIMER_RST_CLR (1 << 6)\n> > +#define TIMER_MODE (1 << 0)\n> > +\n> > +static void timer_update_irq(struct Msf2Timer *st)\n> > +{\n> > + bool isr, ier;\n> > +\n> > + isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK);\n> > + ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR);\n> > + qemu_set_irq(st->irq, (ier && isr));\n> > +}\n> > +\n> > +static void timer_update(struct Msf2Timer *st)\n> > +{\n> > + uint64_t count;\n> > +\n> > + if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL)) {\n> > + ptimer_stop(st->ptimer);\n> > + return;\n> > + }\n> > +\n> > + count = st->regs[R_TIM_LOADVAL];\n> > + ptimer_set_limit(st->ptimer, count, 1);\n> > + ptimer_run(st->ptimer, 1);\n> > +}\n> > +\n> > +static uint64_t\n> > +timer_read(void *opaque, hwaddr offset, unsigned int size)\n> > +{\n> > + MSSTimerState *t = opaque;\n> > + hwaddr addr;\n> > + struct Msf2Timer *st;\n> > + uint32_t ret = 0;\n> > + int timer = 0;\n> > + int isr;\n> > + int ier;\n> > +\n> > + addr = offset >> 2;\n> > + /*\n> > + * Two independent timers has same base address.\n> > + * Based on address passed figure out which timer is being used.\n> > + */\n> > + if ((addr >= R_TIM1_MAX) && (addr < NUM_TIMERS * R_TIM1_MAX)) {\n> > + timer = 1;\n> > + addr -= R_TIM1_MAX;\n> > + }\n> > +\n> > + st = &t->timers[timer];\n> > +\n> > + switch (addr) {\n> > + case R_TIM_VAL:\n> > + ret = ptimer_get_count(st->ptimer);\n> > + break;\n> > +\n> > + case R_TIM_MIS:\n> > + isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK);\n> > + ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR);\n> > + ret = ier & isr;\n> > + break;\n> > +\n> > + default:\n> > + if (addr < R_TIM1_MAX) {\n> > + ret = st->regs[addr];\n> > + } else {\n> > + qemu_log_mask(LOG_GUEST_ERROR,\n> > + TYPE_MSS_TIMER\": 64-bit mode not supported\\n\");\n> > + return ret;\n> > + }\n> > + break;\n> > + }\n> > +\n> > + DB_PRINT(\"timer=%d 0x%\" HWADDR_PRIx \"=0x%\" PRIx32, timer, offset,\n> > + ret);\n> > + return ret;\n> > +}\n> > +\n> > +static void\n> > +timer_write(void *opaque, hwaddr offset,\n> > + uint64_t val64, unsigned int size)\n> > +{\n> > + MSSTimerState *t = opaque;\n> > + hwaddr addr;\n> > + struct Msf2Timer *st;\n> > + int timer = 0;\n> > + uint32_t value = val64;\n> > +\n> > + addr = offset >> 2;\n> > + /*\n> > + * Two independent timers has same base address.\n> > + * Based on addr passed figure out which timer is being used.\n> > + */\n> > + if ((addr >= R_TIM1_MAX) && (addr < NUM_TIMERS * R_TIM1_MAX)) {\n> > + timer = 1;\n> > + addr -= R_TIM1_MAX;\n> > + }\n> > +\n> > + st = &t->timers[timer];\n> > +\n> > + DB_PRINT(\"addr=0x%\" HWADDR_PRIx \" val=0x%\" PRIx32 \" (timer=%d)\",\n> offset,\n> > + value, timer);\n> > +\n> > + switch (addr) {\n> > + case R_TIM_CTRL:\n> > + st->regs[R_TIM_CTRL] = value;\n> > + timer_update(st);\n> > + break;\n> > +\n> > + case R_TIM_RIS:\n> > + if (value & TIMER_RIS_ACK) {\n> > + st->regs[R_TIM_RIS] &= ~TIMER_RIS_ACK;\n> > + }\n> > + break;\n> > +\n> > + case R_TIM_LOADVAL:\n> > + st->regs[R_TIM_LOADVAL] = value;\n> > + if (st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL) {\n> > + timer_update(st);\n> > + }\n> > + break;\n> > +\n> > + case R_TIM_BGLOADVAL:\n> > + st->regs[R_TIM_BGLOADVAL] = value;\n> > + st->regs[R_TIM_LOADVAL] = value;\n> > + break;\n> > +\n> > + case R_TIM_VAL:\n> > + case R_TIM_MIS:\n> > + break;\n> > +\n> > + default:\n> > + if (addr < R_TIM1_MAX) {\n> > + st->regs[addr] = value;\n> > + } else {\n> > + qemu_log_mask(LOG_GUEST_ERROR,\n> > + TYPE_MSS_TIMER\": 64-bit mode not supported\\n\");\n> > + return;\n> > + }\n> > + break;\n> > + }\n> > + timer_update_irq(st);\n> > +}\n> > +\n> > +static const MemoryRegionOps timer_ops = {\n> > + .read = timer_read,\n> > + .write = timer_write,\n> > + .endianness = DEVICE_NATIVE_ENDIAN,\n> > + .valid = {\n> > + .min_access_size = 1,\n> > + .max_access_size = 4\n> > + }\n> > +};\n> > +\n> > +static void timer_hit(void *opaque)\n> > +{\n> > + struct Msf2Timer *st = opaque;\n> > +\n> > + st->regs[R_TIM_RIS] |= TIMER_RIS_ACK;\n> > +\n> > + if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ONESHOT)) {\n> > + timer_update(st);\n> > + }\n> > + timer_update_irq(st);\n> > +}\n> > +\n> > +static void mss_timer_init(Object *obj)\n> > +{\n> > + MSSTimerState *t = MSS_TIMER(obj);\n> > + int i;\n> > +\n> > + /* Init all the ptimers. */\n> > + for (i = 0; i < NUM_TIMERS; i++) {\n> > + struct Msf2Timer *st = &t->timers[i];\n> > +\n> > + st->bh = qemu_bh_new(timer_hit, st);\n> > + st->ptimer = ptimer_init(st->bh, PTIMER_POLICY_DEFAULT);\n> > + ptimer_set_freq(st->ptimer, t->freq_hz);\n> > + sysbus_init_irq(SYS_BUS_DEVICE(obj), &st->irq);\n> > + }\n> > +\n> > + memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t,\n> TYPE_MSS_TIMER,\n> > + NUM_TIMERS * R_TIM1_MAX * 4);\n> > + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &t->mmio);\n> > +}\n> > +\n> > +static const VMStateDescription vmstate_timers = {\n> > + .name = \"mss-timer-block\",\n> > + .version_id = 1,\n> > + .minimum_version_id = 1,\n> > + .fields = (VMStateField[]) {\n> > + VMSTATE_PTIMER(ptimer, struct Msf2Timer),\n> > + VMSTATE_UINT32_ARRAY(regs, struct Msf2Timer, R_TIM1_MAX),\n> > + VMSTATE_END_OF_LIST()\n> > + }\n> > +};\n> > +\n> > +static const VMStateDescription vmstate_mss_timer = {\n> > + .name = TYPE_MSS_TIMER,\n> > + .version_id = 1,\n> > + .minimum_version_id = 1,\n> > + .fields = (VMStateField[]) {\n> > + VMSTATE_UINT32(freq_hz, MSSTimerState),\n> > + VMSTATE_STRUCT_ARRAY(timers, MSSTimerState, NUM_TIMERS, 0,\n> > + vmstate_timers, struct Msf2Timer),\n> > + VMSTATE_END_OF_LIST()\n> > + }\n> > +};\n> > +\n> > +static Property mss_timer_properties[] = {\n> > + /* Libero GUI shows 100Mhz as default for clocks */\n> > + DEFINE_PROP_UINT32(\"clock-frequency\", MSSTimerState, freq_hz,\n> > + 100 * 1000000),\n> > + DEFINE_PROP_END_OF_LIST(),\n> > +};\n> > +\n> > +static void mss_timer_class_init(ObjectClass *klass, void *data)\n> > +{\n> > + DeviceClass *dc = DEVICE_CLASS(klass);\n> > +\n> > + dc->props = mss_timer_properties;\n> > + dc->vmsd = &vmstate_mss_timer;\n> > +}\n> > +\n> > +static const TypeInfo mss_timer_info = {\n> > + .name = TYPE_MSS_TIMER,\n> > + .parent = TYPE_SYS_BUS_DEVICE,\n> > + .instance_size = sizeof(MSSTimerState),\n> > + .instance_init = mss_timer_init,\n> > + .class_init = mss_timer_class_init,\n> > +};\n> > +\n> > +static void mss_timer_register_types(void)\n> > +{\n> > + type_register_static(&mss_timer_info);\n> > +}\n> > +\n> > +type_init(mss_timer_register_types)\n> > diff --git a/include/hw/timer/mss-timer.h b/include/hw/timer/mss-timer.h\n> > new file mode 100644\n> > index 0000000..d15d173\n> > --- /dev/null\n> > +++ b/include/hw/timer/mss-timer.h\n> > @@ -0,0 +1,64 @@\n> > +/*\n> > + * Microsemi SmartFusion2 Timer.\n> > + *\n> > + * Copyright (c) 2017 Subbaraya Sundeep \n> > + *\n> > + * Permission is hereby granted, free of charge, to any person\n> obtaining a copy\n> > + * of this software and associated documentation files (the\n> \"Software\"), to deal\n> > + * in the Software without restriction, including without limitation\n> the rights\n> > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or\n> sell\n> > + * copies of the Software, and to permit persons to whom the Software is\n> > + * furnished to do so, subject to the following conditions:\n> > + *\n> > + * The above copyright notice and this permission notice shall be\n> included in\n> > + * all copies or substantial portions of the Software.\n> > + *\n> > + * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n> EXPRESS OR\n> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n> MERCHANTABILITY,\n> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT\n> SHALL\n> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR\n> OTHER\n> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,\n> ARISING FROM,\n> > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n> DEALINGS IN\n> > + * THE SOFTWARE.\n> > + */\n> > +\n> > +#ifndef HW_MSS_TIMER_H\n> > +#define HW_MSS_TIMER_H\n> > +\n> > +#include \"hw/sysbus.h\"\n> > +#include \"hw/ptimer.h\"\n> > +\n> > +#define TYPE_MSS_TIMER \"mss-timer\"\n> > +#define MSS_TIMER(obj) OBJECT_CHECK(MSSTimerState, \\\n> > + (obj), TYPE_MSS_TIMER)\n> > +\n> > +/*\n> > + * There are two 32-bit down counting timers.\n> > + * Timers 1 and 2 can be concatenated into a single 64-bit Timer\n> > + * that operates either in Periodic mode or in One-shot mode.\n> > + * Writing 1 to the TIM64_MODE register bit 0 sets the Timers in 64-bit\n> mode.\n> > + * In 64-bit mode, writing to the 32-bit registers has no effect.\n> > + * Similarly, in 32-bit mode, writing to the 64-bit mode registers\n> > + * has no effect. Only two 32-bit timers are supported currently.\n> > + */\n> > +#define NUM_TIMERS 2\n> > +\n> > +#define R_TIM1_MAX 6\n> > +\n> > +struct Msf2Timer {\n> > + QEMUBH *bh;\n> > + ptimer_state *ptimer;\n> > +\n> > + uint32_t regs[R_TIM1_MAX];\n> > + qemu_irq irq;\n> > +};\n> > +\n> > +typedef struct MSSTimerState {\n> > + SysBusDevice parent_obj;\n> > +\n> > + MemoryRegion mmio;\n> > + uint32_t freq_hz;\n> > + struct Msf2Timer timers[NUM_TIMERS];\n> > +} MSSTimerState;\n> > +\n> > +#endif /* HW_MSS_TIMER_H */\n> > --\n> > 2.5.0\n> >\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"TT6NbNFl\"; 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\n\tMon, 28 Aug 2017 22:32:26 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"","References":"<1503938283-12404-1-git-send-email-sundeep.lkml@gmail.com>\n\t<1503938283-12404-2-git-send-email-sundeep.lkml@gmail.com>\n\t","From":"sundeep subbaraya ","Date":"Tue, 29 Aug 2017 11:02:26 +0530","Message-ID":"","To":"Alistair Francis ","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400c:c08::243","Content-Type":"text/plain; charset=\"UTF-8\"","X-Content-Filtered-By":"Mailman/MimeDel 2.1.21","Subject":"Re: [Qemu-devel] [Qemu devel v7 PATCH 1/5] msf2: Add Smartfusion2\n\tSystem timer","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Peter Maydell , =?utf-8?q?Philippe_Mathieu-D?=\n\t=?utf-8?b?YXVkw6k=?= , \tqemu-arm ,\n\t\"qemu-devel@nongnu.org Developers\" , \n\tPeter Crosthwaite ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1759729,"web_url":"http://patchwork.ozlabs.org/comment/1759729/","msgid":"","list_archive_url":null,"date":"2017-08-29T21:58:12","subject":"Re: [Qemu-devel] [Qemu devel v7 PATCH 1/5] msf2: Add Smartfusion2\n\tSystem timer","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/people/64571/","name":"Alistair Francis","email":"alistair23@gmail.com"},"content":"On Mon, Aug 28, 2017 at 10:32 PM, sundeep subbaraya\n wrote:\n> Hi Alistair,\n>\n> On Tue, Aug 29, 2017 at 3:23 AM, Alistair Francis \n> wrote:\n>>\n>> On Mon, Aug 28, 2017 at 9:37 AM, Subbaraya Sundeep\n>> wrote:\n>> > Modelled System Timer in Microsemi's Smartfusion2 Soc.\n>> > Timer has two 32bit down counters and two interrupts.\n>> >\n>> > Signed-off-by: Subbaraya Sundeep \n>>\n>> I had already reviewed this patch in v6. As long as you have made all\n>> of the changes mentioned their you can add my reviewed-by to the next\n>> version (as long as there are no other significant changes).\n>>\n>> Can you please ensure you do add and keep reviewed-by tags, it's a\n>> pain to have to do it multiple times.\n>\n>\n> Sorry I was not aware that I can add reviewed by tag myself and send.\n\nYou can't just add them, but if someone has reviewded your patch you\nshould keep it on that patch.\n\n> I will add your reviewed by since I fixed all your comments.\n> Do I need to send another version v8 with your Reviewed-by ?\n\nNo it's ok. I'll have a look at the other patches. When you do send a\nnew version just include them then.\n\nThanks,\nAlistair\n\n>\n> Thanks,\n> Sundeep\n>\n>>\n>>\n>> Thanks,\n>> Alistair\n>>\n>> > ---\n>> > hw/timer/Makefile.objs | 1 +\n>> > hw/timer/mss-timer.c | 289\n>> > +++++++++++++++++++++++++++++++++++++++++++\n>> > include/hw/timer/mss-timer.h | 64 ++++++++++\n>> > 3 files changed, 354 insertions(+)\n>> > create mode 100644 hw/timer/mss-timer.c\n>> > create mode 100644 include/hw/timer/mss-timer.h\n>> >\n>> > diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs\n>> > index 15cce1c..8c19eac 100644\n>> > --- a/hw/timer/Makefile.objs\n>> > +++ b/hw/timer/Makefile.objs\n>> > @@ -42,3 +42,4 @@ common-obj-$(CONFIG_ASPEED_SOC) += aspeed_timer.o\n>> >\n>> > common-obj-$(CONFIG_SUN4V_RTC) += sun4v-rtc.o\n>> > common-obj-$(CONFIG_CMSDK_APB_TIMER) += cmsdk-apb-timer.o\n>> > +common-obj-$(CONFIG_MSF2) += mss-timer.o\n>> > diff --git a/hw/timer/mss-timer.c b/hw/timer/mss-timer.c\n>> > new file mode 100644\n>> > index 0000000..60f1213\n>> > --- /dev/null\n>> > +++ b/hw/timer/mss-timer.c\n>> > @@ -0,0 +1,289 @@\n>> > +/*\n>> > + * Block model of System timer present in\n>> > + * Microsemi's SmartFusion2 and SmartFusion SoCs.\n>> > + *\n>> > + * Copyright (c) 2017 Subbaraya Sundeep .\n>> > + *\n>> > + * Permission is hereby granted, free of charge, to any person\n>> > obtaining a copy\n>> > + * of this software and associated documentation files (the\n>> > \"Software\"), to deal\n>> > + * in the Software without restriction, including without limitation\n>> > the rights\n>> > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or\n>> > sell\n>> > + * copies of the Software, and to permit persons to whom the Software\n>> > is\n>> > + * furnished to do so, subject to the following conditions:\n>> > + *\n>> > + * The above copyright notice and this permission notice shall be\n>> > included in\n>> > + * all copies or substantial portions of the Software.\n>> > + *\n>> > + * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n>> > EXPRESS OR\n>> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n>> > MERCHANTABILITY,\n>> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT\n>> > SHALL\n>> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR\n>> > OTHER\n>> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,\n>> > ARISING FROM,\n>> > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n>> > DEALINGS IN\n>> > + * THE SOFTWARE.\n>> > + */\n>> > +\n>> > +#include \"qemu/osdep.h\"\n>> > +#include \"qemu/main-loop.h\"\n>> > +#include \"qemu/log.h\"\n>> > +#include \"hw/timer/mss-timer.h\"\n>> > +\n>> > +#ifndef MSS_TIMER_ERR_DEBUG\n>> > +#define MSS_TIMER_ERR_DEBUG 0\n>> > +#endif\n>> > +\n>> > +#define DB_PRINT_L(lvl, fmt, args...) do { \\\n>> > + if (MSS_TIMER_ERR_DEBUG >= lvl) { \\\n>> > + qemu_log(\"%s: \" fmt \"\\n\", __func__, ## args); \\\n>> > + } \\\n>> > +} while (0);\n>> > +\n>> > +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)\n>> > +\n>> > +#define R_TIM_VAL 0\n>> > +#define R_TIM_LOADVAL 1\n>> > +#define R_TIM_BGLOADVAL 2\n>> > +#define R_TIM_CTRL 3\n>> > +#define R_TIM_RIS 4\n>> > +#define R_TIM_MIS 5\n>> > +\n>> > +#define TIMER_CTRL_ENBL (1 << 0)\n>> > +#define TIMER_CTRL_ONESHOT (1 << 1)\n>> > +#define TIMER_CTRL_INTR (1 << 2)\n>> > +#define TIMER_RIS_ACK (1 << 0)\n>> > +#define TIMER_RST_CLR (1 << 6)\n>> > +#define TIMER_MODE (1 << 0)\n>> > +\n>> > +static void timer_update_irq(struct Msf2Timer *st)\n>> > +{\n>> > + bool isr, ier;\n>> > +\n>> > + isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK);\n>> > + ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR);\n>> > + qemu_set_irq(st->irq, (ier && isr));\n>> > +}\n>> > +\n>> > +static void timer_update(struct Msf2Timer *st)\n>> > +{\n>> > + uint64_t count;\n>> > +\n>> > + if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL)) {\n>> > + ptimer_stop(st->ptimer);\n>> > + return;\n>> > + }\n>> > +\n>> > + count = st->regs[R_TIM_LOADVAL];\n>> > + ptimer_set_limit(st->ptimer, count, 1);\n>> > + ptimer_run(st->ptimer, 1);\n>> > +}\n>> > +\n>> > +static uint64_t\n>> > +timer_read(void *opaque, hwaddr offset, unsigned int size)\n>> > +{\n>> > + MSSTimerState *t = opaque;\n>> > + hwaddr addr;\n>> > + struct Msf2Timer *st;\n>> > + uint32_t ret = 0;\n>> > + int timer = 0;\n>> > + int isr;\n>> > + int ier;\n>> > +\n>> > + addr = offset >> 2;\n>> > + /*\n>> > + * Two independent timers has same base address.\n>> > + * Based on address passed figure out which timer is being used.\n>> > + */\n>> > + if ((addr >= R_TIM1_MAX) && (addr < NUM_TIMERS * R_TIM1_MAX)) {\n>> > + timer = 1;\n>> > + addr -= R_TIM1_MAX;\n>> > + }\n>> > +\n>> > + st = &t->timers[timer];\n>> > +\n>> > + switch (addr) {\n>> > + case R_TIM_VAL:\n>> > + ret = ptimer_get_count(st->ptimer);\n>> > + break;\n>> > +\n>> > + case R_TIM_MIS:\n>> > + isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK);\n>> > + ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR);\n>> > + ret = ier & isr;\n>> > + break;\n>> > +\n>> > + default:\n>> > + if (addr < R_TIM1_MAX) {\n>> > + ret = st->regs[addr];\n>> > + } else {\n>> > + qemu_log_mask(LOG_GUEST_ERROR,\n>> > + TYPE_MSS_TIMER\": 64-bit mode not supported\\n\");\n>> > + return ret;\n>> > + }\n>> > + break;\n>> > + }\n>> > +\n>> > + DB_PRINT(\"timer=%d 0x%\" HWADDR_PRIx \"=0x%\" PRIx32, timer, offset,\n>> > + ret);\n>> > + return ret;\n>> > +}\n>> > +\n>> > +static void\n>> > +timer_write(void *opaque, hwaddr offset,\n>> > + uint64_t val64, unsigned int size)\n>> > +{\n>> > + MSSTimerState *t = opaque;\n>> > + hwaddr addr;\n>> > + struct Msf2Timer *st;\n>> > + int timer = 0;\n>> > + uint32_t value = val64;\n>> > +\n>> > + addr = offset >> 2;\n>> > + /*\n>> > + * Two independent timers has same base address.\n>> > + * Based on addr passed figure out which timer is being used.\n>> > + */\n>> > + if ((addr >= R_TIM1_MAX) && (addr < NUM_TIMERS * R_TIM1_MAX)) {\n>> > + timer = 1;\n>> > + addr -= R_TIM1_MAX;\n>> > + }\n>> > +\n>> > + st = &t->timers[timer];\n>> > +\n>> > + DB_PRINT(\"addr=0x%\" HWADDR_PRIx \" val=0x%\" PRIx32 \" (timer=%d)\",\n>> > offset,\n>> > + value, timer);\n>> > +\n>> > + switch (addr) {\n>> > + case R_TIM_CTRL:\n>> > + st->regs[R_TIM_CTRL] = value;\n>> > + timer_update(st);\n>> > + break;\n>> > +\n>> > + case R_TIM_RIS:\n>> > + if (value & TIMER_RIS_ACK) {\n>> > + st->regs[R_TIM_RIS] &= ~TIMER_RIS_ACK;\n>> > + }\n>> > + break;\n>> > +\n>> > + case R_TIM_LOADVAL:\n>> > + st->regs[R_TIM_LOADVAL] = value;\n>> > + if (st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL) {\n>> > + timer_update(st);\n>> > + }\n>> > + break;\n>> > +\n>> > + case R_TIM_BGLOADVAL:\n>> > + st->regs[R_TIM_BGLOADVAL] = value;\n>> > + st->regs[R_TIM_LOADVAL] = value;\n>> > + break;\n>> > +\n>> > + case R_TIM_VAL:\n>> > + case R_TIM_MIS:\n>> > + break;\n>> > +\n>> > + default:\n>> > + if (addr < R_TIM1_MAX) {\n>> > + st->regs[addr] = value;\n>> > + } else {\n>> > + qemu_log_mask(LOG_GUEST_ERROR,\n>> > + TYPE_MSS_TIMER\": 64-bit mode not supported\\n\");\n>> > + return;\n>> > + }\n>> > + break;\n>> > + }\n>> > + timer_update_irq(st);\n>> > +}\n>> > +\n>> > +static const MemoryRegionOps timer_ops = {\n>> > + .read = timer_read,\n>> > + .write = timer_write,\n>> > + .endianness = DEVICE_NATIVE_ENDIAN,\n>> > + .valid = {\n>> > + .min_access_size = 1,\n>> > + .max_access_size = 4\n>> > + }\n>> > +};\n>> > +\n>> > +static void timer_hit(void *opaque)\n>> > +{\n>> > + struct Msf2Timer *st = opaque;\n>> > +\n>> > + st->regs[R_TIM_RIS] |= TIMER_RIS_ACK;\n>> > +\n>> > + if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ONESHOT)) {\n>> > + timer_update(st);\n>> > + }\n>> > + timer_update_irq(st);\n>> > +}\n>> > +\n>> > +static void mss_timer_init(Object *obj)\n>> > +{\n>> > + MSSTimerState *t = MSS_TIMER(obj);\n>> > + int i;\n>> > +\n>> > + /* Init all the ptimers. */\n>> > + for (i = 0; i < NUM_TIMERS; i++) {\n>> > + struct Msf2Timer *st = &t->timers[i];\n>> > +\n>> > + st->bh = qemu_bh_new(timer_hit, st);\n>> > + st->ptimer = ptimer_init(st->bh, PTIMER_POLICY_DEFAULT);\n>> > + ptimer_set_freq(st->ptimer, t->freq_hz);\n>> > + sysbus_init_irq(SYS_BUS_DEVICE(obj), &st->irq);\n>> > + }\n>> > +\n>> > + memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t,\n>> > TYPE_MSS_TIMER,\n>> > + NUM_TIMERS * R_TIM1_MAX * 4);\n>> > + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &t->mmio);\n>> > +}\n>> > +\n>> > +static const VMStateDescription vmstate_timers = {\n>> > + .name = \"mss-timer-block\",\n>> > + .version_id = 1,\n>> > + .minimum_version_id = 1,\n>> > + .fields = (VMStateField[]) {\n>> > + VMSTATE_PTIMER(ptimer, struct Msf2Timer),\n>> > + VMSTATE_UINT32_ARRAY(regs, struct Msf2Timer, R_TIM1_MAX),\n>> > + VMSTATE_END_OF_LIST()\n>> > + }\n>> > +};\n>> > +\n>> > +static const VMStateDescription vmstate_mss_timer = {\n>> > + .name = TYPE_MSS_TIMER,\n>> > + .version_id = 1,\n>> > + .minimum_version_id = 1,\n>> > + .fields = (VMStateField[]) {\n>> > + VMSTATE_UINT32(freq_hz, MSSTimerState),\n>> > + VMSTATE_STRUCT_ARRAY(timers, MSSTimerState, NUM_TIMERS, 0,\n>> > + vmstate_timers, struct Msf2Timer),\n>> > + VMSTATE_END_OF_LIST()\n>> > + }\n>> > +};\n>> > +\n>> > +static Property mss_timer_properties[] = {\n>> > + /* Libero GUI shows 100Mhz as default for clocks */\n>> > + DEFINE_PROP_UINT32(\"clock-frequency\", MSSTimerState, freq_hz,\n>> > + 100 * 1000000),\n>> > + DEFINE_PROP_END_OF_LIST(),\n>> > +};\n>> > +\n>> > +static void mss_timer_class_init(ObjectClass *klass, void *data)\n>> > +{\n>> > + DeviceClass *dc = DEVICE_CLASS(klass);\n>> > +\n>> > + dc->props = mss_timer_properties;\n>> > + dc->vmsd = &vmstate_mss_timer;\n>> > +}\n>> > +\n>> > +static const TypeInfo mss_timer_info = {\n>> > + .name = TYPE_MSS_TIMER,\n>> > + .parent = TYPE_SYS_BUS_DEVICE,\n>> > + .instance_size = sizeof(MSSTimerState),\n>> > + .instance_init = mss_timer_init,\n>> > + .class_init = mss_timer_class_init,\n>> > +};\n>> > +\n>> > +static void mss_timer_register_types(void)\n>> > +{\n>> > + type_register_static(&mss_timer_info);\n>> > +}\n>> > +\n>> > +type_init(mss_timer_register_types)\n>> > diff --git a/include/hw/timer/mss-timer.h b/include/hw/timer/mss-timer.h\n>> > new file mode 100644\n>> > index 0000000..d15d173\n>> > --- /dev/null\n>> > +++ b/include/hw/timer/mss-timer.h\n>> > @@ -0,0 +1,64 @@\n>> > +/*\n>> > + * Microsemi SmartFusion2 Timer.\n>> > + *\n>> > + * Copyright (c) 2017 Subbaraya Sundeep \n>> > + *\n>> > + * Permission is hereby granted, free of charge, to any person\n>> > obtaining a copy\n>> > + * of this software and associated documentation files (the\n>> > \"Software\"), to deal\n>> > + * in the Software without restriction, including without limitation\n>> > the rights\n>> > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or\n>> > sell\n>> > + * copies of the Software, and to permit persons to whom the Software\n>> > is\n>> > + * furnished to do so, subject to the following conditions:\n>> > + *\n>> > + * The above copyright notice and this permission notice shall be\n>> > included in\n>> > + * all copies or substantial portions of the Software.\n>> > + *\n>> > + * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n>> > EXPRESS OR\n>> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n>> > MERCHANTABILITY,\n>> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT\n>> > SHALL\n>> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR\n>> > OTHER\n>> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,\n>> > ARISING FROM,\n>> > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n>> > DEALINGS IN\n>> > + * THE SOFTWARE.\n>> > + */\n>> > +\n>> > +#ifndef HW_MSS_TIMER_H\n>> > +#define HW_MSS_TIMER_H\n>> > +\n>> > +#include \"hw/sysbus.h\"\n>> > +#include \"hw/ptimer.h\"\n>> > +\n>> > +#define TYPE_MSS_TIMER \"mss-timer\"\n>> > +#define MSS_TIMER(obj) OBJECT_CHECK(MSSTimerState, \\\n>> > + (obj), TYPE_MSS_TIMER)\n>> > +\n>> > +/*\n>> > + * There are two 32-bit down counting timers.\n>> > + * Timers 1 and 2 can be concatenated into a single 64-bit Timer\n>> > + * that operates either in Periodic mode or in One-shot mode.\n>> > + * Writing 1 to the TIM64_MODE register bit 0 sets the Timers in 64-bit\n>> > mode.\n>> > + * In 64-bit mode, writing to the 32-bit registers has no effect.\n>> > + * Similarly, in 32-bit mode, writing to the 64-bit mode registers\n>> > + * has no effect. Only two 32-bit timers are supported currently.\n>> > + */\n>> > +#define NUM_TIMERS 2\n>> > +\n>> > +#define R_TIM1_MAX 6\n>> > +\n>> > +struct Msf2Timer {\n>> > + QEMUBH *bh;\n>> > + ptimer_state *ptimer;\n>> > +\n>> > + uint32_t regs[R_TIM1_MAX];\n>> > + qemu_irq irq;\n>> > +};\n>> > +\n>> > +typedef struct MSSTimerState {\n>> > + SysBusDevice parent_obj;\n>> > +\n>> > + MemoryRegion mmio;\n>> > + uint32_t freq_hz;\n>> > + struct Msf2Timer timers[NUM_TIMERS];\n>> > +} MSSTimerState;\n>> > +\n>> > +#endif /* HW_MSS_TIMER_H */\n>> > --\n>> > 2.5.0\n>> >\n>\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"mXHF0XBb\"; dkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xhjGb1t70z9s9Y\n\tfor ;\n\tWed, 30 Aug 2017 07:59:35 +1000 (AEST)","from localhost ([::1]:47186 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dmoXl-0003Ab-5G\n\tfor incoming@patchwork.ozlabs.org; Tue, 29 Aug 2017 17:59:33 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:37176)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1dmoX2-00037N-OH\n\tfor qemu-devel@nongnu.org; Tue, 29 Aug 2017 17:58:50 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1dmoX0-0006oR-RM\n\tfor qemu-devel@nongnu.org; Tue, 29 Aug 2017 17:58:48 -0400","from mail-wr0-x244.google.com ([2a00:1450:400c:c0c::244]:33423)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from )\n\tid 1dmoX0-0006no-Hi; Tue, 29 Aug 2017 17:58:46 -0400","by mail-wr0-x244.google.com with SMTP id k94so3100688wrc.0;\n\tTue, 29 Aug 2017 14:58:44 -0700 (PDT)","by 10.28.191.130 with HTTP; Tue, 29 Aug 2017 14:58:12 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=mime-version:in-reply-to:references:from:date:message-id:subject:to\n\t:cc; bh=0mMaRvQMLvANVKS8/1TyDDjz1flSBsv3PqyDI0cY/bM=;\n\tb=mXHF0XBbIbbvkgMvcYeb/ZWwZtqjGtVHKJi/sQzZGr9VyQ/FmNKCLVX59wHjypLmzo\n\tXPDCnhuABIEkLFhUkuea52hVJZ7jd147aiAZgn65Wt2eiSL5XFmLiMvCFZEd2GYlK718\n\to0T+wXuKvMlNxkSkYduVFVAFkiPU+hJU2w9YlCy/zDMTKLmjY3xIwo73raf3jBPNV1li\n\tovFGjuCPAVj0cgEDn40odj5dD8DMDeinwGO04masJFiMkuevXJ2WKj3Bmp2cZqcpLZOX\n\tf3ZEE2IlEuV0pIFvd4LVqq+9eVLVUguCF/rDlJOK6/wXpNMeZYDMTnHp1ID3UYvWXpdh\n\tzIJw==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:mime-version:in-reply-to:references:from:date\n\t:message-id:subject:to:cc;\n\tbh=0mMaRvQMLvANVKS8/1TyDDjz1flSBsv3PqyDI0cY/bM=;\n\tb=skvREKzxfVaQiF1/k/r/Nj44nsYVnlnVTeqWfi2ek25rSbJWEfweN9quoQi9Eb5BL7\n\tUhoCoPu1byQ1HYg3YtivjQoEN8BRVrlsv3iVf3PCT+0g6ZQuX+HYiUlDeeWSce8SLwWR\n\tN/nohFiKAoE8o6rc/NNL7SKSql5BjjTNmzFi13eg1JnoSfsfSU4IH6fuB9Ms1tCk/Xym\n\t64ykQd/xqocbqavjIjscpBG6eDgpCZgQdoBkKBtzpTOiyyKyE4Ee6EWwgwxcoc9+NdBP\n\tw3RoAqcPIhhNmXDOqDHQ9puZ636ha7bV9ruuBQgnKGE0q/G/kdLH3yjWXuXPe3G7bXhr\n\tPIMw==","X-Gm-Message-State":"AHYfb5gyhCuR+q4WoTR+8hi7IOW4sMnX47oDkQGLsAY8cXbJg/mJvP3c\n\t3gTcez+08I6X71FIdR5aJDVnxYCdUA==","X-Received":"by 10.223.163.87 with SMTP id d23mr953124wrb.84.1504043923639;\n\tTue, 29 Aug 2017 14:58:43 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"","References":"<1503938283-12404-1-git-send-email-sundeep.lkml@gmail.com>\n\t<1503938283-12404-2-git-send-email-sundeep.lkml@gmail.com>\n\t\n\t","From":"Alistair Francis ","Date":"Tue, 29 Aug 2017 14:58:12 -0700","Message-ID":"","To":"sundeep subbaraya ","Content-Type":"text/plain; charset=\"UTF-8\"","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2a00:1450:400c:c0c::244","Subject":"Re: [Qemu-devel] [Qemu devel v7 PATCH 1/5] msf2: Add Smartfusion2\n\tSystem timer","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Peter Maydell , =?utf-8?q?Philippe_Mathieu-D?=\n\t=?utf-8?b?YXVkw6k=?= , \tqemu-arm ,\n\t\"qemu-devel@nongnu.org Developers\" , \n\tPeter Crosthwaite ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}}]