[{"id":1771097,"web_url":"http://patchwork.ozlabs.org/comment/1771097/","msgid":"<87wp4urbp5.fsf@free-electrons.com>","list_archive_url":null,"date":"2017-09-19T14:43:18","subject":"Re: [PATCH 1/2] bus: mbus: fix window size calculation for 4GB\n\twindows","submitter":{"id":15771,"url":"http://patchwork.ozlabs.org/api/people/15771/","name":"Gregory CLEMENT","email":"gregory.clement@free-electrons.com"},"content":"Hi Jan,\n \n On lun., août 28 2017, Jan Luebbe wrote:\n\n> At least the Armada XP SoC supports 4GB on a single DRAM window. Because\n> the size register values contain the actual size - 1, the MSB is set in\n> that case. For example, the SDRAM window's control register's value is\n> 0xffffffe1 for 4GB (bits 31 to 24 contain the size).\n>\n> The MBUS driver reads back each window's size from registers and\n> calculates the actual size as (control_reg | ~DDR_SIZE_MASK) + 1, which\n> overflows for 32 bit values, resulting in other miscalculations further\n> on (a bad RAM window for the CESA crypto engine calculated by\n> mvebu_mbus_setup_cpu_target_nooverlap() in my case).\n>\n> This patch changes the type in 'struct mbus_dram_window' from u32 to\n> u64, which allows us to keep using the same register calculation code in\n> most MBUS-using drivers (which calculate ->size - 1 again).\n>\n\nYour patch looks good, but as it is a fix we should also apply it on\nstable, could you provide the commit to fix?\n\nThanks,\n\nGregory\n\n> Signed-off-by: Jan Luebbe \n> ---\n> drivers/bus/mvebu-mbus.c | 2 +-\n> include/linux/mbus.h | 4 ++--\n> 2 files changed, 3 insertions(+), 3 deletions(-)\n>\n> diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c\n> index c7f396903184..70db4d5638a6 100644\n> --- a/drivers/bus/mvebu-mbus.c\n> +++ b/drivers/bus/mvebu-mbus.c\n> @@ -720,7 +720,7 @@ mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus)\n> \t\t\tif (mbus->hw_io_coherency)\n> \t\t\t\tw->mbus_attr |= ATTR_HW_COHERENCY;\n> \t\t\tw->base = base & DDR_BASE_CS_LOW_MASK;\n> -\t\t\tw->size = (size | ~DDR_SIZE_MASK) + 1;\n> +\t\t\tw->size = (u64)(size | ~DDR_SIZE_MASK) + 1;\n> \t\t}\n> \t}\n> \tmvebu_mbus_dram_info.num_cs = cs;\n> diff --git a/include/linux/mbus.h b/include/linux/mbus.h\n> index 0d3f14fd2621..4773145246ed 100644\n> --- a/include/linux/mbus.h\n> +++ b/include/linux/mbus.h\n> @@ -31,8 +31,8 @@ struct mbus_dram_target_info\n> \tstruct mbus_dram_window {\n> \t\tu8\tcs_index;\n> \t\tu8\tmbus_attr;\n> -\t\tu32\tbase;\n> -\t\tu32\tsize;\n> +\t\tu64\tbase;\n> +\t\tu64\tsize;\n> \t} cs[4];\n> };\n> \n> -- \n> 2.11.0\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xxQbs5W6Hz9s7m\n\tfor ;\n\tWed, 20 Sep 2017 00:43:37 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751754AbdISOnV convert rfc822-to-8bit (ORCPT\n\t);\n\tTue, 19 Sep 2017 10:43:21 -0400","from mail.free-electrons.com ([62.4.15.54]:40556 \"EHLO\n\tmail.free-electrons.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751751AbdISOnT (ORCPT\n\t); Tue, 19 Sep 2017 10:43:19 -0400","by mail.free-electrons.com (Postfix, from userid 110)\n\tid D10D420987; Tue, 19 Sep 2017 16:43:17 +0200 (CEST)","from localhost (242.171.71.37.rev.sfr.net [37.71.171.242])\n\tby mail.free-electrons.com (Postfix) with ESMTPSA id A7088208C1;\n\tTue, 19 Sep 2017 16:43:17 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tmail.free-electrons.com","X-Spam-Level":"","X-Spam-Status":"No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT,\n\tURIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0","From":"Gregory CLEMENT ","To":"Jan Luebbe ","Cc":"Andrew Lunn ,\n\tThomas Petazzoni ,\n\tJason Cooper , linux-pci@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,\n\tkernel@pengutronix.de","Subject":"Re: [PATCH 1/2] bus: mbus: fix window size calculation for 4GB\n\twindows","References":"<20170828152517.24506-1-jlu@pengutronix.de>\n\t<20170828152517.24506-2-jlu@pengutronix.de>","Date":"Tue, 19 Sep 2017 16:43:18 +0200","In-Reply-To":"<20170828152517.24506-2-jlu@pengutronix.de> (Jan Luebbe's\n\tmessage of \"Mon, 28 Aug 2017 17:25:16 +0200\")","Message-ID":"<87wp4urbp5.fsf@free-electrons.com>","User-Agent":"Gnus/5.13 (Gnus v5.13) Emacs/25.2 (gnu/linux)","MIME-Version":"1.0","Content-Type":"text/plain; charset=utf-8","Content-Transfer-Encoding":"8BIT","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"}},{"id":1772051,"web_url":"http://patchwork.ozlabs.org/comment/1772051/","msgid":"<20170920163716.l6kpf56ig5gfqzbi@pengutronix.de>","list_archive_url":null,"date":"2017-09-20T16:37:16","subject":"Re: [PATCH 1/2] bus: mbus: fix window size calculation for 4GB\n\twindows","submitter":{"id":1476,"url":"http://patchwork.ozlabs.org/api/people/1476/","name":"Uwe Kleine-König","email":"u.kleine-koenig@pengutronix.de"},"content":"On Tue, Sep 19, 2017 at 04:43:18PM +0200, Gregory CLEMENT wrote:\n> Hi Jan,\n> \n> On lun., août 28 2017, Jan Luebbe wrote:\n> \n> > At least the Armada XP SoC supports 4GB on a single DRAM window. Because\n> > the size register values contain the actual size - 1, the MSB is set in\n> > that case. For example, the SDRAM window's control register's value is\n> > 0xffffffe1 for 4GB (bits 31 to 24 contain the size).\n> >\n> > The MBUS driver reads back each window's size from registers and\n> > calculates the actual size as (control_reg | ~DDR_SIZE_MASK) + 1, which\n> > overflows for 32 bit values, resulting in other miscalculations further\n> > on (a bad RAM window for the CESA crypto engine calculated by\n> > mvebu_mbus_setup_cpu_target_nooverlap() in my case).\n> >\n> > This patch changes the type in 'struct mbus_dram_window' from u32 to\n> > u64, which allows us to keep using the same register calculation code in\n> > most MBUS-using drivers (which calculate ->size - 1 again).\n> >\n> \n> Your patch looks good, but as it is a fix we should also apply it on\n> stable, could you provide the commit to fix?\n\nIt was there just from the start: the .c file was introduced in\nv3.10-rc1~64^2~1^2~8^2~2 and already did that 32 bit calculus.\n\nBest regards\nUwe","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xy54d24CZz9t2V\n\tfor ;\n\tThu, 21 Sep 2017 02:37:21 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751436AbdITQhT (ORCPT );\n\tWed, 20 Sep 2017 12:37:19 -0400","from metis.ext.4.pengutronix.de ([92.198.50.35]:60465 \"EHLO\n\tmetis.ext.4.pengutronix.de\" rhost-flags-OK-OK-OK-OK)\n\tby vger.kernel.org with ESMTP id S1750973AbdITQhS (ORCPT\n\t); Wed, 20 Sep 2017 12:37:18 -0400","from [2001:67c:670:100:5054:ff:fe2a:3aa]\n\t(helo=pty.hi.pengutronix.de)\n\tby metis.ext.pengutronix.de with esmtps\n\t(TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.84_2)\n\t(envelope-from )\n\tid 1duhzw-00010x-NU; Wed, 20 Sep 2017 18:37:16 +0200","from ukl by pty.hi.pengutronix.de with local (Exim 4.89)\n\t(envelope-from )\n\tid 1duhzw-00042x-8K; Wed, 20 Sep 2017 18:37:16 +0200"],"Date":"Wed, 20 Sep 2017 18:37:16 +0200","From":"Uwe =?iso-8859-1?q?Kleine-K=F6nig?= ","To":"Gregory CLEMENT ","Cc":"Jan Luebbe ,\n\tThomas Petazzoni ,\n\tAndrew Lunn ,\n\tJason Cooper , linux-pci@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org, kernel@pengutronix.de,\n\tlinux-arm-kernel@lists.infradead.org","Subject":"Re: [PATCH 1/2] bus: mbus: fix window size calculation for 4GB\n\twindows","Message-ID":"<20170920163716.l6kpf56ig5gfqzbi@pengutronix.de>","References":"<20170828152517.24506-1-jlu@pengutronix.de>\n\t<20170828152517.24506-2-jlu@pengutronix.de>\n\t<87wp4urbp5.fsf@free-electrons.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=iso-8859-1","Content-Disposition":"inline","Content-Transfer-Encoding":"8bit","In-Reply-To":"<87wp4urbp5.fsf@free-electrons.com>","User-Agent":"NeoMutt/20170113 (1.7.2)","X-SA-Exim-Connect-IP":"2001:67c:670:100:5054:ff:fe2a:3aa","X-SA-Exim-Mail-From":"ukl@pengutronix.de","X-SA-Exim-Scanned":"No (on metis.ext.pengutronix.de);\n\tSAEximRunCond expanded to false","X-PTX-Original-Recipient":"linux-pci@vger.kernel.org","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"}}]