[{"id":1775055,"web_url":"http://patchwork.ozlabs.org/comment/1775055/","msgid":"<20170925235658.GK15970@bhelgaas-glaptop.roam.corp.google.com>","list_archive_url":null,"date":"2017-09-25T23:56:58","subject":"Re: [PATCH 2/2] PCI: mvebu: Check DRAM window size","submitter":{"id":67298,"url":"http://patchwork.ozlabs.org/api/people/67298/","name":"Bjorn Helgaas","email":"helgaas@kernel.org"},"content":"On Mon, Aug 28, 2017 at 05:25:17PM +0200, Jan Luebbe wrote:\n> The sum of the DRAM windows may exceed 4GB (at least on Armada XP).\n> Return an error in that case.\n> \n> Signed-off-by: Jan Luebbe \n\nLooking for an ack from Thomas or Jason before applying this...\n\n> ---\n> drivers/pci/host/pci-mvebu.c | 27 ++++++++++++++++++++++-----\n> 1 file changed, 22 insertions(+), 5 deletions(-)\n> \n> diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c\n> index f353a6eb2f01..5d74af81d104 100644\n> --- a/drivers/pci/host/pci-mvebu.c\n> +++ b/drivers/pci/host/pci-mvebu.c\n> @@ -206,10 +206,10 @@ static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr)\n> * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks\n> * WIN[0-3] -> DRAM bank[0-3]\n> */\n> -static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)\n> +static int mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)\n> {\n> \tconst struct mbus_dram_target_info *dram;\n> -\tu32 size;\n> +\tu64 size;\n> \tint i;\n> \n> \tdram = mv_mbus_dram_info();\n> @@ -252,19 +252,32 @@ static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)\n> \tif ((size & (size - 1)) != 0)\n> \t\tsize = 1 << fls(size);\n> \n> +\tif (size > 0x100000000) {\n> +\t\tdev_err(&port->pcie->pdev->dev,\n> +\t\t\t\"Could not configure DRAM window (too large): 0x%llx\\n\",\n> +\t\t\tsize);\n> +\n> +\t\treturn -EINVAL;\n> +\t}\n> +\n> \t/* Setup BAR[1] to all DRAM banks. */\n> \tmvebu_writel(port, dram->cs[0].base, PCIE_BAR_LO_OFF(1));\n> \tmvebu_writel(port, 0, PCIE_BAR_HI_OFF(1));\n> \tmvebu_writel(port, ((size - 1) & 0xffff0000) | 1,\n> \t\t PCIE_BAR_CTRL_OFF(1));\n> +\n> +\treturn 0;\n> }\n> \n> -static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)\n> +static int mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)\n> {\n> \tu32 cmd, mask;\n> +\tint ret;\n> \n> \t/* Point PCIe unit MBUS decode windows to DRAM space. */\n> -\tmvebu_pcie_setup_wins(port);\n> +\tret = mvebu_pcie_setup_wins(port);\n> +\tif (ret)\n> +\t\treturn ret;\n> \n> \t/* Master + slave enable. */\n> \tcmd = mvebu_readl(port, PCIE_CMD_OFF);\n> @@ -277,6 +290,8 @@ static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)\n> \tmask = mvebu_readl(port, PCIE_MASK_OFF);\n> \tmask |= PCIE_MASK_ENABLE_INTS;\n> \tmvebu_writel(port, mask, PCIE_MASK_OFF);\n> +\n> +\treturn 0;\n> }\n> \n> static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port,\n> @@ -882,7 +897,9 @@ static int mvebu_pcie_setup(int nr, struct pci_sys_data *sys)\n> \n> \t\tif (!port->base)\n> \t\t\tcontinue;\n> -\t\tmvebu_pcie_setup_hw(port);\n> +\t\terr = mvebu_pcie_setup_hw(port);\n> +\t\tif (err)\n> +\t\t\treturn 0;\n> \t}\n> \n> \treturn 1;\n> -- \n> 2.11.0\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=)","mail.kernel.org;\n\tdmarc=none (p=none dis=none) header.from=kernel.org","mail.kernel.org;\n\tspf=none smtp.mailfrom=helgaas@kernel.org"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y1Lbg2Q98z9sRV\n\tfor ;\n\tTue, 26 Sep 2017 09:57:03 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S966282AbdIYX5B (ORCPT );\n\tMon, 25 Sep 2017 19:57:01 -0400","from mail.kernel.org ([198.145.29.99]:55586 \"EHLO mail.kernel.org\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S965398AbdIYX5A (ORCPT );\n\tMon, 25 Sep 2017 19:57:00 -0400","from localhost (unknown [69.71.4.159])\n\t(using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits))\n\t(No client certificate requested)\n\tby mail.kernel.org (Postfix) with ESMTPSA id F351C21894;\n\tMon, 25 Sep 2017 23:56:59 +0000 (UTC)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mail.kernel.org F351C21894","Date":"Mon, 25 Sep 2017 18:56:58 -0500","From":"Bjorn Helgaas ","To":"Jan Luebbe ","Cc":"Gregory Clement ,\n\tAndrew Lunn ,\n\tThomas Petazzoni ,\n\tJason Cooper , linux-pci@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,\n\tkernel@pengutronix.de","Subject":"Re: [PATCH 2/2] PCI: mvebu: Check DRAM window size","Message-ID":"<20170925235658.GK15970@bhelgaas-glaptop.roam.corp.google.com>","References":"<20170828152517.24506-1-jlu@pengutronix.de>\n\t<20170828152517.24506-3-jlu@pengutronix.de>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170828152517.24506-3-jlu@pengutronix.de>","User-Agent":"Mutt/1.5.21 (2010-09-15)","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"}},{"id":1781022,"web_url":"http://patchwork.ozlabs.org/comment/1781022/","msgid":"<20171005211650.GZ25517@bhelgaas-glaptop.roam.corp.google.com>","list_archive_url":null,"date":"2017-10-05T21:16:50","subject":"Re: [PATCH 2/2] PCI: mvebu: Check DRAM window size","submitter":{"id":67298,"url":"http://patchwork.ozlabs.org/api/people/67298/","name":"Bjorn Helgaas","email":"helgaas@kernel.org"},"content":"On Mon, Sep 25, 2017 at 06:56:58PM -0500, Bjorn Helgaas wrote:\n> On Mon, Aug 28, 2017 at 05:25:17PM +0200, Jan Luebbe wrote:\n> > The sum of the DRAM windows may exceed 4GB (at least on Armada XP).\n> > Return an error in that case.\n> > \n> > Signed-off-by: Jan Luebbe \n> \n> Looking for an ack from Thomas or Jason before applying this...\n\nPing, I think I'm stil waiting for an ack for this. Or did I miss it?\n\n> > ---\n> > drivers/pci/host/pci-mvebu.c | 27 ++++++++++++++++++++++-----\n> > 1 file changed, 22 insertions(+), 5 deletions(-)\n> > \n> > diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c\n> > index f353a6eb2f01..5d74af81d104 100644\n> > --- a/drivers/pci/host/pci-mvebu.c\n> > +++ b/drivers/pci/host/pci-mvebu.c\n> > @@ -206,10 +206,10 @@ static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr)\n> > * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks\n> > * WIN[0-3] -> DRAM bank[0-3]\n> > */\n> > -static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)\n> > +static int mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)\n> > {\n> > \tconst struct mbus_dram_target_info *dram;\n> > -\tu32 size;\n> > +\tu64 size;\n> > \tint i;\n> > \n> > \tdram = mv_mbus_dram_info();\n> > @@ -252,19 +252,32 @@ static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)\n> > \tif ((size & (size - 1)) != 0)\n> > \t\tsize = 1 << fls(size);\n> > \n> > +\tif (size > 0x100000000) {\n> > +\t\tdev_err(&port->pcie->pdev->dev,\n> > +\t\t\t\"Could not configure DRAM window (too large): 0x%llx\\n\",\n> > +\t\t\tsize);\n> > +\n> > +\t\treturn -EINVAL;\n> > +\t}\n> > +\n> > \t/* Setup BAR[1] to all DRAM banks. */\n> > \tmvebu_writel(port, dram->cs[0].base, PCIE_BAR_LO_OFF(1));\n> > \tmvebu_writel(port, 0, PCIE_BAR_HI_OFF(1));\n> > \tmvebu_writel(port, ((size - 1) & 0xffff0000) | 1,\n> > \t\t PCIE_BAR_CTRL_OFF(1));\n> > +\n> > +\treturn 0;\n> > }\n> > \n> > -static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)\n> > +static int mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)\n> > {\n> > \tu32 cmd, mask;\n> > +\tint ret;\n> > \n> > \t/* Point PCIe unit MBUS decode windows to DRAM space. */\n> > -\tmvebu_pcie_setup_wins(port);\n> > +\tret = mvebu_pcie_setup_wins(port);\n> > +\tif (ret)\n> > +\t\treturn ret;\n> > \n> > \t/* Master + slave enable. */\n> > \tcmd = mvebu_readl(port, PCIE_CMD_OFF);\n> > @@ -277,6 +290,8 @@ static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)\n> > \tmask = mvebu_readl(port, PCIE_MASK_OFF);\n> > \tmask |= PCIE_MASK_ENABLE_INTS;\n> > \tmvebu_writel(port, mask, PCIE_MASK_OFF);\n> > +\n> > +\treturn 0;\n> > }\n> > \n> > static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port,\n> > @@ -882,7 +897,9 @@ static int mvebu_pcie_setup(int nr, struct pci_sys_data *sys)\n> > \n> > \t\tif (!port->base)\n> > \t\t\tcontinue;\n> > -\t\tmvebu_pcie_setup_hw(port);\n> > +\t\terr = mvebu_pcie_setup_hw(port);\n> > +\t\tif (err)\n> > +\t\t\treturn 0;\n> > \t}\n> > \n> > \treturn 1;\n> > -- \n> > 2.11.0\n> > \n> \n> _______________________________________________\n> linux-arm-kernel mailing list\n> linux-arm-kernel@lists.infradead.org\n> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=)","mail.kernel.org;\n\tdmarc=none (p=none dis=none) header.from=kernel.org","mail.kernel.org;\n\tspf=none smtp.mailfrom=helgaas@kernel.org"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y7QZJ1FMbz9sNw\n\tfor ;\n\tFri, 6 Oct 2017 08:16:56 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752228AbdJEVQy (ORCPT );\n\tThu, 5 Oct 2017 17:16:54 -0400","from mail.kernel.org ([198.145.29.99]:53882 \"EHLO mail.kernel.org\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1751408AbdJEVQx (ORCPT );\n\tThu, 5 Oct 2017 17:16:53 -0400","from localhost (unknown [64.22.228.164])\n\t(using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits))\n\t(No client certificate requested)\n\tby mail.kernel.org (Postfix) with ESMTPSA id 7DE9821909;\n\tThu, 5 Oct 2017 21:16:52 +0000 (UTC)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mail.kernel.org 7DE9821909","Date":"Thu, 5 Oct 2017 16:16:50 -0500","From":"Bjorn Helgaas ","To":"Jan Luebbe ","Cc":"Thomas Petazzoni ,\n\tAndrew Lunn ,\n\tJason Cooper , linux-pci@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org, kernel@pengutronix.de,\n\tGregory Clement ,\n\tlinux-arm-kernel@lists.infradead.org","Subject":"Re: [PATCH 2/2] PCI: mvebu: Check DRAM window size","Message-ID":"<20171005211650.GZ25517@bhelgaas-glaptop.roam.corp.google.com>","References":"<20170828152517.24506-1-jlu@pengutronix.de>\n\t<20170828152517.24506-3-jlu@pengutronix.de>\n\t<20170925235658.GK15970@bhelgaas-glaptop.roam.corp.google.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170925235658.GK15970@bhelgaas-glaptop.roam.corp.google.com>","User-Agent":"Mutt/1.5.21 (2010-09-15)","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"}},{"id":1799928,"web_url":"http://patchwork.ozlabs.org/comment/1799928/","msgid":"<20171106191749.GC31930@bhelgaas-glaptop.roam.corp.google.com>","list_archive_url":null,"date":"2017-11-06T19:17:49","subject":"Re: [PATCH 2/2] PCI: mvebu: Check DRAM window size","submitter":{"id":67298,"url":"http://patchwork.ozlabs.org/api/people/67298/","name":"Bjorn Helgaas","email":"helgaas@kernel.org"},"content":"On Thu, Oct 05, 2017 at 04:16:50PM -0500, Bjorn Helgaas wrote:\n> On Mon, Sep 25, 2017 at 06:56:58PM -0500, Bjorn Helgaas wrote:\n> > On Mon, Aug 28, 2017 at 05:25:17PM +0200, Jan Luebbe wrote:\n> > > The sum of the DRAM windows may exceed 4GB (at least on Armada XP).\n> > > Return an error in that case.\n> > > \n> > > Signed-off-by: Jan Luebbe \n> > \n> > Looking for an ack from Thomas or Jason before applying this...\n> \n> Ping, I think I'm stil waiting for an ack for this. Or did I miss it?\n\nI'm dropping this. Please repost it with the appropriate acks if it's\nstill needed.\n\n> > > ---\n> > > drivers/pci/host/pci-mvebu.c | 27 ++++++++++++++++++++++-----\n> > > 1 file changed, 22 insertions(+), 5 deletions(-)\n> > > \n> > > diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c\n> > > index f353a6eb2f01..5d74af81d104 100644\n> > > --- a/drivers/pci/host/pci-mvebu.c\n> > > +++ b/drivers/pci/host/pci-mvebu.c\n> > > @@ -206,10 +206,10 @@ static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr)\n> > > * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks\n> > > * WIN[0-3] -> DRAM bank[0-3]\n> > > */\n> > > -static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)\n> > > +static int mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)\n> > > {\n> > > \tconst struct mbus_dram_target_info *dram;\n> > > -\tu32 size;\n> > > +\tu64 size;\n> > > \tint i;\n> > > \n> > > \tdram = mv_mbus_dram_info();\n> > > @@ -252,19 +252,32 @@ static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)\n> > > \tif ((size & (size - 1)) != 0)\n> > > \t\tsize = 1 << fls(size);\n> > > \n> > > +\tif (size > 0x100000000) {\n> > > +\t\tdev_err(&port->pcie->pdev->dev,\n> > > +\t\t\t\"Could not configure DRAM window (too large): 0x%llx\\n\",\n> > > +\t\t\tsize);\n> > > +\n> > > +\t\treturn -EINVAL;\n> > > +\t}\n> > > +\n> > > \t/* Setup BAR[1] to all DRAM banks. */\n> > > \tmvebu_writel(port, dram->cs[0].base, PCIE_BAR_LO_OFF(1));\n> > > \tmvebu_writel(port, 0, PCIE_BAR_HI_OFF(1));\n> > > \tmvebu_writel(port, ((size - 1) & 0xffff0000) | 1,\n> > > \t\t PCIE_BAR_CTRL_OFF(1));\n> > > +\n> > > +\treturn 0;\n> > > }\n> > > \n> > > -static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)\n> > > +static int mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)\n> > > {\n> > > \tu32 cmd, mask;\n> > > +\tint ret;\n> > > \n> > > \t/* Point PCIe unit MBUS decode windows to DRAM space. */\n> > > -\tmvebu_pcie_setup_wins(port);\n> > > +\tret = mvebu_pcie_setup_wins(port);\n> > > +\tif (ret)\n> > > +\t\treturn ret;\n> > > \n> > > \t/* Master + slave enable. */\n> > > \tcmd = mvebu_readl(port, PCIE_CMD_OFF);\n> > > @@ -277,6 +290,8 @@ static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)\n> > > \tmask = mvebu_readl(port, PCIE_MASK_OFF);\n> > > \tmask |= PCIE_MASK_ENABLE_INTS;\n> > > \tmvebu_writel(port, mask, PCIE_MASK_OFF);\n> > > +\n> > > +\treturn 0;\n> > > }\n> > > \n> > > static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port,\n> > > @@ -882,7 +897,9 @@ static int mvebu_pcie_setup(int nr, struct pci_sys_data *sys)\n> > > \n> > > \t\tif (!port->base)\n> > > \t\t\tcontinue;\n> > > -\t\tmvebu_pcie_setup_hw(port);\n> > > +\t\terr = mvebu_pcie_setup_hw(port);\n> > > +\t\tif (err)\n> > > +\t\t\treturn 0;\n> > > \t}\n> > > \n> > > \treturn 1;\n> > > -- \n> > > 2.11.0\n> > > \n> > \n> > _______________________________________________\n> > linux-arm-kernel mailing list\n> > linux-arm-kernel@lists.infradead.org\n> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=)","mail.kernel.org;\n\tdmarc=none (p=none dis=none) header.from=kernel.org","mail.kernel.org;\n\tspf=none smtp.mailfrom=helgaas@kernel.org"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yW2QB6rWhz9s7g\n\tfor ;\n\tTue, 7 Nov 2017 06:17:54 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S932641AbdKFTRx (ORCPT );\n\tMon, 6 Nov 2017 14:17:53 -0500","from mail.kernel.org ([198.145.29.99]:33836 \"EHLO mail.kernel.org\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S932576AbdKFTRw (ORCPT );\n\tMon, 6 Nov 2017 14:17:52 -0500","from localhost (unknown [69.55.156.246])\n\t(using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits))\n\t(No client certificate requested)\n\tby mail.kernel.org (Postfix) with ESMTPSA id 21F41218B4;\n\tMon, 6 Nov 2017 19:17:51 +0000 (UTC)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mail.kernel.org 21F41218B4","Date":"Mon, 6 Nov 2017 13:17:49 -0600","From":"Bjorn Helgaas ","To":"Jan Luebbe ","Cc":"Thomas Petazzoni ,\n\tAndrew Lunn ,\n\tJason Cooper , linux-pci@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org, kernel@pengutronix.de,\n\tGregory Clement ,\n\tlinux-arm-kernel@lists.infradead.org","Subject":"Re: [PATCH 2/2] PCI: mvebu: Check DRAM window size","Message-ID":"<20171106191749.GC31930@bhelgaas-glaptop.roam.corp.google.com>","References":"<20170828152517.24506-1-jlu@pengutronix.de>\n\t<20170828152517.24506-3-jlu@pengutronix.de>\n\t<20170925235658.GK15970@bhelgaas-glaptop.roam.corp.google.com>\n\t<20171005211650.GZ25517@bhelgaas-glaptop.roam.corp.google.com>","MIME-Version":"1.0","Content-Type":"text/plain; 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